Deposition Of Conductive Or Insulating Materials For Electrode (epo) Patents (Class 257/E21.477)
  • Patent number: 10388620
    Abstract: Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: August 20, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Shien Chen, Sheng-Yu Wu, Mirng-Ji Lii, Chita Chuang
  • Patent number: 9024457
    Abstract: A method for manufacturing a semiconductor device includes a first photolithography step of forming a first device pattern corresponding to a first pattern, and a plurality of alignment marks corresponding to a plurality of marks, upon a step of exposing the entire device region in one shot using a first mask including the first pattern and the plurality of marks, and a second photolithography step of, after the first photolithography step, forming second device patterns respectively corresponding to second patterns in a plurality of divided regions which form the device region, upon steps of individually exposing the plurality of divided regions using second masks each including the second pattern corresponding thereto.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: May 5, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Taikan Kanou
  • Patent number: 9013005
    Abstract: According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Syotaro Ono, Wataru Saito, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita, Toshiyuki Naka
  • Patent number: 8802579
    Abstract: A semiconductor process includes the following steps. A substrate is provided. A dielectric layer having a high dielectric constant is formed on the substrate, wherein the steps of forming the dielectric layer include: (a) a metallic oxide layer is formed; (b) an annealing process is performed to the metallic oxide layer; and the steps (a) and (b) are performed repeatedly. Otherwise, the present invention further provides a semiconductor structure formed by said semiconductor process.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: August 12, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Shao-Wei Wang, Yu-Ren Wang, Ying-Wei Yen
  • Patent number: 8754523
    Abstract: A surface-mounted electronic component including balls bonded to its front surface and, on the front surface, a protective resin layer having a thickness smaller than the ball height, wherein grooves extend in the resin layer between balls of the chip.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: June 17, 2014
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Romain Coffy
  • Patent number: 8753967
    Abstract: It is an object to solve inhibition of miniaturization of an element and complexity of a manufacturing process thereof. It is another object to provide a nonvolatile memory device and a semiconductor device having the memory device, in which data can be additionally written at a time besides the manufacturing time and in which forgery caused by rewriting of data can be prevented. It is further another object to provide an inexpensive nonvolatile memory device and semiconductor device. A memory element is manufactured in which a first conductive layer, a second conductive layer that is beside the first conductive layer, and conductive fine particles of each surface which is covered with an organic film are deposited over an insulating film. The conductive fine particles are deposited between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: June 17, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiharu Hirakata
  • Patent number: 8716101
    Abstract: A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chandra, Ronald G. Filippi, Wai-Kin Li, Ping-Chuan Wang, Chih-Chao Yang
  • Patent number: 8624620
    Abstract: A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: January 7, 2014
    Assignee: Advantest Corporation
    Inventors: Yasuo Tokunaga, Yoshio Komoto
  • Patent number: 8618537
    Abstract: A semiconductor device includes, in a first region over a semiconductor substrate, a first insulating layer, a first wiring, a second insulating layer, a third insulating layer, and a via and a second wiring embedded in the second insulating layer and the third insulating layer through a barrier metal, and includes, in a second region, the first insulating layer, a gate electrode, the second insulating layer, a semiconductor layer located, the third insulating layer, and a first electric conductor and a second electric conductor embedded in the third insulating layer so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view through a barrier metal and coupled to the semiconductor layer through the barrier metal.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: December 31, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kishou Kaneko, Naoya Inoue, Yoshihiro Hayashi
  • Patent number: 8592312
    Abstract: In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The applied voltage increases the selectivity of the deposition process used, thereby preventing the conductive capping layer from causing a short between the metal lines. The conductive capping layer may be deposited through electroplating, electrolessly, by atomic layer deposition (ALD), or by chemical vapor deposition (CVD), for example. In one embodiment, the present method is utilized to fabricate a semiconductor wafer. In one embodiment, the metal lines comprise copper lines, while the conductive capping layer may comprise tantalum or cobalt. The present method enables deposition of a capping layer having high electromigration resistance.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: November 26, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: E. Todd Ryan, John A. Iacoponi
  • Patent number: 8513674
    Abstract: A method of manufacturing of a semiconductor device (101) includes: a fine pattern forming step of forming p-type impurity regions (3, 4) and surface ohmic contact electrodes (5) using a stepper, after forming an N-type epitaxial layer (2) on a SiC single-crystal substrate (1); a protective film planarizing step of forming a protective film so as to cover the surface ohmic contact electrodes (5) and performing planarization of the protective film; a substrate thinning step of thinning the SiC single-crystal substrate (1); a backside ohmic contact electrode forming step of forming a backside ohmic contact electrode (7) on the SiC single-crystal substrate (1); a surface Schottky contact electrode forming step of forming a Schottky metal portion (8) connected to the p-type impurity regions (3, 4) and the surface ohmic contact electrodes (5); and a step of forming a surface pad electrode (9) that covers the Schottky metal portion (8).
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: August 20, 2013
    Assignee: Showa Denko K.K.
    Inventors: Akihiko Sugai, Yasuyuki Sakaguchi
  • Patent number: 8513804
    Abstract: Transparent electrodes are manufactured. In accordance with various example embodiments, a transparent electrode is manufactured by generating a solution including a composite material having nanotubes and a conjugated polymer, in which the nanotubes constitute a majority of the composite material by weight. The conjugated polymer is used to disperse the nanotubes in the solution, and the solution is coated onto a substrate to form an electrode including a network of the carbon nanotubes.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: August 20, 2013
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Sondra Hellstrom, Zhenan Bao
  • Patent number: 8507379
    Abstract: A semiconductor device and a manufacturing method thereof are disclosed. The method comprises: providing a substrate with a first dielectric layer and a gate, wherein the gate is embedded in the first dielectric layer and an upper portion of the gate is an exposed first metal; and covering only the exposed first metal with a conductive material that is harder to be oxidized than the first metal by a selective deposition. An advantage of the present invention is that the metal of the upper surface of the gate is prevented from being oxidized by covering the metal gate with the conductive material that is relatively harder to be oxidized, thereby facilitating the formation of an effective electrical connection to the gate.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: August 13, 2013
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Yiying Zhang, Qiyang He
  • Patent number: 8501613
    Abstract: A method includes forming an under-bump metallurgy (UBM) layer overlying a substrate, and forming a mask overlying the UBM layer. The mask covers a first portion of the UBM layer, and a second portion of the UBM layer is exposed through an opening in the mask. A metal bump is formed in the opening and on the second portion of the UBM layer. The mask is then removed. A laser removal is performed to remove a part of the first portion of the UBM layer and to form an UBM.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: August 6, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Yang Lei, Hung-Jui Kuo, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu
  • Publication number: 20130178014
    Abstract: This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor storage device. When the floating gate voltage is relatively high, the channel under the floating gate is of n type and a simple gate-control pn junction structure is configured; by controlling effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through a floating gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed while the quantity of charges in the floating gate determines the device threshold voltage, thus realizing memory functions. This invention features capacity of manufacturing gate-control diode memory devices able to reduce the chip power consumption through advantages of high driving current and small sub-threshold swing.
    Type: Application
    Filed: June 27, 2012
    Publication date: July 11, 2013
    Inventors: Pengfei Wang, Xiaoyong Liu, Qingqing Sun, Wei Zhang
  • Patent number: 8440556
    Abstract: Forming conformal platinum-zinc films for semiconductor devices is described. In one example, a conformal film is formed by heating a substrate in a reaction chamber, exposing a desired region of the substrate to a precursor that contains platinum, purging excess precursor from the chamber, exposing the desired region of the substrate to a co-reactant containing zinc to cause a reaction between the precursor and the co-reactant to form a platinum zinc film on the desired region, and purging the chamber of excess reaction by-products.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Scott Bruce Clendenning, Niloy Mukherjee
  • Patent number: 8431484
    Abstract: A method and apparatus for plating facilitates the plating of a small contact feature of a wafer die while providing a relatively stable plating bath. The method utilizes a supplemental plating structure that is larger than a die contact that is to be plated. The supplemental plating structure may be located on the wafer, and is conductively connected to the die contact. Conductive connection between the die contact and the supplemental plating structure facilitates the plating of the die contact. The supplemental plating structure also can be used to probe test the die prior to singulation.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: April 30, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joseph T. Lindgren
  • Patent number: 8431997
    Abstract: It is an object to solve inhibition of miniaturization of an element and complexity of a manufacturing process thereof. It is another object to provide a nonvolatile memory device and a semiconductor device having the memory device, in which data can be additionally written at a time besides the manufacturing time and in which forgery caused by rewriting of data can be prevented. It is further another object to provide an inexpensive nonvolatile memory device and semiconductor device. A memory element is manufactured in which a first conductive layer, a second conductive layer that is beside the first conductive layer, and conductive fine particles of each surface which is covered with an organic film are deposited over an insulating film. The conductive fine particles are deposited between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: April 30, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiharu Hirakata
  • Patent number: 8431463
    Abstract: A method is disclosed for passivating and contacting a capacitor in an IC above a top level of interconnect metallization, without adding process steps. Passivation is accomplished by a dielectric layer, part of the IC protective overcoat, deposited directly on the capacitor, overlapping the electrode edges. Contact is made to the top electrode of the capacitor by etching small capacitor vias during a bond pad via etch process, followed by depositing and patterning bond pad metal in the capacitor vias to connect the top electrode to other circuit elements in the IC. The top electrode thickness is increased to accommodate the bond pad via etch process.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: April 30, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Maxwell Walthour Lippitt, III, Stephen Arlon Meisner, Lee Alan Stringer, Stephen Fredrick Clark, Fred Percy Debnam, II, Byron Lovell Williams
  • Publication number: 20130059419
    Abstract: A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 7, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Lee Choon Kuan, David J. Corisis, Chong Chin Hui
  • Patent number: 8362613
    Abstract: The present disclosure is directed to a semiconductor die having a chip outline boundary, a die seal, a row of input/output contact pads separated from the chip outline boundary by the die seal, a first row of solder bump connections positioned between the row of input/output contact pads and the die seal, and a second row of solder bump connections separated from the first row of solder bump connections by the row of input/output contact pads.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: January 29, 2013
    Assignee: STMicroelectronics Pvt Ltd.
    Inventors: Anil Yadav, Sanjeev Kumar Jain, Rajesh Bajaj
  • Publication number: 20130010534
    Abstract: It is an object to solve inhibition of miniaturization of an element and complexity of a manufacturing process thereof. It is another object to provide a nonvolatile memory device and a semiconductor device having the memory device, in which data can be additionally written at a time besides the manufacturing time and in which forgery caused by rewriting of data can be prevented. It is further another object to provide an inexpensive nonvolatile memory device and semiconductor device. A memory element is manufactured in which a first conductive layer, a second conductive layer that is beside the first conductive layer, and conductive fine particles of each surface which is covered with an organic film are deposited over an insulating film. The conductive fine particles are deposited between the first conductive layer and the second conductive layer.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 10, 2013
    Inventor: Yoshiharu Hirakata
  • Patent number: 8329583
    Abstract: Methods and compositions for depositing metal films are disclosed herein. In general, the disclosed methods utilize precursor compounds comprising gold, silver, or copper. More specifically, the disclosed precursor compounds utilize pentadienyl ligands coupled to a metal to increase thermal stability. Furthermore, methods of depositing copper, gold, or silver are disclosed in conjunction with use of other precursors to deposit metal films. The methods and compositions may be used in a variety of deposition processes.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: December 11, 2012
    Assignee: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude
    Inventor: Christian Dussarrat
  • Publication number: 20120306087
    Abstract: A semiconductor device includes a substrate including a first metal layer, a first semiconductor chip having sidewalls, and a first solder layer contacting the first semiconductor chip and the first metal layer. The first metal layer includes a groove extending around sidewalls of the first semiconductor chip. The groove is at least partly filled with excess solder from the first solder layer.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Reinhold Bayerer, Niels Oeschler, Alexander Ciliox
  • Publication number: 20120273922
    Abstract: An amorphous carbon film and an interlayer insulation film are formed in a memory cell region and a peripheral circuit region, respectively. An insulating film is formed on the amorphous carbon film and the interlayer insulation film. A portion of the insulating film that corresponds to capacitors on the amorphous carbon film is removed so that lower electrodes of the capacitors are supported from opposite sides of the lower electrodes. An insulating film pattern continuously extends from the memory cell region to the peripheral circuit region wholly covered with the insulating film pattern. Subsequently, the amorphous carbon film is removed to leave the capacitors supported by the insulating film pattern on both sides of the lower electrodes.
    Type: Application
    Filed: April 25, 2012
    Publication date: November 1, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: YASUHIKO UEDA
  • Publication number: 20120264295
    Abstract: A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.
    Type: Application
    Filed: June 22, 2012
    Publication date: October 18, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kaushik Chandra, Ronald G. Filippi, Wai-Kin Li, Ping-Chuan Wang, Chih-Chao Yang
  • Patent number: 8283724
    Abstract: It is an object to solve inhibition of miniaturization of an element and complexity of a manufacturing process thereof. It is another object to provide a nonvolatile memory device and a semiconductor device having the memory device, in which data can be additionally written at a time besides the manufacturing time and in which forgery caused by rewriting of data can be prevented. It is further another object to provide an inexpensive nonvolatile memory device and semiconductor device. A memory element is manufactured in which a first conductive layer, a second conductive layer that is beside the first conductive layer, and conductive fine particles of each surface which is covered with an organic film are deposited over an insulating film. The conductive fine particles are deposited between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: October 9, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiharu Hirakata
  • Publication number: 20120248614
    Abstract: Methods of forming a Ni material on a bond pad are disclosed. The methods include forming a dielectric material over a bond pad, forming an opening within the dielectric material to expose the bond pad, curing the dielectric material to form a surface of the dielectric material having a steep curvilinear profile, and forming a nickel material over the at least one bond pad. The dielectric material having a steep curvilinear profile may be formed by altering at least one of a curing process of the dielectric material and a thickness of the dielectric material. The dielectric material may be used to form a relatively thick Ni material on bond pads smaller than about 50 ?m. Semiconductor structures formed by such methods are also disclosed.
    Type: Application
    Filed: March 29, 2011
    Publication date: October 4, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jaspreet S. Gandhi, Don L. Yates, Yangyang Sun
  • Publication number: 20120241972
    Abstract: An integrated circuit layout for an Input Output (IO) cell includes at least three metal layers. An IO pad is disposed directly over a top metal layer of the at least three metal layers. At least top two metal layers of the at least three metal layers provide a power bus and a ground bus.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 27, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ren CHEN, Kuo-Ji CHEN, Guang-Cheng WANG
  • Publication number: 20120228778
    Abstract: A through via (144) contains a conductor (244, 276) passing through a substrate (140) for connection to an integrated circuit element. The through via consists of two segments (144.1, 144.2) formed from respective different sides (140.1, 140.2) of the substrate and meeting inside the substrate. Each segment is shorter than the entire via, so via formation is facilitated. The second segment is etched after deposition of an etch stop layer (214) into the first segment. Due to the etch stop layer, the first segment's depth does not have to be rigidly controlled. The conductor is formed by separate depositions of conductive material into the via from each side of the substrate. From each side, the conductor is deposited to a shallower depth than the via depth, so the deposition is facilitated. Other embodiments are also provided.
    Type: Application
    Filed: March 7, 2011
    Publication date: September 13, 2012
    Inventors: Valentin Kosenko, Sergey Savastiouk
  • Patent number: 8258053
    Abstract: In sophisticated semiconductor devices including transistors having a high-k metal gate electrode structure, disposable spacers may be provided on the encapsulating spacer element with a reduced width so as to not unduly increase a lateral offset of a strain-inducing material to be incorporated into the active region. For this purpose, a multi-layer deposition may be used in combination with a low pressure CVD process.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: September 4, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Matthias Kessler, Andreas Kurz
  • Publication number: 20120211884
    Abstract: A method and structure for forming a semiconductor device, for example a device including a wafer chip scale package (WCSP), can include the formation of at least one conductive layer which contacts a bond pad. The at least one conductive layer can be patterned using a first mask, then a passivation layer can be formed over the patterned at least one conductive layer. The passivation layer can be patterned using a second mask to expose the at least one conductive layer, then a conductive layer such as a solder ball, conductive bump, metal-filled paste, or another conductor is formed on the at least one conductive layer. The method can result in a structure which is formed using a reduced number of mask steps.
    Type: Application
    Filed: February 23, 2011
    Publication date: August 23, 2012
    Inventors: Frank Stepniak, Christopher Daniel Manack, Licheng M. Han
  • Patent number: 8247320
    Abstract: The invention relates to a process for producing electrodes for solar cells, the electrode being configured as an electrically conductive layer on a substrate for solar cells, in which, in a first step, a dispersion comprising electrically conductive particles is transferred from a carrier to the substrate by irradiating the dispersion with a laser and, in a second step, the dispersion transferred to the substrate is dried and/or hardened to form the electrically conductive layer.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: August 21, 2012
    Assignee: BASF SE
    Inventors: Rene Lochtman, Norbert Wagner, Jürgen Kaczun, Jürgen Pfister
  • Publication number: 20120206685
    Abstract: Disclosed is an electrode film which does not exfoliate from, or diffuse into, an oxide semiconductor or an oxide thin film. An electrode layer comprises a highly adhesive barrier film being a Cu—Mg—Al thin film and a copper thin film; and an oxide semiconductor and an oxide thin film contact with the highly adhesive barrier film. With the highly adhesive barrier film having magnesium in a range of at least 0.5 at % but at most 5 at % and aluminum at least 5 at % but at most 15 at % when the total number of atoms of copper, magnesium, and aluminum is 100 at %, the highly adhesive barrier film has both adhesion and barrier properties. The electrode layer is suitable because a source electrode layer and a drain electrode layer contact the oxide semiconductor layer. A stopper layer having an oxide may be provided on a layer under the electrode layer.
    Type: Application
    Filed: February 22, 2012
    Publication date: August 16, 2012
    Applicant: ULVAC, INC.,
    Inventors: Satoru TAKASAWA, Masanori SHIRAI, Satoru ISHIBASHI
  • Patent number: 8236598
    Abstract: Formulations and methods of making semiconductor devices and solar cell contacts are disclosed. The invention provides a method of making a semiconductor device or solar cell contact including ink-jet printing onto a silicon wafer an ink composition, typically including a high solids loading (20-80 wt %) of glass frit and preferably a conductive metal such as silver. The wafer is then fired such that the glass frit fuses to form a glass, thereby forming a contact layer to silicon.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: August 7, 2012
    Assignee: Ferro Corporation
    Inventors: Chandrashekhar S. Khadilkar, Srinivasan Sridharan, Paul S. Seman, Aziz S. Shaikh
  • Publication number: 20120168934
    Abstract: The present disclosure is directed to a semiconductor die having a chip outline boundary, a die seal, a row of input/output contact pads separated from the chip outline boundary by the die seal, a first row of solder bump connections positioned between the row of input/output contact pads and the die seal, and a second row of solder bump connections separated from the first row of solder bump connections by the row of input/output contact pads.
    Type: Application
    Filed: December 30, 2010
    Publication date: July 5, 2012
    Applicant: STMicroelectronics Pvt Ltd.
    Inventors: Anil Yadav, Sanjeev Kumar Jain, Rajesh Bajaj
  • Publication number: 20120118619
    Abstract: A stack of an interconnect-level dielectric material layer and a disposable dielectric material layer is patterned so that at least one recessed region is formed through the disposable dielectric material layer and in an upper portion of the interconnect-level dielectric material layer. A dielectric liner layer and a metallic liner layer is formed in the at least one recessed region. At least one photoresist is applied to fill the at least one recessed region and lithographically patterned to form via cavities and/or line cavities in the interconnect-level dielectric material layer. After removing the at least one photoresist, the at least one recessed region, the via cavities, and/or the line cavities are filled with at least one metallic material, which is subsequently planarized to form at least one planar resistor having a top surface that is coplanar with top surfaces of metal lines or metal vias.
    Type: Application
    Filed: November 15, 2010
    Publication date: May 17, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roger A. Booth, JR., Lawrence A. Clevenger
  • Publication number: 20120091453
    Abstract: The invention relates to transparent rectifying contact structures for application in electronic devices, in particular appertaining to optoelectronics, solar technology and sensor technology, and also a method for the production thereof. The transparent rectifying contact structure according to the invention has the following constituents: a) a transparent semiconductor, b) a transparent, non-insulating and non-conducting layer composed of metal oxide, metal sulphide and/or metal nitride, the resistivity of which is preferably in the range of 102 ?cm to 107 ?cm and c) a layer composed of a transparent electrical conductor wherein the layer b) is formed between the semiconductor a) and the layer c) and the composition of the layer b) is defined in greater detail in the description of the patent.
    Type: Application
    Filed: June 21, 2010
    Publication date: April 19, 2012
    Applicant: UNIVERSITAET LEIPZIG
    Inventors: Marius Grundmann, Heiko Frenzel, Alexander Lajn, Holger von Wenckstern
  • Publication number: 20120091577
    Abstract: An integrated circuit device includes a Cu pillar and a solder layer overlying the Cu pillar. A Co-containing metallization layer is formed to cover the Cu pillar and the solder layer, and then a thermally reflow process is performed to form a solder bump and drive the Co element into the solder bump. Next, an oxidation process is performed to form a cobalt oxide layer on the sidewall surface of the Cu pillar.
    Type: Application
    Filed: February 16, 2011
    Publication date: April 19, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling HWANG, Zheng-Yi LIM, Chung-Shi LIU
  • Publication number: 20120080661
    Abstract: According to one embodiment, a graphene interconnection includes an insulating film, a catalyst film, and a graphene layer. An insulating film includes an interconnection trench. A catalyst film is formed in the interconnection trench and filling at least a portion of the interconnection trench. A graphene layer is formed on the catalyst film in the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to a bottom surface of the interconnection trench.
    Type: Application
    Filed: August 24, 2011
    Publication date: April 5, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuro Saito, Makoto Wada, Akihiro Kajita, Atsuko Sakata
  • Publication number: 20120001343
    Abstract: In sophisticated semiconductor devices, densely packed metal line layers may be formed on the basis of an ultra low-k dielectric material, wherein corresponding modified portions of increased dielectric constant may be removed in the presence of the metal lines, for instance, by means of a selective wet chemical etch process. Consequently, the metal lines may be provided with desired critical dimensions without having to take into consideration a change of the critical dimensions upon removing the modified material portion, as is the case in conventional strategies.
    Type: Application
    Filed: December 16, 2010
    Publication date: January 5, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Torsten Huisinga, Michael Grillberger, Frank Feustel
  • Patent number: 8088678
    Abstract: A first aspect of the present invention provides a semiconductor manufacturing apparatus including: a load lock chamber; a transfer chamber; and a treatment chamber 1 and a treatment chamber 2 which carry out treatment using plasma, wherein, in the treatment chamber 2, an exhaust means is provided with a control means for making an oxygen partial pressure into 1*10?5 [Pa] or less.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: January 3, 2012
    Assignee: Canon Anelva Corporation
    Inventors: Naomu Kitano, Takashi Minami, Motomu Kosuda, Heiji Watanabe
  • Publication number: 20110309353
    Abstract: A semiconductor device includes, in a first region over a semiconductor substrate, a first insulating layer, a first wiring, a second insulating layer, a third insulating layer, and a via and a second wiring embedded in the second insulating layer and the third insulating layer through a barrier metal, and includes, in a second region, the first insulating layer, a gate electrode, the second insulating layer, a semiconductor layer located, the third insulating layer, and a first electric conductor and a second electric conductor embedded in the third insulating layer so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view through a barrier metal and coupled to the semiconductor layer through the barrier metal.
    Type: Application
    Filed: May 27, 2011
    Publication date: December 22, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Kishou Kaneko, Naoya Inoue, Yoshihiro Hayashi
  • Publication number: 20110312176
    Abstract: Accordingly, the present invention provides a method of forming an electrode having reduced corrosion and water decomposition on a surface thereof. A substrate which has a conductive layer disposed thereon is provided and the conductive layer has an oxide layer with an exposed surface. The exposed surface of the oxide layer contacts a solution of an organic surface active compound in an organic solvent to form a protective layer of the organic surface active compound over the oxide layer. The protective layer has a thickness of from about 0.5 nm to about 5 nm and ranges therebetween depending on a chemical structure of the surface active compound.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 22, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Shafaat Ahmed, Hariklia Deligianni, Dario L. Goldfarb, Stefan Harrer, Binquan Luan, Glenn J. Martyna, Hongbo Peng, Stanislav Polonsky, Stephen Rossnagel, Xiaoyan Shao, Gustavo A. Stolovitzky
  • Publication number: 20110266674
    Abstract: The present disclosure provides methods for forming semiconductor devices with laser-etched vias and apparatus including the same. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate having a frontside and a backside, and providing a layer above the frontside of the substrate, the layer having a different composition from the substrate. The method further includes controlling a laser power and a laser pulse number to laser etch an opening through the layer and at least a portion of the frontside of the substrate, filling the opening with a conductive material to form a via, removing a portion of the backside of the substrate to expose the via, and electrically coupling a first element to a second element with the via. A semiconductor device fabricated by such a method is also disclosed.
    Type: Application
    Filed: April 28, 2010
    Publication date: November 3, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Ching-Hua Chiu, Troy Wu
  • Publication number: 20110260299
    Abstract: A semiconductor printed circuit board assembly (PCBA) and method for making same for use in electronic packages having a core layer of copper-invar-copper (CIC) with a layer of dielectric substrate placed on the core layer. A second layer of dielectric substrate is placed on the lower surface of the core layer of CIC. The layers are laminated together. Blind vias are laser drilled into the layers of dielectric substrate. The partially completed PCBA is subjected to a reactive ion etch (RIE) plasma as a first step to clean blind vias in the PCBA. After the plasma etch, an acidic etchant liquid solution is used on the blind vias. Pre-plating cleaning of blind vias removes a majority of oxides from the blind vias. Seed copper layers are then applied to the PCBA, followed by a layer of copper plating that can be etched to meet the requirements of the PCBA.
    Type: Application
    Filed: April 22, 2010
    Publication date: October 27, 2011
    Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
    Inventors: Robert D. Edwards, Frank D. Egitto, Luis J. Matienzo, Susan Pitely, Daniel C. Van Hart
  • Publication number: 20110254139
    Abstract: An improved metal interconnect is formed with reduced metal voids and dendrites. An embodiment includes forming a mask layer on a dielectric layer, forming openings in the mask and dielectric layers, depositing a planarization layer over the mask layer and filling the openings, planarizing to remove the mask layer, removing the planarization layer from the openings, and filling the openings with metal. The planarization step prior to depositing the metal removes the etch undercut that occurs during formation of the openings and reduces the aspect ratio in the openings, thereby improving metal fill uniformity.
    Type: Application
    Filed: April 20, 2010
    Publication date: October 20, 2011
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jihong Choi, Tibor Bolom
  • Publication number: 20110248406
    Abstract: In connection with a semiconductor device in which a conductive member is coupled to the surface of a bonding pad exposed from an opening formed in a passivation film, there is provided a technique able to suppress the occurrence of a crack in the passivation film. A second planar distance between a first end of an electrode layer and a first end of a pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the pad.
    Type: Application
    Filed: April 6, 2011
    Publication date: October 13, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Tamaki WADA, Akihiro TOBITA, Seiichi ICHIHARA
  • Publication number: 20110248408
    Abstract: There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided.
    Type: Application
    Filed: March 24, 2011
    Publication date: October 13, 2011
    Applicants: SUNGKYUNKWAN UNIVERSITY Foundation for Corporate Collaboration, SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Wook Park, Young Do Kweon, Jang Hyun Kim, Tae Seok Park, Su Jeong Suh, Jae Gwon Jang, Nam Jung Kim, Seung Kyu Lim, Kwang Keun Lee
  • Publication number: 20110248401
    Abstract: Transparent electrodes are manufactured. In accordance with various example embodiments, a transparent electrode is manufactured by generating a solution including a composite material having nanotubes and a conjugated polymer, in which the nanotubes constitute a majority of the composite material by weight. The conjugated polymer is used to disperse the nanotubes in the solution, and the solution is coated onto a substrate to form an electrode including a network of the carbon nanotubes.
    Type: Application
    Filed: April 13, 2010
    Publication date: October 13, 2011
    Inventors: Sondra Hellstrom, Zhenan Bao