Abstract: A semiconductor structure includes a substrate, a conductive feature over the substrate, a conductive plug structure contacting a portion of an upper surface of the conductive feature, a first etch stop layer over another portion of the upper surface of the conductive feature, and a second etch stop layer over the first etch stop layer. The first etch stop layer is a doped etch stop layer. The first etch stop layer is to function as an etch stop layer during a predetermined etching process for etching the second etch stop layer.

Abstract: A display device and method for fabricating includes patterning a field shield dielectric layer to expose conductors and form a cavity over the conductors. InkJet printing a semiconductor material fills a portion of the cavity in contact with the conductors. An insulation material is deposited on the semiconductor material. A pixel pad is formed over the insulation material and the field shield dielectric layer. A pixel is formed which includes a thin film transistor with an ink jet printed semiconductor layer.

Abstract: Provided are methods of manufacturing semiconductor devices by which two different kinds of contact holes with different sizes are formed using one photolithography process. The methods include preparing a semiconductor substrate in which an active region is titled in a diagonal direction. A hard mask is formed on the entire surface of the semiconductor substrate. A mask hole is patterned not to overlap a word line. A first oxide layer is deposited on the hard mask, and the hard mask is removed to form a piston-shaped sacrificial pattern. A first polysilicon (poly-Si) layer is deposited on the sacrificial pattern and patterned to form a cylindrical first sacrificial mask surrounding the piston-shaped sacrificial pattern. A second oxide layer is coated on the first sacrificial mask to such an extent as to form voids. A second poly-Si layer is deposited in the voids and patterned to form a pillar-shaped second sacrificial mask. The second oxide layer is removed to expose the active region.

Abstract: A method for fabricating a semiconductor device includes forming a trench by etching a substrate using a hard mask layer as an etch barrier, forming an insulation material which covers sidewalls of the trench, forming a sacrificial material which fills the trench and is planarized to expose the surface of the hard mask layer, forming a masking layer having a damaged region over the sacrificial material, selectively removing the damaged region of the masking layer, exposing a portion of the insulation material, which is formed at a sidewall of the trench, by etching a portion of the sacrificial material using the remaining masking layer as a barrier, and forming a side contact by removing the exposed insulation material.

Abstract: In a semiconductor device producing method according to one embodiment, an insulating film containing silicon is formed on a semiconductor substrate, a resist is deposited on the insulating film, the resist is patterned into a predetermined pattern, and the insulating film is processed by a dry etching treatment in which gas containing C, F, Br, H, and O is used with the resist having the predetermined pattern as a mask. A deposited film in which C and Br are coupled is produced on the resist.

Abstract: A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.

Abstract: A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress.

Abstract: A method for fabricating a semiconductor memory device includes: forming a trench in a substrate; forming a gate insulation layer along the trench, wherein the gate insulation layer is thicker at an upper region of the trench than at a lower region thereof; forming a gate pattern on the gate insulation layer to fill the trench; forming a first active region over a first region of the gate pattern to overlap the gate pattern at the thicker region of the gate insulation layer; and forming a second active region formed over a second region of the gate pattern and spaced apart from the first active region by a floating body formed therebetween, wherein the second region is vertically lower than the first region.

Abstract: A method for fabricating semiconductor device includes forming a nitride pattern and a hard mask pattern over a substrate, forming a trench by etching the substrate using the hard mask pattern as an etch barrier, forming an oxide layer filling the trench, performing a planarization process on the oxide layer until the nitride pattern is exposed, and removing the nitride pattern though a dry strip process using a plasma.

Abstract: A photosensitive resin film is formed on a protective insulating film. Next, a plurality of bump cores is formed on the protective insulating film along a first straight line by exposing and developing the photosensitive resin film. Next, a plurality of bumps, and a plurality of interconnects that connects each of the plurality of bumps to any of the electrode pads are formed by selectively forming conductive films on a plurality of bump cores, a plurality of electrode pads, and the protective insulating film. In the step of forming a plurality of bump cores, a region bordering on the interconnect on the lateral faces of the bump core is formed to have a gentler slope than that of a region intersecting the first straight line, by exposing the photosensitive resin film only one time using a multi-gradation mask.

Abstract: A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the second dielectric layer. The dielectric layers define a via having a first part bounded by the first electrode layer and the bottom electrode and a second part bounded by the second dielectric layer and the top electrode. A memory element is within the via and is in electrical contact with the top and bottom electrodes. The first and second parts of the via may comprise a constricted, energy-concentrating region and an enlarged region respectively. The constricted region may have a width smaller than the minimum feature size of the process used to form the enlarged region of the via. A method for manufacturing a memory cell is also disclosed.

Abstract: A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress.

Abstract: According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift mask and a normal photomask. A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The a second wiring layer includes a second wiring and a third wiring. A step of stacking an interlayer insulating film on the second wiring layer. A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask. A step of burying a metal in the first opening and the second opening. A step of providing a pad to be overlaid on the first and second openings.

Abstract: A dielectric cap layer of a sophisticated metallization system may be provided in a locally restricted manner so as to enable direct contact of the dielectric material of one metallization layer with a low-k dielectric material of a subsequent metallization layer, which may thus provide enhanced adhesion and overall mechanical integrity.

Abstract: A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within the buried bit line forming trench, the bit line vias, and the memory storage node vias within the dielectric mass. Other aspects and implementations are contemplated.

Abstract: A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.

Abstract: A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the second dielectric layer. The dielectric layers define a via having a first part bounded by the first electrode layer and the bottom electrode and a second part bounded by the second dielectric layer and the top electrode. A memory element is within the via and is in electrical contact with the top and bottom electrodes. The first and second parts of the via may comprise a constricted, energy-concentrating region and an enlarged region respectively. The constricted region may have a width smaller than the minimum feature size of the process used to form the enlarged region of the via. A method for manufacturing a memory cell is also disclosed.

Abstract: Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.

Abstract: A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress.

Abstract: A method for fabricating a recess pattern in a semiconductor device includes defining an active region on a substrate, forming a first mask pattern over the active region in a line type structure, forming a second mask pattern comprising an open region over the active region, the open region exposing a portion where the active region and the first mask pattern intersect, and etching the active region of the substrate exposed by the first and second mask patterns to form recess patterns.

Abstract: A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within the buried bit line forming trench, the bit line vias, and the memory storage node vias within the dielectric mass. Other aspects and implementations are contemplated.