Moulds (epo) Patents (Class 257/E21.504)
  • Patent number: 10361098
    Abstract: A multi-level leadframe including three bonding levels and one exposed level. Each of the three bonding levels and the one exposed level is positioned in a different horizontal plane, with each bonding level providing a bonding site vertically positioned relative to the horizontal plane of the exposed level, with each bonding site coupled to a package lead at the exposed level. Bonding sites located at first and second bonding levels can be located in a common, outer row, along a common, vertical plane, and bonding sites located at a third bonding level can be located in a separate, inner row, along a separate vertical plane. A third level bonding site can be coupled to a first level bonding site with a multiple level electrical lead conductor that vertically spans a second bonding level. A two-step etch process from a single sheet conductor is provided to manufacture the multi-level leadframe.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dolores Babaran Milo, Cherry Lyn Marquez Aranas
  • Patent number: 10335985
    Abstract: Methods and apparatuses are provided for manufacturing a transaction card. The disclosed methods and apparatuses may be used to form a transaction card frame within a mold. The transaction card frame may include one or more recessed portions formed within a first surface of the transaction card frame. The one or more recessed portions may be configured for affixing one or more electronic components.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: July 2, 2019
    Assignee: Capital One Services, LLC
    Inventors: Carl Alexander Cepress, Elwin Ching Yee Ong
  • Patent number: 10315914
    Abstract: A one or multi-die module comprises multiple dies. The module includes at least one die with a sensor having a sensing region, an encapsulation layer covering top sides of the multiple dies, and a redistribution layer (RDL) covering bottom sides of the multiple dies except for the sensing region. In embodiments, a cap is formed over the sensing region, which has at least a portion that is spaced away from a bottom side of the module. Metal connectors, such as solder balls, are formed on the redistribution layer to provide connection points to the module. This approach can be used to incorporate environmental sensor dies into multi-die modules. It utilizes RDL and openings in the RDL in order to provide robust packaging for the dies, while also allowing the sensor dies to be selectively exposed to the environment.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: June 11, 2019
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventor: Maurice S. Karpman
  • Patent number: 10293541
    Abstract: A thermoforming in-lay technique is discussed that uses retractable pins to hold an in-lay piece securely in place in a primary mold. The in-lay piece is fabricated prior to the primary molding process and creates multiple pin receivers in the in-lay that are retractably engaged by the retractable pins when placed into the primary mold. When the primary substrate is formed into the primary mold, the retractable pins prevent the in-lay piece from moving out of position. Once the primary substrate has cooled sufficiently, the pins are retracted allowing the finished primary carrier art to be removed from the primary mold.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: May 21, 2019
    Assignee: Specialty Manufacturing Inc.
    Inventors: Jeff Upton, Haydn Forward, Frank Ames, Jr.
  • Patent number: 10260684
    Abstract: An LED bulb (10) includes a metal lead frame (50) on which is directly mounted a low beam set of first LED dies (14), a high beam set of second LED dies (16), and a high beam set of third LED dies (16). The lead frame (50) is bent so that the first LED dies (14) face upwards and the second and third LED dies (16) face sideways and in opposite directions. A thermally conductive opaque plastic body is molded around the lead frame and exposes the LED dies. The body includes light-blocking features (26, 32, 40) to cause the light emission pattern of the first LED dies (14) to be limited in lateral and vertical directions for a low beam of a headlight. The light-blocking features also cause the light emission pattern of the second and third LED dies (16) to be less limited in the lateral and vertical directions for a wider high beam of the headlight.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 16, 2019
    Assignee: Lumileds LLC
    Inventors: Marcus Johannes Gerardus Elzinga, Paul Scott Martin
  • Patent number: 10201936
    Abstract: A jig for assisting in aligning a plurality of rectangular workpieces is in the form of a plate having a plurality of grooves parallel to each other. The grooves have respective one ends aligned straight with each other and have a depth smaller than the thickness of the workpieces. After the workpieces have been fitted in the respective grooves, an adhesive tape is applied to the workpieces and the workpieces are transferred from the jig to the adhesive tape, so that the workpieces are arrayed in alignment with each other on the adhesive tape. The workpieces on the adhesive tape are prevented from being placed in different positions and orientations, and can subsequently be processed efficiently.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: February 12, 2019
    Assignee: DISCO CORPORATION
    Inventor: Nobuyasu Kitahara
  • Patent number: 10201099
    Abstract: A circuit board including an electronic device and a manufacturing method of the circuit board are provided. The manufacturing method includes: providing a stainless steel base material including a first surface and a second surface opposite to each other, at least one first cavity located at the first surface and at least one second cavity located at the second surface; respectively forming a first and a second metal layers on the stainless steel base material; respectively disposing at least one first and at least one second electronic devices in the first and the second cavities; respectively forming a first and a second insulating layers on the first and the second surfaces; respectively forming a first and a second circuit structures on the first and the second insulating layers, separating the stainless steel base material, the first and the second metal layers to form two separate circuit substrates including electronic devices.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: February 5, 2019
    Inventor: Chung W. Ho
  • Patent number: 10186432
    Abstract: The reliability of a semiconductor device is improved. During resin injection in a molding step, in a plan view, a plurality of gates of a molding die are arranged at positions different from those over extended lines of a plurality of dicing regions and a resin is injected from the gates. In this way, it becomes possible to reduce entrainment of air in the dicing regions and to lower an occurrence rate of voids. As a consequence, it becomes possible to suppress an occurrence of poor appearance such as formation of voids in a sealing body and to suppress formation of a starting point of a crack which may occur during a reflow process. Thus, the reliability of the semiconductor device can be improved.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: January 22, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Yukinori Tashiro
  • Patent number: 10083899
    Abstract: A method of forming a semiconductor device package includes providing a lead frame having a peripheral structure and a heat slug having an upper and lower surface, the heat slug being attached to the peripheral structure. A semiconductor die is attached to the heat slug. The semiconductor die is encapsulated with a molding compound while the heat slug is attached to the peripheral structure. The heat slug is completely devoid of fasteners before the encapsulating.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: September 25, 2018
    Assignee: Infineon Technologies AG
    Inventors: Mohd Kahar Bajuri, Edmund Sales Cabatbat, Gaylord Evangelista Cruz, Amirul Afiq Hud, Teck Sim Lee, Norbert Joson Santos, Chiew Li Tai, Chin Wei Yang
  • Patent number: 10008430
    Abstract: A semiconductor device includes: a semiconductor element; a frame which has a first surface, holds the semiconductor element on the first surface, and is electrically connected with the semiconductor element; and a seal which has electrical insulation properties and seals the semiconductor element and the frame, wherein a through-hole is formed in the seal, the through-hole has a hole axis which extends in a direction intersecting with the first surface, and an inner peripheral end surface of the seal exposed inside the through-hole is inclined with respect to the hole axis.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: June 26, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masataka Shiramizu, Hiroyuki Hata, Yazhe Wang
  • Patent number: 9966329
    Abstract: Reliability of a semiconductor device is improved. A method for manufacturing the semiconductor device includes the steps of: providing a lead frame having a semiconductor chip mounted thereon; providing a heat radiating frame having a heat radiating plate; and resin sealing the semiconductor chip and the heat radiating plate with the lead frame and the heat radiating frame in a stacked state. The method further includes the steps of: separating a frame body of the heat radiating frame from the lead frame having a sealing body; and applying an inspection to detect resin-unfilled regions to the lead frame having the sealing body. Since the frame body of the heat radiating frame shielding an inspection region is removed before the inspection, it becomes possible to perform the inspection using transmitted light.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: May 8, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Fukumi Shimizu, Haruhiko Harada
  • Patent number: 9917279
    Abstract: Disclosed are an organic light emitting diode display and a manufacturing method thereof, and, more particularly, an organic light emitting diode display which includes an encapsulation layer including an inorganic layer containing carbon at a level of about 0.2 wt % to about 6.2 wt % and an organic layer and a manufacturing method thereof.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: March 13, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Yong Song, Seung-Hun Kim, Jin-Kwang Kim, Cheol Jang
  • Patent number: 9847230
    Abstract: An electronics module assembly is described herein that packages dies using a universal cavity wafer that is independent of electronics module design. In one embodiment, the electronics module assembly can include a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports. The assembly can also include at least one group of dies placed in the frontside cavity and encapsulant that secures the position of the at least one group of dies relative to the cavity wafer. Further, a layer of the encapsulant can cover a backside of the cavity wafer.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: December 19, 2017
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventors: Maurice Karpman, Michael Rickley, Andrew Mueller, Nicole Mueller, Jeffrey Thompson, Charles Baab
  • Patent number: 9837344
    Abstract: An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”).
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: December 5, 2017
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Kishor Desai
  • Patent number: 9831162
    Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first surface), a lower surface (second surface) opposite to the upper surface, and a plurality of side surfaces located between the upper and lower surfaces and having a semiconductor chip mounted thereover. A portion of the metal plate is exposed from a sealing body sealing the semiconductor chip. The exposed portion is covered with a metal film. The side surfaces of the metal plate include a first side surface covered with the sealing body and a side surface (second side surface) provided opposite to the first side surface and exposed from the sealing body. Between the upper and side surfaces of the metal plate, an inclined surface inclined with respect to each of the upper and side surfaces and covered with the metal film is interposed.
    Type: Grant
    Filed: October 23, 2016
    Date of Patent: November 28, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Shoji Hashizume
  • Patent number: 9831105
    Abstract: The invention relates to a method for moulding and surface processing electronic components wherein a grid of electronic components is attached on a carrier; subsequently foil is placed against the side of the electronic components opposite to the carrier and are the electronic components partially encapsulated. After moulding the foil is removed from the electronic components and a free side of the components is surface processed. The invention also relates to a partial encapsulated electronic component as produced with such a method.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: November 28, 2017
    Assignee: Besi Netherlands B.V.
    Inventor: Wilhelmus Gerardus Jozef Gal
  • Patent number: 9832872
    Abstract: A manufacturing method of an electronic device, including: a circuit board with a substrate through hole; a circuit element; and a resin mold with a mold through hole, using a first mold, a second mold having a cavity, and a pressing member protruding from a bottom of the cavity includes: fixing the circuit board to the first mold; fixing the second mold to the first mold to cover an opening of the substrate through hole by the pressing member; and forming the resin mold while covering the circuit element with the constituent material in the cavity. The circuit board is deformed by press-contacting the pressing member to the circuit board in a state where a part of the pressing member is inserted into the substrate through hole so that an opening area of the substrate through hole decreases toward a reverse surface from the one surface.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: November 28, 2017
    Assignee: DENSO CORPORATION
    Inventors: Tetsuto Yamagishi, Masayuki Takenaka, Toshihiro Nagaya, Shinji Hiramitsu
  • Patent number: 9831380
    Abstract: A method of manufacturing a semiconductor device package includes: forming a based frame provided with an outer frame, a plurality of unit frames spaced apart from the outer frame by separating grooves interposed therebetween, and a first connector and a second connector forming connections between each of the plurality of unit frames and the outer frame; forming a package body in each of the plurality of unit frames to allow a mounting area of each unit frame to be open; removing one of the first connector and second the connector connected to each unit frame; mounting a semiconductor device in the mounting area of the unit frame; and cutting the other of the first connector and second the connector connected to each unit frame and separating, from the base frame, the unit frame in which the package body is formed.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: November 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Kyu Park, Wan Jong Kim, Young Geun Jun
  • Patent number: 9793242
    Abstract: A method includes bonding a first device die onto a top surface of a package substrate, and performing an expose molding on the first device die and the package substrate. At least a lower portion of the first device die is molded in a molding material. A top surface of the molding material is level with or higher than a top surface of the first device die. After the expose molding, a second device die is bonded onto a top surface of the first device die. The second device die is electrically coupled to the first device die through through-silicon vias in a semiconductor substrate of the first device die.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Liu, Hai-Ming Chen, Wei-Ting Lin, Jing Ruei Lu, Tsung-Ding Wang
  • Patent number: 9786518
    Abstract: A method of fabricating a receptacle down BGA carrier having a top surface and a bottom surface, the method comprising combining a conductive portion and a molded dielectric portion, said dielectric portion having an inner surface intersecting said top surface, said inner surface forming a cavity for receiving a die; selectively etching part of said conductive portion; and applying solder resist to a portion of a top surface of said conductive portion.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: October 10, 2017
    Assignee: ENABLINK TECHNOLOGIES LIMITED
    Inventor: Ka Wa Cheung
  • Patent number: 9786582
    Abstract: A leadframe for encasing in a mold material includes a plurality of interconnected support members. A die pad is connected to the support members and includes a bottom surface. The die pad is configured to receive a die. A downset is connected to the die pad and positioned below the bottom surface. The downset includes at least one wall defining an interior volume for receiving a flow of the mold material to reduce the velocity of the mold material flow through the downset.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: October 10, 2017
    Assignee: Texas Instruments Incorporated
    Inventors: Chia-Yu Chang, Bob Lee, Steven Su
  • Patent number: 9778687
    Abstract: The disclosure describes methods of fabricating a single-piece housing for an electronic device using an injection molding process. Illustrative fabrication processes describe variations of positioning internal components of an electronic device into a mold enclosure and injecting a foam material to produce a single-piece housing that surrounds the internal components. The single-piece housing may be fabricated to provide the electronic device with at least some buoyancy, as well a means to expel thermal radiation emanating from internal components. Further, the fabricated single-piece housing provides enough structural rigidity to protect internal components of the electronic device from damage, while retaining some malleability to flex without damage when an external pressure is applied.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: October 3, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Vigneswaran Rajagopalan, David Eric Peters, Conan Zhang
  • Patent number: 9755121
    Abstract: A method of detaching a sealing member of a light emitting device which has a substrate, alight emitting element mounted on the substrate and a sealing member that seals the light emitting element, wherein a release layer and/or an air layer is/are provided between the substrate and the sealing member; and the sealing member is detached from the substrate at the release layer and/or the air layer.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: September 5, 2017
    Assignee: NICHIA CORPORATION
    Inventor: Shingo Omura
  • Patent number: 9728688
    Abstract: A method of manufacturing a light emitting device includes providing a light emitting element, a light extracting surface, and a light emitting element lateral surface. A lower mold has an upper surface and a projected portion. The projected portion has a bottom portion. The projected portion has a projected portion upper surface. The projected portion has a projected portion lateral surface provided between the bottom portion and the projected portion upper surface. The light emitting element is arranged on the projected portion such that the light extracting surface contacts the projected portion upper surface. The projected portion lateral surface and the light emitting element lateral surface are covered with a cover member. The lower mold is removed to provide a recessed portion on the light extracting surface surrounded by a sidewall made of the cover member. A first light-transmissive member is provided in the recessed portion.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: August 8, 2017
    Assignee: NICHIA CORPORATION
    Inventor: Shigeki Sajiki
  • Patent number: 9679853
    Abstract: A package-on-package (PoP)-type package includes a first semiconductor package having a first passive element and a first semiconductor device mounted on a first substrate, and a second semiconductor package having a second semiconductor device mounted on a second substrate. The first passive element is electrically connected to the second semiconductor device. Related devices are also discussed.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: June 13, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-joo Lee
  • Patent number: 9659842
    Abstract: A method for fabricating a quad flat non-leaded (QFN) package includes: forming die pads and bump solder pads by pressing a metal plate, wherein each of the die pads and the bump solder pads has at least a cross-sectional area greater than another cross-sectional area located underneath along its vertical thickness dimension, thereby enabling the die pads and the solder pads to be securely embedded in an encapsulant.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: May 23, 2017
    Assignee: APTOS TECHNOLOGY INC.
    Inventor: En-min Jow
  • Patent number: 9653660
    Abstract: A chip scale LED packaging method includes the following steps: clamping an upper mold with a plurality of through holes and a plate-shaped lower mold together; allowing bottoms of the plurality of through holes of the upper mold to be sealed by the plate-shaped lower mold to form a pattern of a plurality of grooves; placing chips one by one in corresponding through holes of the plurality of through holes; pouring encapsulation gel into each of the corresponding through holes; separating the upper mold from the plate-shaped lower mold after the encapsulation gel is cured and molded; and separating each cured and molded encapsulation gel from each of the corresponding through holes of the upper mold and taking each cured and molded encapsulation gel out of the upper mold to obtain an individual chip scale LED package.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 16, 2017
    Inventor: Shu-Hung Lin
  • Patent number: 9635789
    Abstract: According to various aspects, exemplary embodiments are disclosed of EMI shields with increased under-shield space and/or greater component clearance for one or more components under the shield. In an exemplary embodiment, a shield generally includes one or more recessed portions along an inner surface of the cover. Dielectric material is along the inner surface of the cover within at least the one or more recessed portions. The one or more recessed portions may provide increased under-shield space and/or greater clearance for one or more components under the shield. The dielectric material may inhibit the one or more recessed portions of the shield from directly contacting and electrically shorting one or more components when the one or more components are under the shield. Also disclosed are exemplary embodiments of methods relating to making EMI shields and methods relating to providing shielding for one or more components on a substrate.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: April 25, 2017
    Assignee: Laird Technologies, Inc.
    Inventors: Gerald R. English, Joseph C. Boetto, Philip van Haaster
  • Patent number: 9632148
    Abstract: A sensor device having a first housing with a first semiconductor body and a plurality of metallic terminal contacts for electrical contacting of a first sensor, and a second housing with a second semiconductor body with a plurality of metallic terminal contacts for electrical contacting of a second sensor. A section of the plurality of terminal contacts penetrates the second housing on the face side and the second semiconductor body is arranged with a back surface on a front side of the second metal substrate. The two housings form a module, whereby the two housings are connected form-fittingly to one another in the shape of a stack by a fixing device in a way in which the bottom side of the first housing is joined to the bottom side of the second housing and the plurality of terminal contacts of the two housings point in the same direction.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: April 25, 2017
    Assignee: Micronas GmbH
    Inventor: Camillo Pilla
  • Patent number: 9627352
    Abstract: Devices and methods for processing singulated radio-frequency (RF) units. In some embodiments, a device for processing singulated RF packages can include a plate having a plurality of apertures. Each aperture can be dimensioned to receive and position a singulated RF package to thereby facilitate processing of the singulated RF packages positioned in their respective apertures. In some embodiments, such a device can be utilized to batch process high volume of RF packages as if the RF packages are still in a panel format.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: April 18, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventor: Matthew Sean Read
  • Patent number: 9565773
    Abstract: An electronic device may have housing structures, electrical components, and other electronic device structures. Adhesive may be used to join electronic device structures. Adhesive may be dispensed as liquid adhesive and cured to form adhesive joints. Adhesive joints may be debonded. Chain reactions may be initiated by applying a localized initiator such as a chemical or localized energy to the adhesive. Once initiated, the chain reaction may spread throughout the adhesive to cure the adhesive, to globally change adhesive viscosity, or to weaken the adhesive to facilitate debonding. Local changes to adhesive may also be made such as local increases and decreases to adhesive viscosity. Chain reaction curing may be used to cure adhesive or debond adhesive that is hidden from view within gaps in the electronic device structures. Viscosity changes may be used to control where adhesive flows.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: February 7, 2017
    Assignee: Apple Inc.
    Inventor: John J. Baker
  • Patent number: 9543277
    Abstract: A fan-out microelectronic package is provided in which bond wires electrically couple bond pads on a microelectronic element, e.g., a semiconductor chip which may have additional traces thereon, with contacts at a fan-out area of a dielectric element adjacent an edge surface of the chip. The bond wires mechanically decouple the microelectronic element from the fan-out area, which can make the electrical interconnections less prone to reliability issues due to effects of differential thermal expansion, such as caused by temperature excursions during initial package fabrication, bonding operations or thermal cycling. In addition, mechanical decoupling provided by the bond wires may also remedy other mechanical issues such as shock and possible delamination of package elements.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: January 10, 2017
    Assignee: Invensas Corporation
    Inventors: Bongsub Lee, Tu Tam Vu, Rajesh Katkar, Laura Wills Mirkarimi, Akash Agrawal, Kyong-Mo Bang, Gabriel Z. Guevara, Xuan Li, Long Huynh
  • Patent number: 9484228
    Abstract: Molding assemblies and methods for dual side package molding are described. In an embodiment, a molding compound is injected into a front cavity with a first actuator, and a molding compound is injected into a back cavity with a second actuator, with the first and second actuator assemblies being independently controlled. In an embodiment, the molding compound flows through a through-hole in a molding substrate from a front side of the molding substrate to a back side of the molding substrate, and into the back cavity.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: November 1, 2016
    Assignee: Apple Inc.
    Inventors: Scott L. Gooch, Shankar S. Pennathur
  • Patent number: 9449876
    Abstract: A method of separating individual dies of a semiconductor wafer includes forming a metal layer on a first surface of a semiconductor wafer, the semiconductor wafer including a plurality of dies, separating the plurality of dies from one another, and electrical discharge machining the metal layer into individual segments each of which remains attached to one of the dies. A corresponding semiconductor die produced by such a method is also provided.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: September 20, 2016
    Assignee: Infineon Technologies AG
    Inventors: Michael Roesner, Gudrun Stranzl, Manfred Schneegans
  • Patent number: 9443780
    Abstract: A device and method of manufacture is provided that utilize recessed regions along a package edge. For example, in an integrated fan-out package, the dielectric layers, e.g., the polymer layers, of the redistribution layers are removed along the scribe line such that after singulation the dielectric layers are recessed back from the edges of the die. The corner regions may be recessed further. The recessed regions may be triangular, rounded, or other shape. In some embodiments one or more of the corner regions may be recessed further relative to the remaining corner regions. The redistribution layers may be recessed along one or both of the front side redistribution layers and the backside redistribution layers.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 9425165
    Abstract: A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: August 23, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Tadatoshi Danno, Hiroyoshi Taya, Yoshiharu Shimizu
  • Patent number: 9368361
    Abstract: In one embodiment, a method for forming an electronic device includes providing a substrate having a plurality of electronic devices formed therein, forming a protective layer over a major surface of the substrate containing the plurality of electronic devices, forming a mold layer over the protective layer, thinning a major surface of the substrate opposite to the major surface containing the plurality of electronic devices, and removing the adhesive layer and the mold layer. In another embodiment, a zone coating layer can be included between the protective layer and the mold layer.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: June 14, 2016
    Assignee: Amkor Technology, Inc.
    Inventors: Seung Chul Han, Jae Kyu Song, Do Hyung Kim
  • Patent number: 9330946
    Abstract: Structures and processes for die stacking using an opaque or translucent pre-applied underfill material generally include selectively applying a low surface tension material to at least a portion of an alignment mark surface on a die; and applying the opaque or translucent underfill material to the die surface, wherein the underfill material does not wet or adhere to the low surface tension material such that the alignment mark surface is free of underfill material.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: May 3, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mukta G. Farooq, Michael A. Gaynes, Katsuyuki Sakuma
  • Patent number: 9312233
    Abstract: Methods of forming molded panel coreless package structures are described. Those methods and structures may include fabrication of embedded die packages using large panel format and use of molding to improve rigidity of the panel, as well as to embed the die in a non-sacrificial mold material. The methods and structures described include methods for manufacturing thin, coreless substrate architectures which possess low warpage.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: April 12, 2016
    Assignee: Intel Corporation
    Inventors: Rahul N. Manepalli, Hamid R. Azimi, John S. Guzek
  • Patent number: 8993376
    Abstract: A semiconductor device has a base substrate with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base substrate. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base substrate and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base substrate. A portion of the second surface of the base substrate is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Emmanuel A. Espiritu, Henry D. Bathan, Dioscoro A. Merilo
  • Patent number: 8994162
    Abstract: A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces as appropriate for interconnection with the die (on the die attach side) and with other elements (such as other packages in a multi-package module). Interconnection with a die is made by wire bonding to exposed traces on a die attach side of the metal layer, and bond fingers and lands for access to testing the package are provided on the opposite (land) side of the metal layer.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventor: Marcos Karnezos
  • Patent number: 8981568
    Abstract: A semiconductor package with simulated wirebonds. A substrate is provided with a plurality of first pads on a first surface and a plurality of second pads on a second surface. Each of the first pads are electrically coupled to one or more of the second pads. At least one semiconductor device is located proximate the first surface of a substrate. The simulated wirebonds include at least a first dielectric layer selectively printed to create a plurality of recesses, and a conductive material located in the recesses to form first and second contact pads, and electrical traces electrically coupling the first and second contact pads. The first contact pads are electrically coupled to terminals on the semiconductor device and the second contact pads are electrically coupled to the first pads on the first surface of the substrate. An overmolding material seals the semiconductor device and the simulated wirebonds.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: March 17, 2015
    Assignee: HSIO Technologies, LLC
    Inventor: James Rathburn
  • Patent number: 8975734
    Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 10, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 8969977
    Abstract: The invention provides a flow sensor structure for sealing the surface of an electric control circuit and a part of a semiconductor device via a manufacturing method capable of preventing occurrence of flash or chip crack when clamping the semiconductor device via a mold. The invention provides a flow sensor structure comprising a semiconductor device having an air flow sensing unit and a diaphragm formed thereto, and a board or a lead frame having an electric control circuit for controlling the semiconductor device disposed thereto, wherein a surface of the electric control circuit and a part of a surface of the semiconductor device is covered with resin while having the air flow sensing unit portion exposed.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: March 3, 2015
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Tsutomu Kono, Yuuki Okamoto, Takeshi Morino, Keiji Hanzawa
  • Patent number: 8946743
    Abstract: Disclosed is a light emitting apparatus. The light emitting apparatus includes a package body; first and second electrodes; a light emitting device electrically connected to the first and second electrodes and including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer between the first and second conductive semiconductor layers; and a lens supported on the package body and at least a part of the lens including a reflective structure. The package body includes a first cavity, one ends of the first and second electrodes are exposed in the first cavity and other ends of the first and second electrodes are exposed at lateral sides of the package body, and a second cavity is formed at a predetermined portion of the first electrode exposed in the first cavity.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: February 3, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Bong Kul Min
  • Patent number: 8937372
    Abstract: An integrated circuit package system includes an in-line strip, attaching an integrated circuit die over the in-line strip, and applying a molding material with a molded segment having a molded strip protrusion formed therefrom over the in-line strip.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: January 20, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jae Hak Yee, Junwoo Myung
  • Patent number: 8859333
    Abstract: An IC package that is suitable for surface mounting arrangements includes a heat spreader device that is coupled to a bottom portion of the package below the IC die. Coupling the heat spreader device to the bottom portion of the package reduces or eliminates the possibility that placement of the heat spreader device will result in the molding compound bleeding on top of the heat spreader device, and delamination at the footings of the heat spreader device that can cause the package to delaminate, or “popcorn”.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: October 14, 2014
    Assignee: LSI Corporation
    Inventors: Kok Hua Simon Chua, Budi Njoman
  • Patent number: 8828805
    Abstract: The formation of a void is suppressed in the assembly of a semiconductor device. An MCU chip and an AFE chip are mounted over a die pad formed of a quadrangle having a pair of first sides and a pair of second sides. After wire bonding is carried out on the MCU chip and the AFE chip, resin is supplied from the side of one second side of the two second sides to the side of the other second side. The resin is thereby passed through the opening between a first pad group and a second pad group over the MCU chip to fill the area between the chips and thus the formation of a void is suppressed in the area between the chips.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: September 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Masato Numazaki
  • Patent number: 8796052
    Abstract: A method for manufacturing a plurality of optoelectronic apparatuses include attaching bottom surfaces of a plurality of packaged optoelectronic semiconductor devices (POSDs) to a carrier substrate (e.g., a tape) so that there is a space between each POSD and its one or more neighboring POSD(s). A light reflective molding compound is molded around a portion each of the POSDs attached to the carrier substrate so that a reflector cup is formed from the light reflective molding compound for each of the POSDs. The light reflective molding compound can also attach the POSDs to one another. Alternatively, an opaque molding compound can be molded around each POSD/reflector cup to attach the POSDs/reflector cups to one another and form a light barrier between each POSD and its neighboring POSD(s). The carrier substrate is thereafter removed so that electrical contacts on the bottom surfaces of the POSDs are exposed.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: August 5, 2014
    Assignee: Intersil Americas LLC
    Inventors: Seshasayee S. Ankireddi, Lynn K. Wiese
  • Patent number: 8779599
    Abstract: A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Cheng-Lin Huang, Szu Wei Lu, Jui-Pin Hung, Shin-Puu Jeng, Chen-Hua Yu