Moulds (epo) Patents (Class 257/E21.504)
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Patent number: 11967587Abstract: A printed circuit board (PCB) system includes an integrated circuit (IC) package having a main IC chip that is electrically coupled to a top surface of a package substrate. A first printed circuit board (PCB) is electrically coupled to first contact structures on a bottom surface of the package substrate. A heat dissipation member is coupled to the main IC chip. A memory module is configured to electrically couple, via an interposer, with second contact structures on a top surface of the package substrate while the heat dissipation member dissipates heat from the main IC chip away from one or more memory IC chips on the memory module. The interposer is configured to electrically couple the second contact structures of the IC package with the memory module while the heat dissipation member dissipates heat from the main IC chip away from the one or more memory IC chips.Type: GrantFiled: February 10, 2023Date of Patent: April 23, 2024Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Dan Azeroual, Liav Ben Artsi
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Patent number: 11961920Abstract: An integrated circuit package and method of fabrication are described. The integrated circuit package includes a lead frame having a first surface and a second opposing surface and a semiconductor die having a first, active surface in which circuitry is disposed and a second opposing surface attached to the first surface of the lead frame. A magnet attached to the second surface of the lead frame has a non-contiguous central region and at least one channel extending laterally from the central region. An overmold material forms an enclosure surrounding the magnet, semiconductor die, and a portion of the lead frame.Type: GrantFiled: April 26, 2023Date of Patent: April 16, 2024Assignee: Allegro MicroSystems, LLCInventors: Ravi Vig, William P. Taylor, Paul A. David, P. Karl Scheller, Andreas P. Friedrich
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Patent number: 11894344Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.Type: GrantFiled: April 6, 2022Date of Patent: February 6, 2024Assignee: Intel CorporationInventors: Zhijun Xu, Bin Liu, Yong She, Zhicheng Ding
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Patent number: 11848277Abstract: Provided is a control module including a printed circuit board, an IC, and a shielding cover. The shielding cover is provided with a dispensing hole for adhesive dispensing. The IC is soldered onto the printed circuit board, and an adhesive may be dispensed between the IC and the printed circuit board through the dispensing hole. A method for manufacturing a control module is also provided.Type: GrantFiled: August 21, 2020Date of Patent: December 19, 2023Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Meizhu Zheng, Yuanyuan Li, Dalin Xiang, Jiuzhen Wang
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Patent number: 11842935Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.Type: GrantFiled: May 12, 2021Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Shien Chen, Kuo-Ching Hsu, Wei-Hung Lin, Hui-Min Huang, Ming-Da Cheng, Mirng-Ji Lii
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Patent number: 11646252Abstract: A semiconductor device includes a semiconductor chip, a connection element configured to mechanically and electrically couple the semiconductor device to a circuit board, wherein the connection element is electrically coupled to the semiconductor chip and arranged in a mounting plane of the semiconductor device, and the semiconductor chip is mounted on the connection element. The semiconductor device further includes an extension element mechanically coupled to the connection element and extending in a direction out of the mounting plane, wherein the extension element is configured for air cooling.Type: GrantFiled: February 2, 2021Date of Patent: May 9, 2023Assignee: Infineon Technologies AGInventor: Tomasz Naeve
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Patent number: 11604105Abstract: An adhesive strain sensing pod includes at least one strain sensor, electronics for electrically sensing at least one strain signal from the at least one strain sensor, and a sensor adhesive for adhering the strain sensor to a surface of a structural element. The pod may have a protective case for protecting the strain sensor and the electronics and for transferring at least part of a force, pressing the pod against the surface, to press the strain sensor against the surface. The sensor adhesive may be a liquid adhesive contained in a fragile pouch that ruptures when the pod is forced against the surface, or may be a thermally activated adhesive film that is activated to bond the strain sensor to the surface. A protective film may protect the sensor adhesive prior to installation of the pod and is removed prior to installation of the pod on the surface.Type: GrantFiled: December 3, 2019Date of Patent: March 14, 2023Assignee: 4IIII INNOVATIONS INC.Inventors: Kipling William Fyfe, James Hildebrandt, Ken Fyfe, Anna Miasnikova
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Patent number: 11527509Abstract: A semiconductor package including a first semiconductor chip including a first semiconductor layer having a first forward surface having a first integrated circuit thereon and a first rear surface and a plurality of first through vias electrically connected to the first integrated circuit and including at least first and second groups of first through vias, a second semiconductor chip including a second integrated circuit electrically connected to the first group of first through vias, and a third semiconductor chip including third through vias electrically connected to the second group of first through vias, wherein the first group of first through vias transfer input/output signals of the first integrated circuit, and the second group of first through vias transfer power to the first integrated circuit, may be provided.Type: GrantFiled: June 30, 2021Date of Patent: December 13, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Sanghoon Lee, Hyuekjae Lee
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Patent number: 11426900Abstract: In one example, a process for making a micro device structure includes molding a micro device in a monolithic body of material and forming a fluid flow passage in the body through which fluid can pass directly to the micro device.Type: GrantFiled: March 20, 2013Date of Patent: August 30, 2022Assignee: Hewlett-Packard Development Company, L.P.Inventors: Chien-Hua Chen, Michael W. Cumbie, Arun K. Agarwal
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Patent number: 11417578Abstract: A semiconductor device includes: a semiconductor element; a frame which has a first surface, holds the semiconductor element on the first surface, and is electrically connected with the semiconductor element; and a seal which has electrical insulation properties and seals the semiconductor element and the frame, wherein a through-hole is formed in the seal, the through-hole has a hole axis which extends in a direction intersecting with the first surface, and an inner peripheral end surface of the seal exposed inside the through-hole is inclined with respect to the hole axis.Type: GrantFiled: May 7, 2018Date of Patent: August 16, 2022Assignee: Mitsubishi Electric CorporationInventors: Masataka Shiramizu, Hiroyuki Hata, Yazhe Wang
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Patent number: 11363720Abstract: A system for manufacturing an electromechanical structure includes first, second, and third entities. The first entity produces conductors on a planar, flat film. The second entity attaches electronic elements at locations on the film in relation to a three-dimensional shape of the film. The electronic elements include a number of surface mount technology components. The locations of the electronic elements are selected to omit substantial deformation during subsequent forming of the film into the three-dimensional shape. The third entity forms the film into the three-dimensional shape when the electronic elements are supported on the film. The third entity includes one or more machines that are continuously roll-fed, automatically in-precut-pieces-fed, computer numerical control, thermoforming, vacuum former, pressure forming, or blow molding. The first, second, and third entities are arranged relative to one another to manufacture the electromechanical structure.Type: GrantFiled: August 28, 2020Date of Patent: June 14, 2022Assignee: TACTOTEK OYInventors: Mikko Heikkinen, Jarmo Sääski, Jarkko Torvinen, Paavo Niskala, Mikko Sippari, Pasi Raappana, Antti Keränen
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Patent number: 11352251Abstract: An electronic integrated circuit (IC) component is mounted to a substrate. A cap member is applied onto the substrate and covers the electronic IC component. The cap member includes an outer wall defining an opening and an inner wall surrounding the electronic IC component. The inner wall extends from a proximal end at the substrate towards a distal end facing the opening in the outer wall to provide a reception chamber for the electronic IC component and a peripheral chamber between the inner wall and the outer wall of the cap member. An encapsulant material is provided in the reception chamber to seal the electronic IC component without being present in the peripheral chamber.Type: GrantFiled: March 26, 2020Date of Patent: June 7, 2022Assignee: STMicroelectronics (Malta) LtdInventors: Kevin Formosa, Eftal Saribas
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Patent number: 11171066Abstract: A method for manufacturing a semiconductor panel is disclosed. In one example, the method includes providing a first preformed polymer form. The method further includes arranging multiple semiconductor chips over the first preformed polymer form. The method further includes attaching a second preformed polymer form to the first preformed polymer form, wherein the semiconductor chips are arranged between the attached preformed polymer forms, and wherein the attached preformed polymer forms form the semiconductor panel encapsulating the semiconductor chips.Type: GrantFiled: November 21, 2019Date of Patent: November 9, 2021Assignee: Infineon Technologies AGInventors: Thorsten Meyer, Andreas Grassmann
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Patent number: 11122700Abstract: An electrical assembly includes a printed circuit board substrate, at least one electrical component which is arranged on the printed circuit board substrate and with which the printed circuit board substrate makes electrical contact, a protective cap which is arranged above the electrical component, and a sheathing material which is applied to the printed circuit board substrate over the protective cap and which covers at least the protective cap on the outside in such a way that the protective cap is provided with at least one filling opening. The sheathing material is introduced through the at least one filling opening into a cap interior between the protective cap and the printed circuit board substrate in such a way that a clearance, which is not filled with the sheathing material and which directly adjoins the at least one electrical component, remains between the protective cap and the printed circuit board substrate.Type: GrantFiled: September 5, 2017Date of Patent: September 14, 2021Assignee: Robert Bosch GmbHInventor: Stefan Moeller
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Patent number: 11031422Abstract: Provided is a solid-state imaging element that is a wafer-level chip size package, that includes an optical sensor chip, a protective layer that is stacked on a light receiving surface of the optical sensor chip, and a rewiring layer that is stacked on a surface opposite to the light receiving surface of the optical sensor chip, in which a connection terminal of the rewiring layer is a copper flat pad without a solder ball, an alloy layer of tin and copper is not formed on a front surface of the flat pad, and a thermal expansion coefficient of the protective layer is substantially balanced with a thermal expansion coefficient of the rewiring layer.Type: GrantFiled: August 4, 2017Date of Patent: June 8, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Naoto Sasaki, Yutaka Ooka
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Patent number: 10946565Abstract: Methods and apparatuses are provided for manufacturing a transaction card. The disclosed methods and apparatuses may be used to form a transaction card frame within a mold. The transaction card frame may include one or more recessed portions formed within a first surface of the transaction card frame. The one or more recessed portions may be configured for affixing one or more electronic components.Type: GrantFiled: December 21, 2018Date of Patent: March 16, 2021Assignee: Capital One Services, LLCInventors: Carl Alexander Cepress, Elwin Ching Yee Ong
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Patent number: 10913191Abstract: A mould includes at least two mould parts, one of which includes a mould cavity for enclosing electronic components placed on a carrier and a contact surface for at least partially enclosing the mould cavity, contacting the carrier, and forming a tight connection with the carrier. A feed channel is recessed into the contact surface and the mould part further includes a displaceable barrier element that is displaceable in a direction substantially perpendicular to the contact surface connecting to the feed channel for regulating the size of a passage in the feed channel. A foil handler applies a foil layer between a wall of the feed channel and the displaceable barrier element which is configured for exerting a pressure onto the foil layer when the mould parts are moved apart to release the carrier with electronic components from the mould part.Type: GrantFiled: December 10, 2015Date of Patent: February 9, 2021Assignee: Besi Netherlands B.V.Inventors: Johannes Lambertus Gerardus Maria Venrooij, Albertus Franciscus Gerardus Van Driel
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Patent number: 10872785Abstract: A multi-level leadframe including three bonding levels and one exposed level. Each of the three bonding levels and the one exposed level is positioned in a different horizontal plane, with each bonding level providing a bonding site vertically positioned relative to the horizontal plane of the exposed level, with each bonding site coupled to a package lead at the exposed level. Bonding sites located at first and second bonding levels can be located in a common, outer row, along a common, vertical plane, and bonding sites located at a third bonding level can be located in a separate, inner row, along a separate vertical plane. A third level bonding site can be coupled to a first level bonding site with a multiple level electrical lead conductor that vertically spans a second bonding level. A two-step etch process from a single sheet conductor is provided to manufacture the multi-level leadframe.Type: GrantFiled: July 23, 2019Date of Patent: December 22, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dolores Babaran Milo, Cherry Lyn Marquez Aranas
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Patent number: 10811298Abstract: An apparatus is provided, comprising: a wafer having a first planar surface and a second surface opposite the first surface. The second surface includes a plurality of recesses. Each recess includes a plurality of sidewalls and a lower surface and is configured to receive a semiconductor device. The plurality of sidewalls of each recess is configured to align the semiconductor device and constrain the semiconductor device from moving in a direction parallel to the second surface.Type: GrantFiled: December 31, 2018Date of Patent: October 20, 2020Assignee: Micron Technology, Inc.Inventor: Jing Cheng Lin
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Patent number: 10712188Abstract: Provide a flow measuring device which inhibits a reduction of flow detection accuracy, which is caused by an influence of a bottom flow which is flowed and inputted from a fit gap between a flow detecting element and an installing portion of the flow detecting element. A concave portion, which inhibits an influence of a bottom flow which is flowed and inputted from a fit gap between an installing portion and a flow detecting element, is provided at a bottom surface of the installing portion of a plate which is positioned on a projected area of a cavity of the flow detecting element.Type: GrantFiled: January 23, 2018Date of Patent: July 14, 2020Assignee: Mitsubishi Electric CorporationInventors: Kazuto Akagi, Yuji Ariyoshi, Masahiro Kawai, Naoyuki Kishikawa
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Patent number: 10666120Abstract: A method includes arranging and clamping a laminated iron core body between a receive unit and a mold unit that includes a resin pool part, the laminated iron core body including a plurality of laminated iron core pieces and a resin hole pierced in the lamination direction, with the laminated iron core body being clamped, extruding a resin of an inside of the resin pool part using a plunger and injecting the resin into the resin hole, after curing the resin in the resin hole, separating unwanted resin from the plunger by moving the plunger by a given distance in a direction away from the laminated iron core body before the laminated iron core body with unwanted resin is detached from the mold unit, and after separating the unwanted resin from the plunger, moving the plunger to the side of the laminated iron core body.Type: GrantFiled: August 2, 2017Date of Patent: May 26, 2020Assignee: MITSUI HIGH-TEC, INC.Inventors: Hirotoshi Mabu, Satoshi Matsubayashi
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Patent number: 10639833Abstract: An apparatus for molding a physical body comprising at least two mold materials, wherein the apparatus comprises a first mold tool and a second mold tool configured for defining a mold volume in between in which the physical body is moldable by supplying the at least two mold materials, and a supply unit configured for separately supplying the at least two mold materials to the mold volume, wherein at least part of at least one of the first mold tool and the second mold tool is movable to thereby increase the dimension of the mold volume after having supplied the first mold material to the mold volume and before and/or during supplying the second mold material to the mold volume.Type: GrantFiled: March 29, 2017Date of Patent: May 5, 2020Assignee: Infineon Technologies AGInventors: Chau Fatt Chiang, Khar Foong Chung
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Patent number: 10636765Abstract: A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.Type: GrantFiled: March 14, 2017Date of Patent: April 28, 2020Assignee: STATS ChipPAC Pte. Ltd.Inventors: DeokKyung Yang, YongMin Kim, JaeHyuk Choi, YeoChan Ko, HeeSoo Lee
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Patent number: 10632655Abstract: A method of producing a carrier substrate for an optoelectronic semiconductor component includes: providing a leadframe including a first electrically conductive contact section and a second electrically conductive contact section, and injection molding a housing including a housing frame embedding the leadframe by an injection-molding material free of epoxy such that the leadframe embedded in the housing frame of the injection-molded housing forms a carrier substrate for an optoelectronic semiconductor component.Type: GrantFiled: August 11, 2016Date of Patent: April 28, 2020Assignee: OSRAM OLED GmbHInventors: Stephan Eicher, Martin Brandl, Markus Boss
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Patent number: 10627672Abstract: A light emitting diode (LED) package includes: an LED; a stack structure including a light-scattering structure spaced apart from the LED, and a light conversion layer disposed on at least one surface selected from an inner surface and an outer surface of the light-scattering structure and configured to convert light emitted from the LED into white light, wherein the light conversion layer includes a semiconductor nanocrystal; and an organic barrier layer disposed on a surface of the light conversion layer.Type: GrantFiled: September 21, 2016Date of Patent: April 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun Joo Jang, Hyun A Kang, Shin Ae Jun, Oul Cho
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Patent number: 10580750Abstract: An electronic component includes: four device chips having rectangular planar shapes and arranged on a substrate so that a corner of four corners constituting a rectangle of one device chip is adjacent to the corners of remaining three device chips; first pads located on surfaces of the four device chips and closest to the corner; one or more first bumps bonding the first pads to the substrate in the four device chips; second pads located on surfaces of the four device chips, the second pad being one of pads other than the first pad; and one or more second bumps bonding the second pads to the substrate in the four device chips, a sum of bonded areas between the one or more second bumps and the second pad being less than a sum of bonded areas between the first pad and the one or more first bumps.Type: GrantFiled: August 14, 2018Date of Patent: March 3, 2020Assignee: TAIYO YUDEN CO., LTD.Inventors: Motoi Yamauchi, Yuki Endo
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Patent number: 10505102Abstract: A semiconductor device includes a substrate, a semiconductor die attached to the substrate, and an encapsulation material. The semiconductor die includes a sensing element. The encapsulation material encapsulates the semiconductor die and a portion of the substrate. The encapsulation material defines a through-hole to receive a conductive element. The sensing element may include a magnetic field sensor to sense a magnetic field generated by the conductive element.Type: GrantFiled: April 4, 2016Date of Patent: December 10, 2019Assignee: Infineon Technologies AGInventors: Volker Strutz, Klaus Elian, Cyrus Ghahremani, Rainer Markus Schaller
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Patent number: 10498203Abstract: A laminated rotor core (36) wherein permanent magnets (47) are inserted in respective magnet insertion holes (46) is disposed between and pressed by an upper die (37) and a lower die (29). The upper die (37) has resin reservoir pots (50) provided above the laminated rotor core (36) and at positions corresponding to the respective magnet insertion holes (46). Raw resin material put in the resin reservoir pots (50) is heated by the upper die (37). Subsequently, the resin material in a liquefied state is ejected from the resin reservoir pots (50) by plungers (52) that are inserted and moves vertically in the resin reservoir pots (50) and is directly filled in the magnet insertion holes (46). Consequently, the respective magnet insertion holes (46) are filled with the resin material more evenly and highly reliable products can be supplied at low cost.Type: GrantFiled: February 4, 2014Date of Patent: December 3, 2019Assignee: MITSUI HIGH-TEC, INC.Inventors: Satoshi Matsubayashi, Hirotoshi Mabu, Katsumi Amano, Atsushi Shiraishi
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Patent number: 10361098Abstract: A multi-level leadframe including three bonding levels and one exposed level. Each of the three bonding levels and the one exposed level is positioned in a different horizontal plane, with each bonding level providing a bonding site vertically positioned relative to the horizontal plane of the exposed level, with each bonding site coupled to a package lead at the exposed level. Bonding sites located at first and second bonding levels can be located in a common, outer row, along a common, vertical plane, and bonding sites located at a third bonding level can be located in a separate, inner row, along a separate vertical plane. A third level bonding site can be coupled to a first level bonding site with a multiple level electrical lead conductor that vertically spans a second bonding level. A two-step etch process from a single sheet conductor is provided to manufacture the multi-level leadframe.Type: GrantFiled: December 20, 2017Date of Patent: July 23, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dolores Babaran Milo, Cherry Lyn Marquez Aranas
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Patent number: 10335985Abstract: Methods and apparatuses are provided for manufacturing a transaction card. The disclosed methods and apparatuses may be used to form a transaction card frame within a mold. The transaction card frame may include one or more recessed portions formed within a first surface of the transaction card frame. The one or more recessed portions may be configured for affixing one or more electronic components.Type: GrantFiled: October 13, 2016Date of Patent: July 2, 2019Assignee: Capital One Services, LLCInventors: Carl Alexander Cepress, Elwin Ching Yee Ong
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Patent number: 10315914Abstract: A one or multi-die module comprises multiple dies. The module includes at least one die with a sensor having a sensing region, an encapsulation layer covering top sides of the multiple dies, and a redistribution layer (RDL) covering bottom sides of the multiple dies except for the sensing region. In embodiments, a cap is formed over the sensing region, which has at least a portion that is spaced away from a bottom side of the module. Metal connectors, such as solder balls, are formed on the redistribution layer to provide connection points to the module. This approach can be used to incorporate environmental sensor dies into multi-die modules. It utilizes RDL and openings in the RDL in order to provide robust packaging for the dies, while also allowing the sensor dies to be selectively exposed to the environment.Type: GrantFiled: June 27, 2017Date of Patent: June 11, 2019Assignee: The Charles Stark Draper Laboratory, Inc.Inventor: Maurice S. Karpman
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Patent number: 10293541Abstract: A thermoforming in-lay technique is discussed that uses retractable pins to hold an in-lay piece securely in place in a primary mold. The in-lay piece is fabricated prior to the primary molding process and creates multiple pin receivers in the in-lay that are retractably engaged by the retractable pins when placed into the primary mold. When the primary substrate is formed into the primary mold, the retractable pins prevent the in-lay piece from moving out of position. Once the primary substrate has cooled sufficiently, the pins are retracted allowing the finished primary carrier art to be removed from the primary mold.Type: GrantFiled: February 21, 2017Date of Patent: May 21, 2019Assignee: Specialty Manufacturing Inc.Inventors: Jeff Upton, Haydn Forward, Frank Ames, Jr.
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Patent number: 10260684Abstract: An LED bulb (10) includes a metal lead frame (50) on which is directly mounted a low beam set of first LED dies (14), a high beam set of second LED dies (16), and a high beam set of third LED dies (16). The lead frame (50) is bent so that the first LED dies (14) face upwards and the second and third LED dies (16) face sideways and in opposite directions. A thermally conductive opaque plastic body is molded around the lead frame and exposes the LED dies. The body includes light-blocking features (26, 32, 40) to cause the light emission pattern of the first LED dies (14) to be limited in lateral and vertical directions for a low beam of a headlight. The light-blocking features also cause the light emission pattern of the second and third LED dies (16) to be less limited in the lateral and vertical directions for a wider high beam of the headlight.Type: GrantFiled: December 16, 2014Date of Patent: April 16, 2019Assignee: Lumileds LLCInventors: Marcus Johannes Gerardus Elzinga, Paul Scott Martin
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Patent number: 10201936Abstract: A jig for assisting in aligning a plurality of rectangular workpieces is in the form of a plate having a plurality of grooves parallel to each other. The grooves have respective one ends aligned straight with each other and have a depth smaller than the thickness of the workpieces. After the workpieces have been fitted in the respective grooves, an adhesive tape is applied to the workpieces and the workpieces are transferred from the jig to the adhesive tape, so that the workpieces are arrayed in alignment with each other on the adhesive tape. The workpieces on the adhesive tape are prevented from being placed in different positions and orientations, and can subsequently be processed efficiently.Type: GrantFiled: January 19, 2017Date of Patent: February 12, 2019Assignee: DISCO CORPORATIONInventor: Nobuyasu Kitahara
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Patent number: 10201099Abstract: A circuit board including an electronic device and a manufacturing method of the circuit board are provided. The manufacturing method includes: providing a stainless steel base material including a first surface and a second surface opposite to each other, at least one first cavity located at the first surface and at least one second cavity located at the second surface; respectively forming a first and a second metal layers on the stainless steel base material; respectively disposing at least one first and at least one second electronic devices in the first and the second cavities; respectively forming a first and a second insulating layers on the first and the second surfaces; respectively forming a first and a second circuit structures on the first and the second insulating layers, separating the stainless steel base material, the first and the second metal layers to form two separate circuit substrates including electronic devices.Type: GrantFiled: February 2, 2018Date of Patent: February 5, 2019Inventor: Chung W. Ho
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Patent number: 10186432Abstract: The reliability of a semiconductor device is improved. During resin injection in a molding step, in a plan view, a plurality of gates of a molding die are arranged at positions different from those over extended lines of a plurality of dicing regions and a resin is injected from the gates. In this way, it becomes possible to reduce entrainment of air in the dicing regions and to lower an occurrence rate of voids. As a consequence, it becomes possible to suppress an occurrence of poor appearance such as formation of voids in a sealing body and to suppress formation of a starting point of a crack which may occur during a reflow process. Thus, the reliability of the semiconductor device can be improved.Type: GrantFiled: April 9, 2018Date of Patent: January 22, 2019Assignee: Renesas Electronics CorporationInventor: Yukinori Tashiro
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Patent number: 10083899Abstract: A method of forming a semiconductor device package includes providing a lead frame having a peripheral structure and a heat slug having an upper and lower surface, the heat slug being attached to the peripheral structure. A semiconductor die is attached to the heat slug. The semiconductor die is encapsulated with a molding compound while the heat slug is attached to the peripheral structure. The heat slug is completely devoid of fasteners before the encapsulating.Type: GrantFiled: January 23, 2017Date of Patent: September 25, 2018Assignee: Infineon Technologies AGInventors: Mohd Kahar Bajuri, Edmund Sales Cabatbat, Gaylord Evangelista Cruz, Amirul Afiq Hud, Teck Sim Lee, Norbert Joson Santos, Chiew Li Tai, Chin Wei Yang
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Patent number: 10008430Abstract: A semiconductor device includes: a semiconductor element; a frame which has a first surface, holds the semiconductor element on the first surface, and is electrically connected with the semiconductor element; and a seal which has electrical insulation properties and seals the semiconductor element and the frame, wherein a through-hole is formed in the seal, the through-hole has a hole axis which extends in a direction intersecting with the first surface, and an inner peripheral end surface of the seal exposed inside the through-hole is inclined with respect to the hole axis.Type: GrantFiled: March 6, 2015Date of Patent: June 26, 2018Assignee: Mitsubishi Electric CorporationInventors: Masataka Shiramizu, Hiroyuki Hata, Yazhe Wang
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Patent number: 9966329Abstract: Reliability of a semiconductor device is improved. A method for manufacturing the semiconductor device includes the steps of: providing a lead frame having a semiconductor chip mounted thereon; providing a heat radiating frame having a heat radiating plate; and resin sealing the semiconductor chip and the heat radiating plate with the lead frame and the heat radiating frame in a stacked state. The method further includes the steps of: separating a frame body of the heat radiating frame from the lead frame having a sealing body; and applying an inspection to detect resin-unfilled regions to the lead frame having the sealing body. Since the frame body of the heat radiating frame shielding an inspection region is removed before the inspection, it becomes possible to perform the inspection using transmitted light.Type: GrantFiled: July 26, 2017Date of Patent: May 8, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Fukumi Shimizu, Haruhiko Harada
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Patent number: 9917279Abstract: Disclosed are an organic light emitting diode display and a manufacturing method thereof, and, more particularly, an organic light emitting diode display which includes an encapsulation layer including an inorganic layer containing carbon at a level of about 0.2 wt % to about 6.2 wt % and an organic layer and a manufacturing method thereof.Type: GrantFiled: May 19, 2015Date of Patent: March 13, 2018Assignee: Samsung Display Co., Ltd.Inventors: Seung-Yong Song, Seung-Hun Kim, Jin-Kwang Kim, Cheol Jang
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Patent number: 9847230Abstract: An electronics module assembly is described herein that packages dies using a universal cavity wafer that is independent of electronics module design. In one embodiment, the electronics module assembly can include a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports. The assembly can also include at least one group of dies placed in the frontside cavity and encapsulant that secures the position of the at least one group of dies relative to the cavity wafer. Further, a layer of the encapsulant can cover a backside of the cavity wafer.Type: GrantFiled: June 9, 2016Date of Patent: December 19, 2017Assignee: The Charles Stark Draper Laboratory, Inc.Inventors: Maurice Karpman, Michael Rickley, Andrew Mueller, Nicole Mueller, Jeffrey Thompson, Charles Baab
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Patent number: 9837344Abstract: An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”).Type: GrantFiled: July 25, 2016Date of Patent: December 5, 2017Assignee: Invensas CorporationInventors: Belgacem Haba, Kishor Desai
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Patent number: 9831380Abstract: A method of manufacturing a semiconductor device package includes: forming a based frame provided with an outer frame, a plurality of unit frames spaced apart from the outer frame by separating grooves interposed therebetween, and a first connector and a second connector forming connections between each of the plurality of unit frames and the outer frame; forming a package body in each of the plurality of unit frames to allow a mounting area of each unit frame to be open; removing one of the first connector and second the connector connected to each unit frame; mounting a semiconductor device in the mounting area of the unit frame; and cutting the other of the first connector and second the connector connected to each unit frame and separating, from the base frame, the unit frame in which the package body is formed.Type: GrantFiled: June 26, 2015Date of Patent: November 28, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Kyu Park, Wan Jong Kim, Young Geun Jun
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Patent number: 9832872Abstract: A manufacturing method of an electronic device, including: a circuit board with a substrate through hole; a circuit element; and a resin mold with a mold through hole, using a first mold, a second mold having a cavity, and a pressing member protruding from a bottom of the cavity includes: fixing the circuit board to the first mold; fixing the second mold to the first mold to cover an opening of the substrate through hole by the pressing member; and forming the resin mold while covering the circuit element with the constituent material in the cavity. The circuit board is deformed by press-contacting the pressing member to the circuit board in a state where a part of the pressing member is inserted into the substrate through hole so that an opening area of the substrate through hole decreases toward a reverse surface from the one surface.Type: GrantFiled: September 14, 2015Date of Patent: November 28, 2017Assignee: DENSO CORPORATIONInventors: Tetsuto Yamagishi, Masayuki Takenaka, Toshihiro Nagaya, Shinji Hiramitsu
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Patent number: 9831105Abstract: The invention relates to a method for moulding and surface processing electronic components wherein a grid of electronic components is attached on a carrier; subsequently foil is placed against the side of the electronic components opposite to the carrier and are the electronic components partially encapsulated. After moulding the foil is removed from the electronic components and a free side of the components is surface processed. The invention also relates to a partial encapsulated electronic component as produced with such a method.Type: GrantFiled: September 26, 2014Date of Patent: November 28, 2017Assignee: Besi Netherlands B.V.Inventor: Wilhelmus Gerardus Jozef Gal
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Patent number: 9831162Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first surface), a lower surface (second surface) opposite to the upper surface, and a plurality of side surfaces located between the upper and lower surfaces and having a semiconductor chip mounted thereover. A portion of the metal plate is exposed from a sealing body sealing the semiconductor chip. The exposed portion is covered with a metal film. The side surfaces of the metal plate include a first side surface covered with the sealing body and a side surface (second side surface) provided opposite to the first side surface and exposed from the sealing body. Between the upper and side surfaces of the metal plate, an inclined surface inclined with respect to each of the upper and side surfaces and covered with the metal film is interposed.Type: GrantFiled: October 23, 2016Date of Patent: November 28, 2017Assignee: Renesas Electronics CorporationInventor: Shoji Hashizume
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Patent number: 9793242Abstract: A method includes bonding a first device die onto a top surface of a package substrate, and performing an expose molding on the first device die and the package substrate. At least a lower portion of the first device die is molded in a molding material. A top surface of the molding material is level with or higher than a top surface of the first device die. After the expose molding, a second device die is bonded onto a top surface of the first device die. The second device die is electrically coupled to the first device die through through-silicon vias in a semiconductor substrate of the first device die.Type: GrantFiled: December 30, 2013Date of Patent: October 17, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chih Liu, Hai-Ming Chen, Wei-Ting Lin, Jing Ruei Lu, Tsung-Ding Wang
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Patent number: 9786582Abstract: A leadframe for encasing in a mold material includes a plurality of interconnected support members. A die pad is connected to the support members and includes a bottom surface. The die pad is configured to receive a die. A downset is connected to the die pad and positioned below the bottom surface. The downset includes at least one wall defining an interior volume for receiving a flow of the mold material to reduce the velocity of the mold material flow through the downset.Type: GrantFiled: January 29, 2016Date of Patent: October 10, 2017Assignee: Texas Instruments IncorporatedInventors: Chia-Yu Chang, Bob Lee, Steven Su
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Patent number: 9786518Abstract: A method of fabricating a receptacle down BGA carrier having a top surface and a bottom surface, the method comprising combining a conductive portion and a molded dielectric portion, said dielectric portion having an inner surface intersecting said top surface, said inner surface forming a cavity for receiving a die; selectively etching part of said conductive portion; and applying solder resist to a portion of a top surface of said conductive portion.Type: GrantFiled: December 5, 2014Date of Patent: October 10, 2017Assignee: ENABLINK TECHNOLOGIES LIMITEDInventor: Ka Wa Cheung
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Patent number: 9778687Abstract: The disclosure describes methods of fabricating a single-piece housing for an electronic device using an injection molding process. Illustrative fabrication processes describe variations of positioning internal components of an electronic device into a mold enclosure and injecting a foam material to produce a single-piece housing that surrounds the internal components. The single-piece housing may be fabricated to provide the electronic device with at least some buoyancy, as well a means to expel thermal radiation emanating from internal components. Further, the fabricated single-piece housing provides enough structural rigidity to protect internal components of the electronic device from damage, while retaining some malleability to flex without damage when an external pressure is applied.Type: GrantFiled: June 8, 2015Date of Patent: October 3, 2017Assignee: Amazon Technologies, Inc.Inventors: Vigneswaran Rajagopalan, David Eric Peters, Conan Zhang