Abstract: A case including a case main body, a matrix including a semiconductor nanocrystal, the matrix disposed in the case main body, and a sealant disposed on the case main body, wherein the sealant has a gas permeability of about 1 cubic centimeter at standard temperature and pressure per centimeter per meter squared per day per atmosphere or less and a tensile strength of about 5 megaPascals or more, and wherein the semiconductor nanocrystal is a Group II-VI compound, a Group III-V compound, a Group IV-VI compound, a Group IV element, a Group IV element, a Group IV compound, or a combination thereof.

Abstract: The present invention relates to an under-fill dam with high detection probability that is composed of a dry film solder resist and provided in the form of a fence around a chip device in order to prevent leaks of an under-fill material filled in a gap between a substrate and the chip device.

Abstract: A chip packaging structure and a manufacturing method for the same are provided. The chip packaging structure includes a first chip, a second chip and a transfer component. The first chip has a plurality of first bonding pads formed on the top surface of the first chip. The second chip has a plurality of second bonding pads formed on the top surface of the second chip. The first chip and the second chip are arranged abreast and electrically connected to each other. The transfer component is disposed on the top surface of the first chip and electrically connected with the first chip. Via these arrangements, the chip packaging structure can have smaller dimensions.

Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.

Abstract: A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections, a resin encapsulation portion having a recess portion for exposing at least a portion of the die pad sections, the resin encapsulation portion configured to cover the die pad sections and the semiconductor chips, and a heat radiation layer arranged in the recess portion. The heat radiation layer includes an elastic layer exposed toward a direction in which the recess portion is opened. The heat radiation layer directly faces at least a portion of the die pad sections. The elastic layer overlaps with at least a portion of the die pad sections when seen in a thickness direction of the heat radiation layer.

Abstract: Embodiments disclosed herein generally include methods of sealing a cavity in a device structure. The cavity may be opened by etching away sacrificial material that may define the cavity volume. Material from below the cavity may be sputter etched and redeposited over and in passageways leading to the cavity to thereby seal the cavity. Material may be sputter etched from above the cavity and redeposited in the passageways leading to the cavity as well. The sputter etching may occur in a substantially inert atmosphere. As the sputter etching is a physical process, little or no sputter etched material will redeposit within the cavity itself. The inert gases may sweep out any residual gases that may be present in the cavity after the cavity has been opened. Thus, after the sputter etching, the cavity may be substantially filled with inert gases that do not negatively impact the cavity.

Abstract: An apparatus for packaging MEMS and ICs can include a semiconductor substrate, one or more MEMS devices, an enclosure, and one or more bonding structures. The semiconductor substrate can be bonded to a portion of the surface region. The semiconductor substrate can include one or more integrated circuits. Also, the semiconductor substrate can have an upper surface region. The one or more MEMS devise can overlie an inner region of the upper surface region formed by the semiconductor substrate. The enclosure can house the one or more MEMS devices. The enclosure can overlie a first outer region of the upper surface region. Also, the enclosure can have an upper cover region. The one or more bonding structures can be provided within a second outer region of the supper surface region.

Abstract: A semiconductor device has a temporary layer, such as a dam material or adhesive layer, formed over a carrier. A plurality of recesses is formed in the temporary layer. A first semiconductor die is mounted within the recesses of the temporary layer. An encapsulant is deposited over the first semiconductor die and temporary layer. The encapsulant extends into the recesses in the temporary layer. The carrier and temporary layer are removed to form recessed interconnect areas around the first semiconductor die. Alternatively, the recessed interconnect areas can be formed the carrier or encapsulant. Multiple steps can be formed in the recesses of the temporary layer. A conductive layer is formed over the first semiconductor die and encapsulant and into the recessed interconnect areas. A second semiconductor die can be mounted on the first semiconductor die. The semiconductor device can be integrated into PiP and Fi-PoP arrangements.

Abstract: An encapsulated semiconductor device includes: a first conduction path formative plate (1); a second conduction path formative plate (5) joined to the first conduction path formative plate; a power element (12) bonded to the first conduction path formative plate; a heatsink (14) held by the first conduction path formative plate with an insulation sheet (13) interposed between the heatsink and the first conduction path formative plate; and an encapsulation resin (9) configured to encapsulate the first and second conduction path formative plates. A through hole (3) or a lead gap (1b) is formed in a region of the first conduction path formative plate in contact with the insulation sheet. The insulation sheet is press-fitted into the through hole or the lead gap.

Abstract: A graphene layer is generated on a substrate. A plastic material is deposited on the graphene layer to at least partially cover the graphene layer. The substrate is separated into at least two substrate pieces.

Abstract: A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a stiffener, having a stiffener opening completely through the stiffener, on the substrate; molding an encapsulation on the substrate and directly on an outer upper periphery surface of the stiffener and exposing an inner upper periphery surface of the stiffener, the encapsulation exposing a portion of the substrate; mounting an integrated circuit over the substrate and within the perimeter of the stiffener; and attaching a lid plate on the inner upper periphery surface of the stiffener and over the integrated circuit, the lid plate extending above an encapsulation top side.

Abstract: A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material.

Abstract: Provided is a method of manufacturing an electronic device having a first electronic component having a first terminal and a second electronic component having a second terminal, wherein the first electric component is electrically connected to the second electronic component by connecting the first terminal to the second terminal with solder, the method including: providing a resin layer having a flux action between the first terminal and the second terminal to obtain a laminate including the first electronic component, the second electronic component, and the resin layer, wherein a solder is provided on the first terminal or the second terminal; soldering the first terminal and the second terminal; and curing the resin layer while pressing the laminate with a pressurized fluid.

Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting a substrate-less integrated circuit package, having a terminal having characteristics of an intermetallic compound, over a substrate; connecting the substrate and the substrate-less integrated circuit package; and forming a base encapsulation over the substrate-less integrated circuit package with the terminal exposed.

Abstract: A method of manufacture of an integrated circuit package system includes: providing a penetrable layer; partially immersing leads in the penetrable layer; coupling an integrated circuit die to the leads; molding a package body on the integrated circuit die, the leads, and the penetrable layer; and exposing stand-off leads from the leads by removing the penetrable layer including establishing a stand-off height between a bottom of the package body and the bottom of the stand-off leads.

Abstract: A semiconductor device lead frame having enhanced mold locking features is provided. The lead frame has a flag with bendable edge features along the edge of the flag. Each edge feature is shaped to resist movement against encapsulating mold material in a plane of the edge feature. By bending a portion of the edge feature, improved mold locking of the flag is provided in multiple planes.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral interconnect having a bond finger and a contact pad with a trace in direct contact with the bond finger and the contact pad, the bond finger vertically offset from the contact pad; connecting an integrated circuit die and the bond finger; and forming a module encapsulation on the integrated circuit die, the bond finger and the trace exposed from the module encapsulation.

Abstract: A semiconductor chip package and a method to manufacture a semiconductor chip package are disclosed. An embodiment of the present invention comprises a substrate and a semiconductor chip disposed on the substrate and laterally surrounded by a packaging material. The package further comprises a current rail adjacent the semiconductor chip, the current rail isolated from the semiconductor chip by an isolation layer, a first external pad, and a via contact contacting the current rail with the first external pad.

Abstract: A semiconductor device includes a semiconductor module having a heat conductive portion formed of metal and also having a molded resin having a surface at which the heat conductive portion is exposed, a cooling body secured to the semiconductor module by means of bonding material, and heat conductive material formed between and thermally coupling the heat conductive portion and the cooling body.

Abstract: An electronic device includes a support substrate 12, an electric circuit 14 provided in a sealing region set on the support substrate 12, a sealing member 16 provided on the support substrate 12 to surround the sealing region, a sealing substrate 17 bonded to the support substrate 12 with the sealing member 16 interposed therebetween, and a spacer 23 arranged between the support substrate 12 and the sealing substrate 17. The electric circuit 14 includes an electronic element 24 having an organic layer. The sealing member 16 and the spacer 23 are formed using the same material.

Abstract: A semiconductor device has a semiconductor die mounted to a substrate. The semiconductor die and substrate are disposed within a mold chase with a releasing layer disposed over the semiconductor die. A MUF material is deposited around the semiconductor die, releasing layer, and substrate through an opening in the mold chase. The opening in the mold chase is located in an upper mold support of the mold chase. A recess is formed in the MUF material by removing the releasing layer. A TIM is formed in the recess of the MUF material. The TIM is substantially coplanar with the MUF material. A heat spreader is formed over the TIM material. The heat spreader can be formed within the recess of the MUF material over the TIM. A plurality of bumps is formed over a surface of the substrate opposite the semiconductor die.

Abstract: A semiconductor device includes a semiconductor chip, a die pad including an obverse surface on which the semiconductor chip is bonded, a lead spaced apart from the die pad, a bonding wire electrically connecting the semiconductor chip and the lead to each other, and a resin package that seals the semiconductor chip and the bonding wire. The bonding wire includes a first bond portion press-bonded to the semiconductor chip by ball bonding, a second bond portion press bonded to the lead by stitch bonding, a landing portion extending from the second bond portion toward the die pad and formed in contact with an obverse surface of the lead, and a loop extending obliquely upward from the landing portion toward the semiconductor chip.

Abstract: A method for forming signal conduits before encapsulation for incorporation as through vias in a semiconductor device package is provided. One or more signal conduits are formed through photolithography and metal deposition on a metal film or substrate. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die and other parts of the package. The ends of the signal conduits are exposed and the signal conduits can then be used as through vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package, and electrical contacts of the semiconductor die. Using this method, signal conduits can be provided in a variety of geometric placings in the semiconductor device package. A semiconductor device package including the signal conduits made from the above method is also provided.

Abstract: A mechanism for accurate alignment of semiconductor package back side interconnect processing is provided. As semiconductor die are placed in position for an encapsulated panel, two or more alignment die having fiducial markings formed on the back, or non-active, side of those die are also placed in the panel. Once all the die and other components have been placed for the panel, the panel is encapsulated using an encapsulant. Excess encapsulant, if any, is removed by a process such as backgrinding. The back grinding process exposes the back side of the alignment die and the fiducial features on those alignment die. The fiducial features on the alignment die can then be used for alignment of backside processing operations on the panel.

Abstract: A chip package includes a substrate, a pad, a double-sided adhesive tape, a chip, and a sealing member. The pad is arranged on the substrate and has a top surface facing away from the substrate. The double-sided adhesive tape includes a first paste surface and an opposing second paste surface. The first paste surface is attached to the top surface. The chip is attached onto the second paste surface and includes a light emitting surface or a light receiving surface facing away from the second paste surface. The sealing member is formed on the pad and tightly surrounds the chip and the double-sided adhesive.

Abstract: A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

Abstract: A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided.

Abstract: A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications.

Abstract: A photovoltaic module includes an encapsulated photovoltaic element and an infrared transmissive decorative overlay simulating conventional roofing.

Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Abstract: A semiconductor package includes an electromagnetic shielding member for shielding electromagnetic waves. An antenna is disposed on an upper face of the electromagnetic shielding member and includes an antenna part with a plurality of conductive particles electrically connected with each other and an insulation part disposed on the upper face of the electromagnetic shielding member and insulating the antenna part. Ball lands are disposed on the electromagnetic shielding member and are electrically connected with the antenna part. A Radio Frequency Identification (RFID) chip is electrically connected to the ball lands.

Abstract: An adhesive includes an epoxy resin and a hardener. The hardener includes trioxdiamine, diaminodicyclohexylmethane, toluene diamine, and bisphenol-A dianhydride.

Abstract: A semiconductor package and a method of manufacturing the semiconductor package are disclosed. A semiconductor package in accordance with an embodiment of the present invention includes a substrate, which has a ground circuit formed thereon, a semiconductor chip, which is mounted on the substrate, a conductive first shield, which is formed on an upper surface of the semiconductor chip and connected with the ground circuit, and a conductive second shield, which covers the substrate and the semiconductor chip and is connected with the first shield. With a semiconductor package in accordance with an embodiment of the present invention, grounding is possible between semiconductor chips because a shield is also formed on an upper surface of the semiconductor chip, and the shielding property can be improved by a double shielding structure.

Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a substrate bottom side and a substrate top side opposite the substrate bottom side; mounting an integrated circuit over the package substrate, the integrated circuit having an inactive side and an active side opposite the inactive side; connecting stack connectors to the substrate top side; applying a multi-layer film over the substrate top side, the integrated circuit, and the stack connectors, the multi-layer film having a base film layer, a penetrable film layer, and a penetrable adhesive; removing the base film layer and the penetrable film layer to expose the penetrable adhesive and exposed portions of the stack connectors; and forming an adhesive film layer by hardening the penetrable adhesive.

Abstract: A semiconductor device has a substrate and first semiconductor die to the substrate. A plurality of vertically-oriented discrete electrical devices, such as a capacitor, inductor, resistor, diode, or transistor, is mounted over the substrate in proximity to the first semiconductor die. A first terminal of the discrete electrical devices is connected to the substrate. A plurality of bumps is formed over the substrate adjacent to the discrete electrical devices. An encapsulant is deposited over and between the first semiconductor die and substrate. A portion of the bumps and a second terminal of the discrete electrical devices is exposed from the encapsulant. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. The semiconductor devices are stackable and electrically connected through the substrate, discrete electrical devices, and bumps. A heat spreader or second semiconductor die can be disposed between the stacked semiconductor devices.

Abstract: A semiconductor device includes a semiconductor substrate, which includes a through hole that extends through the semiconductor substrate. An insulative layer includes a first surface, an opposite second surface covering the semiconductor substrate, and an opening aligned with the through hole. An insulative film covers an inner wall surface of the semiconductor substrate and the opening. A through electrode is formed in the through hole and the opening inward from the insulative film. The through electrode includes a first end surface that forms a pad exposed from the first surface of the insulative layer. The first end surface of the through electrode is flush with the first surface of the insulative layer.

Abstract: There are provided a semiconductor package capable including an electromagnetic wave shielding structure having excellent electromagnetic interference (EMI) shielding characteristics while protecting individual elements therein from impacts, and a method of manufacturing the same. The semiconductor package includes: a substrate having ground electrodes formed on an upper surface thereof; at least one electronic component mounted on the upper surface of the substrate; an underfill resin filled in a space between the electronic component and the substrate; and a conductive shield part formed along an outer surface formed by the electronic component and the underfill resin and electrically connected to the ground electrodes.

Abstract: A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal.

Abstract: The present semiconductor device packages include a die, a redistribution layer and a plurality of conductive pillars electrically connected to the redistribution layer. A molding compound partially encapsulates the die and the pillars. A plurality of interconnect patterns on the molding compound are electrically connected to the pillars. The interconnect patterns provide electrical connections for a second, stacked semiconductor package.

Abstract: A method of multi-chip wafer level packaging comprises forming a reconfigured wafer using a plurality of photo-sensitive material layers. A plurality of semiconductor chips and wafers are embedded in the photo-sensitive material layers. Furthermore, a variety of through assembly vias are formed in the photo-sensitive material layers. Each semiconductor chip embedded in the photo-sensitive material layers is connected to input/output pads through connection paths formed by the through assembly vias.

Abstract: An apparatus and method of forming a semiconductor package includes having and applying, respectively, a thermal interface material on a semiconductor die. The semiconductor die is included on a die assembly. The semiconductor die is installed in a heat spreader. The heat spreader is at least partially filled with mold compound and the semiconductor die is at least partially immersed in the mold compound once the die assembly is mounted on the heat spreader. The mold compound is then cured.

Abstract: A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.

Abstract: A method of manufacturing a semiconductor device, includes the steps of: (a) providing a support including a plane having a first region for mounting a chip thereon and a second region provided around the first region; (b) forming an insulating resin layer in a semi-curing state on the plane; (c) forming, on the insulating resin layer, a first opening portion for exposing the first region; (d) fitting a chip in the first opening portion to mount the chip on the first region; and (e) completely curing the insulating resin layer after the step (d).

Abstract: An object of the present invention is to improve the quality control of a semiconductor device. By forming an inscription comprising a culled or pixel skipping pattern of dimples on the upper surface of a die pad in a QFN, it is possible to confirm the inscription by X-ray inspection or the like even after individuation and specify a cavity of a resin molding die. Further, it is possible to specify the position of a device region in a lead frame. As a result, when a defect appears, it is possible to sort a defective QFN by appearance inspection and improve quality control in the assembly of a QFN.

Abstract: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

Abstract: A method of forming an electronic assembly includes attaching a backside metal layer the bottomside of a semiconductor die. An area of the backside metal layer matches an area of the bottomside of the die. A die pad and leads are encapsulated within the molding material. The leads include an exposed portion that includes a bonding portion. A gap exposes the backside metal layer along a bottom surface of the package. Bond wires couple the pads on the topside of the die to the leads and the bonding portions. Packaged semiconductor device is soldered to a printed circuit board (PCB). The backside metal layer and the bonding portions of the leads are soldered substrate pads on said PCB.

Abstract: A semiconductor package that stably protects an internal semiconductor chip from external shocks, and a method of manufacturing the semiconductor package is disclosed. The semiconductor package includes a first semiconductor chip including a first body layer having a first surface, a second surface, and a lateral surface between the first surface and the second surface, and a first protective layer that exposes an edge portion of the first surface and forms a step difference with the first surface; an encapsulation structure that covers a lateral surface of the first body layer and the edge portion of the first surface so as to encapsulate the first semiconductor chip to have a locking structure; and a first conductive terminal formed on the first body layer through the protective layer.

Abstract: A semiconductor device has a carrier. A first semiconductor die is mounted to the carrier with an active surface of the first semiconductor die oriented toward the carrier. A dam structure is formed on the carrier and around the first semiconductor die by depositing dam material on the carrier with screen printing, electrolytic plating, electroless plating, or spray coating. An encapsulant is deposited over the carrier and around the first semiconductor die. The encapsulant has a coefficient of thermal expansion (CTE) that corresponds to a CTE of the dam material. The CTE of the dam material is equal to or less than the CTE of the encapsulant. The carrier is removed to expose the active surface of the first semiconductor die with the dam structure stiffening a periphery of the first semiconductor die. The semiconductor device is singulated through the dam structure.