Abstract: The embodiments of mechanisms of wafer-level packaging (WLP) described above utilize a planarization stop layer to determine an end-point of the removal of excess molding compound prior to formation of redistribution lines (RDLs). Such mechanisms of WLP are used to implement fan-out and multi-chip packaging. The mechanisms are also usable to manufacture a package including chips (or dies) with different types of external connections. For example, a die with pre-formed bumps can be packaged with a die without pre-formed bumps.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a paddle having an indented planar surface intersecting an outwardly extending planar surface at an angle of approximately 135 degrees plus 25 degrees or minus 5 degrees; mounting an integrated circuit over the paddle; and forming an encapsulation over the integrated circuit and under the extension void free.

Abstract: An optoelectronic semiconductor component includes a connection support with a connection side, at least one optoelectronic semiconductor chip mounted on the connection side and electrically connected to the connection support, an adhesion-promoting intermediate film applied to the connection side and covering the latter at least in selected places, and at least one radiation-transmissive cast body which at least partially surrounds the semiconductor chip, the cast body being connected mechanically to the connection support by the intermediate film.

Abstract: A semiconductor package includes a circuit board comprising a first surface and a second surface opposite the first surface. A first semiconductor chip is stacked on the first surface and a second semiconductor chip stacked on the first semiconductor chip. A region of the second chip protrudes beyond a side of the first semiconductor chip. A support underpins the protruding region of the second chip. The support may be, for example, dry film solder resist dam.

Abstract: A device includes a first and a second package component. A metal trace is disposed on a surface of the first package component. The metal trace has a lengthwise direction. The second package component includes a metal pillar, wherein the second package component is disposed over the first package component. A solder region bonds the metal pillar to the metal trace, wherein the solder region contacts a top surface of the metal trace.

Abstract: Disclosed is a granular resin composition for encapsulating a semiconductor used for a semiconductor device obtained by encapsulating a semiconductor element by compression molding, satisfying the following requirements (a) to (c) on condition that ion viscosity is measured with a dielectric analyzer under a measurement temperature of 175° C. and a measurement frequency of 100 10 Hz: (a) the time from the initiation of the measurement until a decrease of the ion viscosity to the lowest ion viscosity is 20 seconds or shorter; (b) the lowest ion viscosity value is not more than 6.5; and (c) the time interval between the time from the initiation of the measurement until a decrease of the ion viscosity to the lowest ion viscosity and the time from the initiation of the measurement until the ion viscosity reaching 90% of an ion viscosity value measured at 300 seconds is 10 seconds or longer.

Abstract: A probe card includes a main circuit board electrically connected to a tester in order to test a plurality of unpackaged sets of chips, a frame provided on the main circuit board and including a plurality of sockets for respectively receiving the unpackaged sets of chips, probe blocks respectively provided in the sockets and including a plurality of probes electrically connected to input/output terminals of the unpackaged sets of chips, and a cover plate positioned over the frame and including a plurality of pressure members for pressurizing the unpackaged sets of chips in the sockets.

Abstract: A method of assembling an integrated circuit package is disclosed. The method comprises placing a die on a substrate of the integrated circuit package; coupling a plurality of wire bonds from a plurality of bond pads on the die to corresponding bond pads on the substrate; applying a non-conductive material to the plurality of wire bonds; and encapsulating the die and the plurality of wire bonds. An integrated circuit package is also disclosed.

Abstract: Provided is a simple and low-cost method for manufacturing, in a short time, many light emitting devices wherein adhesiveness between a leadframe and a thermosetting resin composition is high. The method for manufacturing the light emitting device having a resin package (20) wherein the optical reflectivity at a wavelength of 350-800 nm after thermal curing is 70% or more and a resin section (25) and a lead (22) are formed on substantially a same surface on an outer surface (20b) has: a step of sandwiching a leadframe (21) provided with a notched section (21a) by an upper molding die (61) and a lower molding die (62); a step of transfer-molding a thermosetting resin (23) containing a light-reflecting substance (26), in a molding die (60) sandwiched by the upper molding die (61) and the lower molding die (62) and forming a resin-molded body (24) on the leadframe (21); and a step of cutting the resin-molded body (24) and the leadframe (21) along the notched section (21a).

Abstract: Embodiments of stacked die assemblies for an IC are disclosed. One embodiment includes a first interposer; a second interposer; a first integrated circuit die, a second integrated circuit die, and a plurality of components. The first integrated circuit die is interconnected to the first interposer and the second interposer, and the second integrated circuit die is interconnected to the second interposer. The plurality of components interconnect the first integrated circuit die to the first interposer and the second interposer. The plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area of the first interposer and the second interposer, and signals are routed between the first interposer and the second interposer via the first integrated circuit die and the plurality of components, avoiding the interconnect restricted area of the first interposer and the second interposer.

Abstract: A method of assembling a pressure sensor device includes providing a substrate having a plurality of substrate connection pads. A pressure sensor die is attached to a first major surface of the substrate and bond pads of the pressure sensor die are electrically connected to the respective substrate connection pads. A retractable cavity pin is placed on the first major surface of the substrate such that the cavity pin covers the pressure sensor die and the electrical connections to the die. A molding compound is then dispensed onto the first major surface of the substrate such that the molding compound surrounds the pressure sensor die and the cavity pin. The cavity pin is retracted such that a cavity is formed around the pressure sensor die and a gel material is dispensed within the cavity such that the gel material fills the cavity and covers the pressure sensor die.

Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a bottom packaged die having solder balls disposed on the top surface thereof and a top packaged die having metal stud bumps disposed on a bottom surface thereof. The metal stud bumps include a bump region and a tail region coupled to the bump region. Each metal stud bump on the top packaged die is coupled to one of the solder balls on the bottom packaged die.

Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM.

Abstract: A method includes placing a mold chase over a bottom package, wherein the bottom package has a connector at a top surface of the bottom package. The mold chase includes a cover, and a pin under and connected to the cover. The pin occupies a space extending from a top surface of the connector to the cover. A polymer is filled into a space between the cover of the mold chase and the bottom package. The polymer is then cured. After the step of curing the polymer, the mold chase is removed, and the connector is exposed through an opening in the polymer, wherein the opening is left by the pin of the mold chase.

Abstract: A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

Abstract: Various semiconductor substrates and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor chip on a side of a first substrate. The first substrate has at least one thru-silicon-via. An insulating layer is molded on the side of the first substrate. The insulating layer provides a support structure to enable handling of the first substrate.

Abstract: A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

Abstract: A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The second surface can have a central region disposed between the first and second axes. Each microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. The terminals can be configured to carry all of the address signals transferred to the microelectronic package.

Abstract: An integrated circuit device is disclosed that includes a semiconductor substrate and a die attached to the semiconductor substrate. A conductive pillar is connected to at least one of the semiconductor substrate or the die. An overmold is molded onto the semiconductor substrate over the die, and the conductive pillar extends through the overmold.

Abstract: A method of manufacturing a semiconductor package includes placing a semiconductor chip in a recess provided on a surface of a supporting body so that a part of the semiconductor chip projects from the recess; forming a resin part on the surface of the supporting body, the resin part encapsulating the projecting part of the semiconductor chip; removing the supporting body; and forming an interconnection structure electrically connected to the semiconductor chip by using the resin part as a part of the base body of the semiconductor package.

Abstract: A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL.

Abstract: The present invention relates to a chip packaging method and structure, in which bonding pads provided on the chip are connected by a plurality of metal wires via bonding, each of the metal wires is bending in the middle part to be higher than a predetermined height, and its ends are respectively electrically connected with two of the bonding pads. A molding layer is packaged on the chip and the molding layer is higher than the predetermined height. The molding layer is sliced at the predetermined height. Two upper breakpoints of each metal wire are exposed and a substrate is attached onto the molding layer. A plurality of circuit contacts of the substrate are respectively electrically coupled with the upper breakpoints. Whereby, the invention is capable of reducing the length of the metal wires in order to improve transmission speed, but also to reduce the volume of the packaging structure.

Abstract: A semiconductor wafer has a plurality of semiconductor die distributed over a surface area. The semiconductor die are singulated from the semiconductor wafer. The semiconductor die are mounted to a carrier to form a reconstituted semiconductor wafer. The carrier has a surface area 10-50% larger than the surface area of the semiconductor wafer. The number of semiconductor die mounted to the carrier is greater than a number of semiconductor die singulated from the semiconductor wafer. The reconstituted wafer is mounted within a chase mold. The chase mold is closed with the semiconductor die disposed within a cavity of the chase mold. An encapsulant is dispersed around the semiconductor die within the cavity under temperature and pressure. The encapsulant can be injected into the cavity of the chase mold. The reconstituted wafer is removed from the chase mold. An interconnect structure is formed over the reconstituted wafer.

Abstract: Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.

Abstract: Embodiments of an interposer package structure are provided herein. Embodiments include a substrate having first and second opposing surfaces. An IC die electrically coupled to the first surface of the substrate. A plurality of contact members coupled to the first surface of the substrate. An interposer having a plurality of contact elements located on a first surface. Each conductive element coupled to a respective one of the plurality of contact members.

Abstract: Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding compound, proximate a selected surface or surfaces of a semiconductor die or dice during encapsulation are disclosed. Flow diverting structures may be included in or associated with one or more portions of a lead frame, such as a paddle, tie bars, or lead fingers. Flow diverting structures may also be inserted into a mold in association with semiconductor dice carried on non-lead frame substrates, such as interposers and circuit boards, to preferentially impede, redirect or both impede and redirect the flow of molding compound flowing between and over the semiconductor dice.

Abstract: Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.

Abstract: A chip-packaging module for a chip is provided, the chip-packaging module including a chip including a first chip side, wherein the first chip side includes an input portion configured to receive a signal; a chip carrier configured to be in electrical connection with the first chip side, wherein the chip is mounted to the chip carrier via the first chip side; and a mold material configured to cover the chip on at least the first chip side, wherein at least part of the input portion is released from the mold material.

Abstract: An embedded package includes a semiconductor chip divided into a cell region and a peripheral region, having a first surface and a second surface which faces away from the first surface, and including an integrated circuit which is formed in the cell region on the first surface, a bonding pad which is formed in the peripheral region on the first surface and a bump which is formed over the bonding pad; a core layer attached to the second surface of the semiconductor chip; an insulation component formed over the core layer including the semiconductor chip and having an opening which exposes the bump; and a circuit wiring line formed over the insulation component and the bump and electrically connected to is the bump, wherein the insulation component formed in the cell region has a thickness larger than a height of the bump.

Abstract: A semiconductor package includes a substrate, a driving chip module including a plurality of driving chips stacked on the substrate, and a molding part formed on the substrate by compressing a sheet type molding member in a semi-cured (B-stage) state to cover the driving chip module.

Abstract: Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes first and second lead frames disposed to face each other; ceramic coating layers formed on a portion of a first surface of both or one of both of the first and second lead frames; and semiconductor devices mounted on second surfaces of the first and second lead frames.

Abstract: A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process.

Abstract: In a manufacturing method of a molded package, a lead frame including an island portion and a support portion is prepared. A circuit chip is mounted on the island portion, and the sensor chip is arranged such that a first end section having an electric connecting portion is adjacent to the circuit chip and a second end section having a sensing portion is supported by the support portion. The circuit chip and the electric connecting portion of the first end section is electrically connected through a connection member. The circuit chip, the island portion, the connection member and the first end section are sealed with a resin while maintaining the support state. After the sealing, the support portion is cut from the lead frame and separated from the second end section.

Abstract: Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die.

Abstract: A substrate and a semiconductor chip are connected by means of flip-chip interconnection. Around connecting pads of the substrate and input/output terminals of the semiconductor chip, an underfill material is injected. The underfill material is a composite material of filler and resin. Also, a first main surface of the substrate, which is not covered with the underfill material, and the side surfaces of the semiconductor chip are encapsulated with a molding material. The molding material is a composite material of filler and resin. An integrated body of the substrate and the semiconductor chip, which are covered with the molding material, is thinned from above and below.

Abstract: There is provided a system and method for an externally wire bondable chip scale package in a system-in-package module. There is provided a system-in-package module comprising a substrate including a first contact pad disposed thereon, a packaged device attached to the substrate, wherein an electrode of the packaged device is wirebonded to the first contact pad, and an unpackaged device, wherein an electrode of the unpackaged device is coupled to the substrate. By flipping the packaged device within the module and utilizing wire bondable finishes on the packaged device, an externally wire bondable chip scale package may be provided. The structure of the disclosed system-in-package module provides several advantages over conventional designs including increased yields, a single assembly line, facilitated die substitution, reduced heat stress, higher package density, and a simplified single package structure for reduced fabrication time and cost.

Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: stacking and adhering a second semiconductor chip on a first semiconductor chip via an adhesive layer; adjusting at least one of an elasticity modulus of the adhesive layer, a sink amount of the adhesive layer, a thickness of a protective film at a surface of the first chip, and an elasticity modulus of the protective film such that “y” in a following formula is 70 or less; and sealing the chips by a molding resin with filler particles. y=74.7?82.7a1+273.2a2?9882a3+65.

Abstract: A process for forming semiconductor packages includes partially etching a leadframe matrix, encapsulating it with mold compound, placing a semiconductor die in a leadframe unit and singulating the leadframe matrix. A system for forming semiconductor packages includes means for partially etching a leadframe matrix, means for encapsulating it with mold compound, means for placing a semiconductor die in a leadframe unit and means for singulating the leadframe matrix.

Abstract: A substrate with a vent for a semiconductor device where the vent is integrated within the substrate itself. The integrated air vent forms a passageway or relief path for gas or air within a mold cavity to escape during a transfer molding packaging process. The vents integrated in the substrate reduce trapped gas and mold voids and limit vent flash to improve yield.

Abstract: A method for manufacturing light-emitting diode devices. Multiple metal frames are provided. The metal frames are adjacent to each other and are arranged on a same plane. Each metal frame includes a first connection pin and a second connection pin. A light-emitting diode chip is disposed on and electrically connected to each metal frame. The metal frames are respectively bent, enabling the adjacent metal frames to separate from each other. A moldboard formed with a plurality of mold cavities is provided. The bent metal frames are respectively disposed in the mold cavities, locating each light-emitting diode chip in each mold cavity. The mold cavities are respectively filled with package gel. The package gel filled in each mold cavity covers each light-emitting diode chip. The package gel is solidified. The mold cavities are separated from the package gel. The metal frames are separated from each other, forming the light-emitting diode devices.

Abstract: An integrated circuit is attached to a package substrate. The integrated circuit is electrically connected to the package substrate using a plurality of bond wires connected between a plurality of bond posts and a plurality of bond pads. A first plurality of the bond pads are along a first side of the integrated circuit and coupled to a first plurality of the bond posts with a first plurality of the bond wires. A second plurality of the bond pads are along a second side of the integrated circuit and coupled to a second plurality of the bond posts with a second plurality of the bond wires. Mold compound is injected through a plurality of openings in the package substrate. A first opening is between the first plurality of bond posts and the first side. A second opening is between the second plurality of bond posts and the second side.

Abstract: An inertial sensor, comprises a detection element detecting an amount of a physical quantity in a detection axis direction, a plurality of support members having flexibility and supporting nearly a center of the detection element, and a package substrate housing the detection element and the plurality of support members. In a case when an X-axis is defined as an extending direction of the plurality of support members, a Y-axis is perpendicular to the X-axis in a plane including the detection element, and a Z-axis is perpendicular to the X-axis and the Y-axis, one of load components in a direction of the Y-axis of the detection member applied to the plurality of support members is nearly equal to other among the plurality of support members, and one of load components in a direction of the Z-axis is nearly equal to the other among the plurality of support members.

Abstract: A chip-packaging module for a chip is provided, the chip-packaging module including an isolation material configured to cover a chip on at least one side, the isolation material having a first surface proximate to a first side of a chip, and said isolation material having a second surface facing an opposite direction to the first surface; and at least one layer in connection with the chip first side, the at least one layer further configured to extend from the chip first side to the second surface of the isolation material.

Abstract: An electronic device is disclosed. The electronic device comprises at least one electronic chip and a package for the electronic chip. The package comprises a laminate substrate, wherein the electronic chip is attached on the laminate substrate. The laminate substrate comprises one or more conduction layers, one or more insulation layers and a plurality of pads formed in a conduction layer on the side of the laminate substrate opposite to the side connected to the electronic chip. Furthermore, the package comprises an insulation body formed around the electronic chip. Moreover, the package comprises a plurality of electrodes that extend through the insulation body. For each pad of the laminate substrate, wiring is formed in the one or more of conduction layers and in one or more vias passing through the one or more insulation layers for electrically connecting the pad with at least one of the electrodes.

Abstract: The method for producing a resin package according to the present invention includes a step of forming a copper oxide layer by oxidizing the surface of a lead frame in which at least the surface is made of copper, and a step of forming a resin package main unit by allowing a resin to adhere to the copper oxide layer on the lead frame surface by resin molding for package, and then removing a predetermined area of the copper oxide layer with an acidic solution.

Abstract: The reliability of a semiconductor device is improved. A sealing resin (sealed body) is formed between a sub-substrate (first base member) and a base substrate (second base member) that are provided individually and distinctly to be integrated therewith, and then, the sub-substrate is electrically coupled to the second base member. As a means for electrically coupling the sub-substrate to the base substrate, lands (first lands) formed on the sub-substrate and lands (second lands) formed on the base substrate are disposed such that the respective positions thereof are aligned. After through holes are formed from the lands of the sub-substrate toward the lands of the base substrate, a solder member (conductive member) is formed in each of the through holes.

Abstract: An LED light module (100) for street lamp includes a frame (1), electrodes (5) and a heat sink (4) mounted in the frame, an LED chip (2) attached on a top of the heat sink; and a silicon lens (3) formed on the frame and closely sealing the LED chip therein. The LED light module is an integral structure with the silicon lens being formed thereon through an in-mold process. The silicon lens lengthwise includes two convergent parts (31, 33) at either end and a depressed part (32) at middle thereof for consecutively bridging the two convergent parts. Thus the exit light beam from the LED light module is elongated without light loss. A one-body molding process for manufacturing the LED light module is disclosed as well, which is in high-efficiency, and adapted for a mass production.

Abstract: A semiconductor apparatus includes a semiconductor device, a bed, a plurality of leads, a suspension pin, and a mold resin. The bed includes an alignment pin provided in a peripheral portion of the bed. The semiconductor device is mounted on the bed via a first solder. The plurality of leads are electrically connected to a plurality of electrodes of the semiconductor device. The suspension pin is made of the same conductive material as the lead. The suspension pin has an alignment hole in a tip of the suspension pin. The suspension pin engages the peripheral portion of the bed by the alignment pin being inserted into the alignment hole. The suspension pin is fixed to the peripheral portion of the bed by a second solder. The mold resin contains the semiconductor device, the bed, one end of the leads, and the suspension pin.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a substrate having a redistribution line thereon; mounting an integrated circuit to the substrate; and molding a transparent encapsulation over the substrate covering the integrated circuit and the redistribution line and the integrated circuit seen through the transparent encapsulation.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an integrated circuit adjacent the lead; molding an encapsulation encapsulating the lead and the integrated circuit; and forming a leveling standoff protruded from the same surface of the encapsulation as the lead with the integrated circuit between the lead and the leveling standoff electrically isolated from the lead and the integrated circuit.