Acting In Response To Ongoing Measurement Without Interruption Of Processing, E.g., Endpoint Detection, In-situ Thickness Measurement (epo) Patents (Class 257/E21.528)
  • Patent number: 10360671
    Abstract: Systems and methods for tool health monitoring and matching through integrated real-time data collection, event prioritization, and automated determination of matched states through image analysis are disclosed. Data from the semiconductor production tools can be received in real-time. A control limit impact (CLI) of the parametric data and the defect attributes data can be determined and causation factors can be prioritized. Image analysis techniques can compare images and can be used to judge tool matching, such as by identifying one of the states at which the two or more of the semiconductor manufacturing tools match.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: July 23, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Ravichander Rao, Gary Taan, Andreas Russ, Bjorn Brauer, Roger Davis, Bryant Mantiply, Swati Ramanathan, Karen Biagini
  • Patent number: 10290525
    Abstract: Disclosed is a method for marking, by using a laser marker, a plurality of wafer dice divided by a wafer dicing process. The disclosed marking method for wafer dice comprises the steps of: setting a plurality of scan regions having a mutually overlapping portion on a wafer including the wafer dice; scanning the scan regions of the wafer a plurality of times by using a line scan camera; collecting position information of each of wafer dice located in regions in which the scan regions do not overlap; collecting, through image synthesis, position information of each of wafer dice located in regions in which the scan regions overlap; and marking, by using the laser marker, each of all the wafer dice of which the position information has been collected.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: May 14, 2019
    Assignee: EO TECHNICS CO., LTD.
    Inventors: Sun Jung Kim, Jae Man Choi, Sung Beom Jung, Jung Jin Seo
  • Patent number: 10236223
    Abstract: Disclosed is a substrate processing method. The substrate processing method includes: a first acquisition step of acquiring a first processing condition in a first processing performed using a first number of monitor substrates and a first processing result related to the monitor substrates; a second acquisition step of acquiring a second processing condition in a second processing performed using a second number of monitor substrates and a second processing result related to the monitor substrates; a first calculation step of calculating a processing condition difference between the first processing condition and the second processing condition; and a second calculation step of calculating a processing result of substrates at slot positions where no monitor substrate is placed in the first processing, based on the first processing result, the second processing result, the processing condition difference, and a process model representing a relationship between a processing condition and a processing result.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: March 19, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Yuichi Takenaga, Takanori Saito
  • Patent number: 10209300
    Abstract: Methods and systems for manufacturing and analyzing interconnect structures in integrated circuit (IC) devices. The methods include forming an interconnect structure, such as a pillar, in an IC device. The pillar is analyzed using an opto-acoustic sensor to quantify physical characteristics used to determine whether the pillar satisfies predetermined quality criterion. The analysis includes capturing an opto-acoustic signal from the pillar and estimating optical parameters for a number of local maxima of the signal. A mode may then be fitted for each of the identified local maxima based on the optical characteristics. The modes and estimated optical parameters may then be iteratively corrected in an order from strongest to weakest local maximum. The corrected values may then be compared to a predicted physical model to identify the physical characteristics of the pillar. If the physical characteristics fall outside of the quality criterion, manufacturing processes may be altered.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: February 19, 2019
    Assignee: Rudolph Technologies, Inc.
    Inventors: Michael Kotelyanskii, Roman Basistyy
  • Patent number: 10203596
    Abstract: A method of filtering overlay data by field is provided in the present invention. The method includes the following steps. A minimum number of measure points per field on a semiconductor substrate is decided. Field data filtering rules are set. Overlay raw data is inputted. A raw data filtration is performed to the overlay raw data by field according to the field data filtering rules. Modified exposure parameters are generated for each field according to overlay data of remaining measure points per field after the raw data filtration when the number of the remaining measure points per field is larger than or equal to the minimum number of the measure points per field. Accordingly, the modified exposure parameters will be more effective in reducing the overlay error because more outliers may be filtered out before generating the modified exposure parameters.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: February 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Che-Yi Lin
  • Patent number: 10114368
    Abstract: Inspection apparatus includes an imaging module, which is configured to capture images of defects at different, respective locations on a sample. A processor is coupled to process the images so as to automatically assign respective classifications to the defects, and to autonomously control the imaging module to continue capturing the images responsively to the assigned classifications.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: October 30, 2018
    Assignee: APPLIED MATERIALS ISRAEL LTD.
    Inventors: Gadi Greenberg, Idan Kaizerman, Zeev Zohar
  • Patent number: 9996647
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 12, 2018
    Assignee: Lam Research Corporation
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Patent number: 9911577
    Abstract: An arrangement for controlling a plasma processing system is provided. The arrangement includes an RF sensing mechanism for obtaining an RF voltage signal. The arrangement also includes a voltage probe coupled to the RF sensing mechanism to facilitate acquisition of the signal while reducing perturbation of RF power driving a plasma in the plasma processing system. The arrangement further includes a signal processing arrangement configured for receiving the signal, split the voltage signals into a plurality of channels, convert the signals into a plurality of direct current (DC) signals, convert the DC signals into digital signals and process the digital signal in a digital domain to generate a transfer function output. The arrangement moreover includes an ESC power supply subsystem configured to receive the transfer function output as a feedback signal to control the plasma processing system.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: March 6, 2018
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Henry S. Povolny
  • Patent number: 9846135
    Abstract: A moisture sensor arrangement including a plate-like semiconductor substrate and an integrated signal processing component disposed on a first side of the semiconductor substrate. The moisture sensor arrangement including a capacitive moisture sensor connected electrically conductively to the integrated signal processing component, wherein the capacitive moisture sensor is disposed on either the first side or a second side of the semiconductor substrate that is opposite the first side of the semiconductor substrate. In addition, the plate-like semiconductor substrate includes 1) plated through-holes, by way of which elements on the first side and the second side of the semiconductor substrate are electrically connectable to one another; and 2) a temperature sensor integrated with the integrated signal processing component.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: December 19, 2017
    Assignee: E+E ELEKTRONIK GES.M.B.H
    Inventors: Elmar Mayer, Georg Niessner, Joachim Runck
  • Patent number: 9818629
    Abstract: Provided is a substrate processing apparatus capable of efficiently resuming processing of unprocessed substrates after an error occurs during processing of substrates. In the substrate processing apparatus that executes a recipe defining an order of processing substrates and manages process status of the substrates, the process status are changed to a processing state so as to execute the recipe, are changed to a paused state when unprocessed substrates are present among the substrates to be processed according to the recipe, due to an error occurring during the execution of the recipe, and are changed from the paused state to the processing state to resume the execution of the recipe so as to process the unprocessed substrates when the error is canceled and a operation is performed to resume the execution of the recipe.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: November 14, 2017
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventor: Makoto Shirakawa
  • Patent number: 9792393
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: October 17, 2017
    Assignee: Lam Research Corporation
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Patent number: 9767997
    Abstract: A plasma processing apparatus includes: a detector configured to detect a change in an intensity of light emission from plasma formed inside a processing chamber; and a unit configured to adjust conditions for forming the plasma or processing a wafer arranged inside the processing chamber using an output from the detector, wherein the detector detects a signal of the intensity of light emission at plural time instants before an arbitrary time instant during processing, and wherein the adjusting unit removes the component of a temporal change of a long cycle of the intensity of light emission from this detected signal and detects the component of a short temporal change of the intensity of light emission, and adjusts the conditions for forming the plasma or processing a wafer arranged inside the processing chamber based on the short temporal change of the detected intensity of light emission.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: September 19, 2017
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Masahito Togami, Tatehito Usui, Kosa Hirota, Satomi Inoue, Shigeru Nakamoto
  • Patent number: 9714473
    Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: July 25, 2017
    Assignee: Microfabrica Inc.
    Inventors: Uri Frodis, Adam L. Cohen, Michael S. Lockard
  • Patent number: 9673113
    Abstract: Systems and methods are provided for controlling a polishing process in real-time. First and second characteristics are identified in first and second data sets, respectively, with each data set corresponding to a real-time wafer polishing data. A time delta is computed between the times at which the first and second characteristics occur within their respective data sets, and polishing parameters are then updated in real-time based on the computed time delta.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: June 6, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jamie S. Leighton, Yee Sheen Pong
  • Patent number: 9590151
    Abstract: A method is provided for producing a plurality of radiation-emitting semiconductor chips, having the following steps: providing a plurality of semiconductor bodies (1) which are suitable for emitting electromagnetic radiation from a radiation exit face (3), applying the semiconductor bodies (1) to a carrier (2), applying a first mask layer (4) to regions of the carrier (2) between the semiconductor bodies (1), applying a conversion layer (5) to the entire surface of the semiconductor bodies (1) and the first mask layer (4) using a spray coating method, and removing the first mask layer (4), such that in each case a conversion layer (5) arises on the radiation exit faces (3) of the semiconductor bodies (1).
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 7, 2017
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Markus Richter, Alexander Baumgartner, Hans-Christoph Gallmeier, Tony Albrecht
  • Patent number: 9583405
    Abstract: Methods and apparatus for spectrum-based endpointing. An endpointing method includes selecting a reference spectrum. The reference spectrum is a spectrum of white light reflected from a film of interest on a first substrate and has a thickness greater than a target thickness. The reference spectrum is empirically selected for particular spectrum-based endpoint determination logic so that the target thickness is achieved when endpoint is called by applying the particular spectrum-based endpoint logic. The method includes obtaining a current spectrum. The current spectrum is a spectrum of white light reflected from a film of interest on a second substrate when the film of interest is being subjected to a polishing step and has a current thickness that is greater than the target thickness. The method includes determining, for the second substrate, when an endpoint of the polishing step has been achieved. The determining is based on the reference and current spectra.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: February 28, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Dominic J. Benvegnu, Jeffrey Drue David, Boguslaw A. Swedek
  • Patent number: 9482519
    Abstract: The present invention relates generally to metrology, and more particularly, to an apparatus and method of measuring multiple parameters of a structure or feature of a semiconductor device using a combination of stepwise optical metrology and a linear system of equations to generate an output as function of position. In an embodiment, a light beam having a width greater than the features to be measured may be shined on a first area of the semiconductor device to calculate a first average. The light beam may then be shined on a second area that overlaps the first area by at least one individual feature to calculate a second average. The averages may be entered into a system of linear equations which may then be solved to calculate an overall average.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: November 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Yunlin Zhang
  • Patent number: 9390323
    Abstract: Methods, systems, and computer program products relate to recommending sites including identifying a location associated with a computing device, analyzing metadata of geotagged image data, the image data including blocked image data, and suggesting sites near the identified location based on the results of the metadata analysis.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: July 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Peters, Dana L. Price, James C. Riordan, Belinda M. Vennam, Ramratan Vennam
  • Patent number: 9368941
    Abstract: A device includes an array of optical transmitters having first and second temperature sensors each disposed at or near a first and second end of the array of the transmitters. The device includes a controller in communication with the temperature sensors and the transmitters. The controller receives temperature measurements from the temperatures sensors and determines a temperature difference between a first temperature measurement of the first temperature sensor and a second temperature measurement of the second temperature sensor. The controller determines a compensation for each transmitter within the transmitter array based on the temperature difference and a transmitter position within the array of transmitters. The compensation causes the corresponding transmitter to transmit at a wavelength associated with that transmitter. The controller executes the compensations for the transmitters.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: June 14, 2016
    Assignee: Google Inc.
    Inventors: Pedram Zare Dashti, Changhong Joy Jiang, Jun Zheng, Yi Wang
  • Patent number: 8986560
    Abstract: A method for producing an optical semiconductor device includes the steps of determining a wafer size to make a section arrangement including a plurality of sections in each of which the optical semiconductor device including a semiconductor mesa is formed; obtaining an in-plane distribution of a thickness of a resin layer on a wafer; obtaining a correlation between a thickness of a resin layer and a trench width; forming a trench width map using the in-plane distribution of the thickness and the correlation; preparing an epitaxial substrate by forming a stacked semiconductor layer; forming, on the epitaxial substrate, a mask based on the trench width map; forming a trench structure including the semiconductor mesa by etching the stacked semiconductor layer using the mask; forming a resin layer on the trench structure; and forming an opening on the semiconductor mesa by etching the resin layer.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takamitsu Kitamura, Hideki Yagi
  • Patent number: 8936948
    Abstract: A hard mask, a protective film, which protects the hard mask film from oxidation, a first mask film and a first organic film are sequentially stacked. The first organic film is processed into a first pattern, and the first mask film is etched using the patterned first organic film as a mask. After the first organic film is removed, a second organic film is formed. The second organic film is processed into a second pattern. The first mask film is secondary etched using the patterned second organic film as a mask so that the surface of the first mask film is exposed but the surface of the protective film is not exposed, thereby selectively patterning only the first mask film. After that, when removing the residual second organic film by ashing, it is possible to ensure the function of the protective film that protects the hard mask film from oxidation.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: January 20, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Osamu Fujita
  • Patent number: 8916874
    Abstract: Sacrificial optical test structures are constructed upon a wafer of pre-cleaved optical chips for testing the optical functions of the pre-cleaved optical chips. The sacrificial optical structures are disabled upon the cleaving the optical chips from the wafer and the cleaved optical chips can be used for their desired end functions. The test structures may remain on the cleaved optical chips or they may be discarded.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: December 23, 2014
    Assignee: Oclaro Technology Limited
    Inventors: Neil David Whitbread, Lloyd Nicholas Langley, Andrew Cannon Carter
  • Patent number: 8900886
    Abstract: A method of semiconductor processing comprises providing a semiconductor wafer in a processing chamber; feeding at least one tungsten-containing precursor in a gas state into the processing chamber for atomic layer deposition (ALD) of tungsten; feeding at least one reducing chemical in a gas state into the processing chamber; and monitoring a concentration of at least one gaseous byproduct in the chamber; and providing a signal indicating concentration of the at least one gaseous byproduct in the chamber. The byproduct is produced by a reaction between the at least one tungsten-containing precursor and the at least one reducing chemical during the ALD.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kun-Ei Chen, Jen-Yi Chen, Yi-Chung Lin, Chen-Chieh Chiang, Ling-Sung Wang
  • Patent number: 8877655
    Abstract: The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD).
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: November 4, 2014
    Assignee: ASM America, Inc.
    Inventors: Eric J. Shero, Petri I. Raisanen, Sung-Hoon Jung, Chang-Gong Wang
  • Patent number: 8846417
    Abstract: An optoelectronic device including at least one of a solar device, a semiconductor device, and an electronic device. The device includes a semiconductor unit. A plurality of metal fingers is disposed on a surface of the semiconductor unit for electrical conduction. Each of the metal fingers includes a pad area for forming an electrical contact. The optoelectronic device includes a plurality of pad areas that is available for connection to a bus bar, wherein each of the metal fingers is connected to a corresponding pad area for forming an electrical contact.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: September 30, 2014
    Assignee: Alta Devices, Inc.
    Inventor: Andreas Hegedus
  • Patent number: 8841146
    Abstract: A method for fabricating light emitting diode (LED) dice includes the steps of coating a transparent substrate with a wavelength conversion material, continuously evaluating a correlated color temperature (CCT) of the output electromagnetic radiation produced by the wavelength conversion material and comparing the correlated color temperature (CCT) to a target correlated color temperature (CCT), and controlling the coating step responsive to feedback from the evaluating and comparing step to adjust the correlated color temperature (CCT) to achieve the target correlated color temperature (CCT). A system for fabricating light emitting diode (LED) dice includes a coating system, a monitoring system, and a control system configured to control the coating system to adjust the correlated color temperature (CCT) of the wavelength conversion material on the transparent substrate to achieve the target correlated color temperature (CCT).
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: September 23, 2014
    Assignee: SemiLEDS Optoelectronics Co., Ltd.
    Inventors: Jui-Kang Yen, Georg Soerensen, Mark Ewing Tuttle
  • Patent number: 8809075
    Abstract: The method for filling a liquid material, and the apparatus and the program make it possible, without changing a moving speed of an ejection device, to correct a change in ejection amount and to stabilize an application shape. The method fills a liquid material into a gap between a substrate and a work by using the capillary action. The method includes the steps of: generating an application pattern consisting of a plurality of application areas continuous to one another; assigning a plurality of ejection cycles, each obtained by combining the number of ejection pulses and the number of pause pulses at a predetermined ratio therebetween, to each of the application areas; and measuring an ejection amount at correction intervals and calculating a correction amount for the ejection amount.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: August 19, 2014
    Assignee: Musashi Engineering, Inc.
    Inventor: Kazumasa Ikushima
  • Patent number: 8753901
    Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: June 17, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ertle Werner, Bernd Goller, Michael Horn, Bernd Kothe
  • Publication number: 20140106476
    Abstract: A method for etching a layer is provided. A substrate is provided in a chamber. An etch plasma for etching a layer on the substrate is generated. Light from a first region of the chamber is measured to provide a first signal. Light from a second region of the chamber is measured to provide a second signal. The first signal with the second signal are compared to determine an etch endpoint.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Applicant: Lam Research Corporation
    Inventor: Evelio SEVILLANO
  • Patent number: 8685265
    Abstract: An etching apparatus includes a process unit and a control unit. Emission intensity of plasma inside the process unit is obtained by an OES detector, a nonlinear regression analysis is performed by an etching control device to determine a regression formula. The nonlinear regression analysis is performed by using the emission intensity of the plasma obtained until a first time when the emission intensity of the plasma passes a peak, and a second time to be an etching end point is calculated by using the regression formula. The etching end point is calculated as a time when the emission intensity decreases for a predetermined value from the first time. The etching apparatus finishes an etching when the process reaches the etching end point. It is thereby possible to control the etching end point with high-accuracy.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: April 1, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yoshiyuki Nakao, Kazuo Hashimi
  • Publication number: 20140030826
    Abstract: A method of polishing a wafer having a Ru film and a Ta film or TaN film beneath the Ru film is provided. This polishing method includes: polishing the Ru film by bringing the wafer into sliding contact with a polishing pad; measuring a thickness of the Ru film by a film thickness sensor while polishing the Ru film; calculating a derivative value of an output value of the film thickness sensor; detecting a predetermined point of change in the derivative value; and determining a removal point of the Ru film from a point of time when the point of change is detected.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 30, 2014
    Inventors: Shinrou Ohta, Toshikazu Nomura, Takeshi Iizumi
  • Publication number: 20140004626
    Abstract: Methods for chemical mechanical polishing (CMP) of semiconductor substrates, and more particularly to temperature control during such chemical mechanical polishing are provided. In one aspect, the method comprises polishing the substrate with a polishing surface during a polishing process to remove a portion of the conductive material, repeatedly monitoring a temperature of the polishing surface during the polishing process, and exposing the polishing surface to a rate quench process in response to the monitored temperature so as to achieve a target value for the monitored temperature during the polishing process.
    Type: Application
    Filed: June 30, 2012
    Publication date: January 2, 2014
    Applicant: Applied Materials, Inc.
    Inventors: KUN XU, Jimin Zhang, David H. Mai, Stephen Jew, Shih-Haur Walters Shen, Zhihong Wang, Thomas H. Osterheld, Wen-Chiang Tu, Gary Ka Ho Lam, Tomohiko Kitajima
  • Publication number: 20130341620
    Abstract: In accordance with an embodiment of the present invention, a method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Albert Birner, Tobias Herzig
  • Publication number: 20130323859
    Abstract: A method of semiconductor processing comprises providing a semiconductor wafer in a processing chamber; feeding at least one tungsten-containing precursor in a gas state into the processing chamber for atomic layer deposition (ALD) of tungsten; feeding at least one reducing chemical in a gas state into the processing chamber; and monitoring a concentration of at least one gaseous byproduct in the chamber; and providing a signal indicating concentration of the at least one gaseous byproduct in the chamber. The byproduct is produced by a reaction between the at least one tungsten-containing precursor and the at least one reducing chemical during the ALD.
    Type: Application
    Filed: June 1, 2012
    Publication date: December 5, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kun-Ei CHEN, Jen-Yi CHEN, Yi-Chung LIN, Chen-Chieh CHIANG, Ling-Sung WANG
  • Patent number: 8546152
    Abstract: A method of fabricating non-volatile memory is provided for memory cells employing a charge storage element with multiple charge storage regions. A first charge storage layer is formed over a tunnel dielectric layer at both a memory array region and an endpoint region of a semiconductor substrate. The first charge storage layer is removed from the endpoint region to expose the tunnel dielectric region. A second charge storage layer is formed over the first charge storage layer at the memory array region and over the tunnel dielectric layer at the endpoint region. When etching the second charge storage layer to form the stem regions of the memory cells, the tunnel dielectric layer provides a detectable endpoint signal to indicate that etching for the second charge storage layer is complete.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: October 1, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Takashi Orimoto, George Matamis, James Kai, Vinod Robert Purayath
  • Patent number: 8532796
    Abstract: The invention provides a systems and methods for creating Double Pattern (DP) structures on a patterned wafer in real-time using Dual Pattern Contact-Etch (DPCE) processing sequences and associated Contact-Etch-Multi-Input/Multi-Output (CE-MIMO) models. The DPCE processing sequences can include one or more contact-etch procedures, one or more measurement procedures, one or more contact-etch modeling procedures, and one or more contact-etch verification procedures. The CE-MIMO model uses dynamically interacting behavioral modeling between multiple layers and/or multiple contact-etch procedures. The multiple layers and/or the multiple contact-etch procedures can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created during Double Patterning (DP) procedures.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: September 10, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Daniel J Prager, Merritt Funk, Peter Biolsi, Ryukichi Shimizu
  • Patent number: 8507297
    Abstract: A wafer containing a plurality of electro-optical devices, each device being enclosed in chamber that has a translucent cover. An X-Y matrix of pairs of interconnections on the wafer are connected to the circuitry of the electro-optical devices for addressing the electro-optical devices. The pairs of interconnections extend outside of the chambers enclosing the devices to testing areas on the periphery of the wafer. Testing is done by signals applied through the interconnections while simultaneously exposing the devices to light through the translucent covers.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: August 13, 2013
    Assignee: Spatial Photonics, Inc.
    Inventors: Shaoher X. Pan, Vlad Novotny
  • Patent number: 8501499
    Abstract: The invention provides a method of processing a wafer using Ion Energy (IE)-related multilayer process sequences and Ion Energy Controlled Multi-Input/Multi-Output (IEC-MIMO) models and libraries that can include one or more measurement procedures, one or more IEC-etch sequences, and one or more Ion Energy Optimized (IEO) etch procedures. The IEC-MIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple IEC etch sequences. The multiple layers and/or the multiple IEC etch sequence can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using IEO etch procedures.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: August 6, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Radha Sundararajan, Merritt Funk, Lee Chen, Barton Lane
  • Publication number: 20130157387
    Abstract: The present disclosure relates to a semiconductor body etching apparatus having a multi-zone end point detection system. In some embodiments, the multi-zone end point detection system has a processing chamber that houses a workpiece that is etched according to an etching process. A plurality of end point detector (EPD) probes are located within the processing chamber. Respective EPD probes are located within different zones in the processing chamber, thereby enabling the detection of end point signals from multiple zones within the processing chamber. The detected end point signals are provided from the plurality of EPD probes to an advanced process control (APC) unit. The APC unit is configured to make a tuning knob adjustment to etching process parameters based upon the detected end point signals and to thereby account for etching non-uniformities.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-An Chen, Yen-Shuo Su, Ying Xiao, Chin-Hsiang Lin
  • Publication number: 20130157388
    Abstract: A method and apparatus for etching a photomask substrate with enhanced process monitoring is provided. In one embodiment, a method of determining an etching endpoint includes performing an etching process on a first tantalum containing layer through a patterned mask layer, directing a radiation source having a first wavelength from about 200 nm and about 800 nm to an area uncovered by the patterned mask layer, collecting an optical signal reflected from the area covered by the patterned mask layer, analyzing a waveform obtained the reflected optical signal reflected from the substrate from a first time point to a second time point, and determining a first endpoint of the etching process when a slope of the waveform is changed about 5 percent from the first time point to the second time point.
    Type: Application
    Filed: July 6, 2012
    Publication date: June 20, 2013
    Inventor: Michael Grimbergen
  • Patent number: 8465589
    Abstract: A method of manufacture of CIGS photovoltaic cells and modules involves sequential deposition of copper indium gallium diselenide compounds in multiple thin sublayers to form a composite CIGS absorber layer of a desirable thickness greater than the thickness of each sublayer. In an embodiment, the method is adapted to roll-to-roll processing of CIGS PV cells. In an embodiment, the method is adapted to preparation of a CIGS absorber layer having graded composition through the layer. In a particular embodiment, the graded composition is enriched in copper at a base of the layer. In an embodiment, each CIGS sublayer is deposited by co-evaporation of copper, indium, gallium, and selenium which react in-situ to form CIGS.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: June 18, 2013
    Assignee: Ascent Solar Technologies, Inc.
    Inventors: Prem Nath, Venugopala R. Basava, Ajay Kumar Kalla, Peter Alex Shevchuk, Mohan S. Misra
  • Publication number: 20130130409
    Abstract: A method and apparatus for etching a photomask substrate with enhanced process monitoring, for example, by providing for optical monitoring at different regions of the photomask to obtain desired etch rate or thickness loss is provided. In one embodiment, the method includes performing an etching process on a reflective multi-material layer that includes at least one molybdenum layer and one silicon layer through a patterned mask, directing radiation having a wavelength from about 170 nm and about 800 nm to an area of the multi-material layer uncovered by the patterned mask, collecting an optical signal reflected from the area uncovered by the patterned mask, analyzing a waveform obtained from the reflected optical signal, and determining a first endpoint of the etching process when an intensity of the reflected optical signal is between about 60 percent and about 90 percent less than an initial reflected optical signal.
    Type: Application
    Filed: July 8, 2012
    Publication date: May 23, 2013
    Inventor: Michael Grimbergen
  • Patent number: 8445296
    Abstract: Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: May 21, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Rhone Wang, Tzu-Cheng Lin, Yu-Jen Cheng, Chih-Wei Lai, Hung-Pin Chang, Tsang-Jiuh Wu
  • Patent number: 8420498
    Abstract: An alignment method of chips that are formed on a surface of a semiconductor wafer with alignment marks corresponding to the chips includes the steps of irradiating an alignment mark corresponding to a predetermined alignment chip in a predetermined area including the chips with a laser light; detecting reflected waves from the alignment mark of the predetermined alignment chip to obtain a position of the alignment mark of the predetermined alignment chip; irradiating an alignment mark of an alternative chip different from the predetermined alignment chip with the laser light in case of not being able to obtain the position of the alignment mark of the predetermined alignment chip; obtaining a position of the alignment mark of the alternative chip by detecting the reflected waves from the alignment mark of the alternative chip; and aligning the chips in the predetermined area based on positions of alignment marks including the position of the alignment mark of the alternative chip.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: April 16, 2013
    Assignee: Mitsumi Electric Co., Ltd.
    Inventor: Yukihiro Tanemura
  • Publication number: 20130071955
    Abstract: A method for processing a substrate to form a desired pattern by an etching process after forming a mask pattern over the substrate includes the steps of: forming two layers over the substrate; measuring a width of the mask pattern or an etched pattern of one of the two layers; and adjusting a flow rate of any one of HBr and other gases, used in the etching process, based on the measured width. The two layers may include a silicon nitride layer and an organic dielectric layer.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Applicant: Tokyo Electron Limited
    Inventors: Hiroki Kintaka, Toshihisa Ozu, Masahiko Takahashi
  • Publication number: 20130065328
    Abstract: A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material The sound wave is detected using a sensor. A topography of the top surface is determined based on the detected sound wave. The determined topography is used to control an immersion lithography process.
    Type: Application
    Filed: September 8, 2011
    Publication date: March 14, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Pan WANG, Chien-Hsuan Liu, Ching-Hsien Chen, Chao-Chi Chen
  • Publication number: 20130052754
    Abstract: A vapor growth method includes: loading a wafer into a reaction chamber and placing the wafer on a support unit; heating the wafer with a heater provided below the support unit and controlling an output of the heater so that the wafer reaches a predetermined temperature; rotating the wafer and supplying process gas onto the wafer, thereby forming a film on the wafer; unloading the wafer from the reaction chamber; supplying etching gas into the reaction chamber and removing a reaction product deposited inside the reaction chamber by etching; and detecting an etching end point based on variation in a first temperature, which is a temperature on the support unit when the output of the heater is controlled to have a predetermined amount, or variation in the output of the heater, which is controlled so that the first temperature reaches a predetermined temperature.
    Type: Application
    Filed: August 29, 2012
    Publication date: February 28, 2013
    Inventors: Kouki ZAITSU, Yuusuke SATO
  • Publication number: 20130052757
    Abstract: Methods for optimizing a plasma process are provided. The method may include obtaining a measurement spectrum from a plasma reaction in a chamber, calculating a normalized measurement standard and a normalized measurement spectrum of the measurement spectrum, comparing the normalized measurement spectrum with a normalized reference spectrum, and comparing the normalized measurement standard with a normalized reference standard to determine whether to change a process parameter of the plasma process or clean the chamber when the normalized measurement spectrum and the normalized reference spectrum are mismatched.
    Type: Application
    Filed: August 30, 2012
    Publication date: February 28, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sangwuk Park, Kye Hyun Baek, Kyoungsub Shin, Brad H. Lee
  • Publication number: 20130052755
    Abstract: A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.
    Type: Application
    Filed: August 26, 2011
    Publication date: February 28, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
  • Publication number: 20130045546
    Abstract: An efficient method of detecting defects in metal patterns on the surface of wafers. Embodiments include forming a metal pattern on each of a plurality of wafers, polishing each wafer, and analyzing the surface of the metal pattern on each polished wafer for the presence of defects in the metal pattern by analyzing an optical across-wafer endpoint signal, generated at the endpoint of polishing. Embodiments include determining the location of defects in the metal pattern by determining the position of non-uniformities in the optical-across-wafer endpoint signal.
    Type: Application
    Filed: August 16, 2011
    Publication date: February 21, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: Mike Schlicker