Acting In Response To Ongoing Measurement Without Interruption Of Processing, E.g., Endpoint Detection, In-situ Thickness Measurement (epo) Patents (Class 257/E21.528)
  • Publication number: 20080233662
    Abstract: An advanced process control (APC) method for semiconductor fabrication is provided. A first substrate and a second substrate are provided. The first substrate and the second substrate include a dielectric layer. A first etch process parameter for the first substrate is determined. A trench is etched in the dielectric layer of the first substrate using the first etch process parameter. At least one aspect of the etched trench of the first substrate is measured. A second etch process parameter for the second substrate is determined using the measured aspect of the etched trench of the first substrate. A planarization process parameter for the first substrate is determined also using the measured aspect of the etched trench of the first substrate.
    Type: Application
    Filed: March 21, 2007
    Publication date: September 25, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsueh Chi Shen, Chun-Hsien Lin
  • Publication number: 20080227225
    Abstract: The present invention relates to a method of manufacturing a semiconductor device wherein etching is performed on films on a wafer using a plasma treatment apparatus. In the manufacturing method according to the present invention, a change in the difference between the emission intensities of a first wavelength component and a second wavelength component in plasma is monitored during etching. If the amount of change in the difference per unit time exceeds a predetermined threshold a given number of times in a row, then the flow rate of oxygen introduced to the plasma treatment apparatus is increased or, if the amount of change exceeding the predetermined threshold has not been seen, then the oxygen flow rate is set back to the original value thereof. This series of actions is repeated all the time during a set period of time.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 18, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Yasuhiko Ueda
  • Publication number: 20080224322
    Abstract: This invention is directed to offer a semiconductor device having a stacked layer structure and its manufacturing method that bring high yield and reliability. Semiconductor dice judged as good dice are stacked on a base substrate in which through holes and through hole electrodes are formed. Next, a protection layer to cover the semiconductor dice is formed. It is preferable that the protection layer is composed of a plurality of resin layers (a first resin layer and a second resin layer) that are different in hardness from each other. Then, a conductive terminal that is connected with the through hole electrode is formed on a back surface of the base substrate. Next, the second resin layer and the base substrate are cut along predetermined dicing lines and separated into individual semiconductor devices in chip form. As described above, a process step of separation into the semiconductor devices is performed while each of the semiconductor dice is mounted on the base substrate in wafer form.
    Type: Application
    Filed: March 14, 2008
    Publication date: September 18, 2008
    Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventor: Hiroyuki SHINOGI
  • Publication number: 20080213925
    Abstract: A process system adapted for processing of or with a material therein. The process system includes: a sampling region for the material; an infrared photometric monitor constructed and arranged to transmit infrared radiation through the sampling region and to responsively generate an output signal correlative of the material in the sampling region, based on its interaction with the infrared radiation; and process control means arranged to receive the output of the infrared photometric monitor and to responsively control one or more process conditions in and/or affecting the process system.
    Type: Application
    Filed: May 13, 2008
    Publication date: September 4, 2008
    Applicant: ADVANCED TECHNOLOGY MATERIALS, INC.
    Inventor: Jose I. Arno
  • Publication number: 20080188013
    Abstract: The present invention generally provides methods and apparatus for monitoring ion dosage during a plasma process. One embodiment of the present invention provides a method for processing a substrate comprising generating a correlation between the at least one attribute of the plasma and a dosage quantity.
    Type: Application
    Filed: February 4, 2008
    Publication date: August 7, 2008
    Inventors: Seon-Mee Cho, Majeed A. Foad
  • Publication number: 20080179005
    Abstract: There is provided a plasma processing apparatus includes a lower electrode in a processing chamber on which a object to be processed is mounted; an upper electrode confronting the lower electrode; a first and a second high-frequency power supply for applying high-frequency powers respectively to the upper and the lower electrode; and an output controller for raising each of outputs from the high-frequency power supplies at least three times in a stepwise manner up to each of set levels for processing the object to be processed. The output controller adjusts each of rising times of the outputs from the high-frequency power supplies so that an output of the second high-frequency power supply is raised earlier than an output of the first high-frequency power supply while the outputs from the high-frequency power supplies are raised up to the set levels in a stepwise manner.
    Type: Application
    Filed: March 26, 2008
    Publication date: July 31, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Naoto SAGAE, Hiroshi Tsuchiya, Tsutomu Higashiura, Hideo Kato, Ryuji Ohtani
  • Patent number: 7405091
    Abstract: The present invention is a method for testing a contact open capable of effectively testing a contact open defect in an In-line as securing a mass productivity. The method includes the steps of: performing a photolithography process for forming a contact; forming a contact hole by performing a contact etching process after sampling at least one wafer; depositing a conductive layer on the wafer provided with the contact hole; isolating the conductive layer within the contact hole; performing a test for testing a contact open interface to check whether a remaining layer is existed in an interface between the conductive layer and a lower structure of the conductive layer; and performing a process for etching the contact of a main lot based on a test result.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: July 29, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung-Kwon Lee, Tae-Woo Jung, Min-Suk Lee
  • Publication number: 20080153180
    Abstract: An integrated circuit wafer system includes an integrated circuit wafer, measuring thicknesses of the integrated circuit wafer, calculating a change in temperature ramp rates and thickness offsets for subsequent processing based on the temperature ramp rates for prior processing and the resultant thicknesses, and calculating an average temperature and deposition time for subsequent processing based on calculated changes in temperature ramp rates, coupled with the average temperature, deposition time for prior processing, and the resultant thicknesses.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Applicant: SPANSION LLC
    Inventors: Christopher Hans Lansford, Qinghua He
  • Patent number: 7364993
    Abstract: A semiconductor material with photoconductive properties and a method of the semiconductor, wherein a base material is grown and then annealed post-growth at a temperature of 475° C. or less. It has been found that be annealing at temperatures of 475° C., or less the carrier lifetime of the material and the resistivity can be optimized so as to obtain semiconductor with useful photoconductive properties.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: April 29, 2008
    Assignee: TeraView Limited
    Inventors: Michael J. Evans, William R. Tribe
  • Publication number: 20080090310
    Abstract: A substrate processing apparatus capable of completely removing an oxide layer that can cause defects in electronic devices, without lowering throughput of the apparatus. A process ship of the substrate processing apparatus includes a process module in which COR processing is performed on a wafer and another process module in which PHT processing is performed on a wafer. The latter process module includes a process module exhaust system through which volatile gases and other gases in a chamber are exhausted. This exhaust system includes an analysis unit communicated with a main exhaust pipe between the chamber and an APC valve and adapted to measure concentrations of the volatile gases in the exhausted gases and detect a termination of the PHT processing.
    Type: Application
    Filed: September 12, 2007
    Publication date: April 17, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Susumu SAITO
  • Patent number: 7358187
    Abstract: The present invention provides a coating process for patterned substrate surfaces, in which a substrate (101) is provided, the substrate having a surface (105) which is patterned in a substrate patterning region (102) and has one or more trenches (106) that are to be filled to a predetermined filling height (205), a catalyst layer (201) is introduced into the trenches (106) that are to be filled, a reaction layer (202) is deposited catalytically in the trenches (106) that are to be filled, the catalytically deposited reaction layer (202) is densified in the trenches (106) that are to be filled, and the introduction of the catalyst layer (201) and the catalytic deposition of the reaction layer (202) are repeated until the trenches (106) that are to be filled have been filled to the predetermined filling height (205).
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: April 15, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas Hecht, Stefan Jakschik, Uwe Schröder
  • Publication number: 20080070327
    Abstract: In a plasma processing method, a correlation between substrate type data and optical data is obtained by using a multivariate analysis; substrate type data is obtained from optical data based on the correlation when initiating a plasma processing; and a substrate type is determined by using the obtained substrate type data. Further, a setting data set corresponding to the determined substrate type is selected from setting data sets, each for detecting a plasma processing end point of the plasma processing, each of the setting data sets being stored in advance in a data storage unit; an end point of the plasma processing is detected based on the selected setting data set; and the plasma processing is terminated at the detected end point.
    Type: Application
    Filed: March 16, 2007
    Publication date: March 20, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kosuke OGASAWARA, Susumu Saito, Syuji Nozawa
  • Publication number: 20080032428
    Abstract: A method and system for controlling a dimension of an etched feature. The method includes: measuring a mask feature formed on a top surface of a layer on a substrate to obtain a mask feature dimension value; and calculating a mask trim plasma etch time based on the mask feature dimension value, a mask feature dimension target value, a total of selected radio frequency power-on times of a plasma etch tool since an event occurring to a chamber or chambers of a plasma etch tool for plasma etching the layer, and an etch bias target for a layer feature to be formed from the layer where the layer is not protected by the mask feature during a plasma etch of the layer.
    Type: Application
    Filed: October 15, 2007
    Publication date: February 7, 2008
    Inventors: Gary Behm, Teresita Magtoto, Rajiv Ranade
  • Publication number: 20070287202
    Abstract: A method of an embodiment of the present of the present application is for producing a nano-scale low dimensional quantum structure. The method includes: bringing a catalyst on a substrate into contact with vaporized carbon source, and emitting an electromagnetic wave to the catalyst so as to form single-walled carbon nano-tubes on the catalyst. As a result, it is possible to form the nano-scale low-dimensional quantum structure on a target area.
    Type: Application
    Filed: August 30, 2005
    Publication date: December 13, 2007
    Inventors: Kenzo Maehashi, Yasuyuki Fujiwara, Koichi Inoue, Kazuhiko Matsumoto, Yasuhide Ohno
  • Publication number: 20070259457
    Abstract: In accordance with the invention, there is a semiconductor device comprising optical enhancement medium and there are methods of end point detection in an etching process and also in a planarization process using an optical enhancement medium such as an anti-reflective coating. The method can include forming a semiconductor structure having at least one trench in a first layer, forming a layer of anti-reflective coating over the first layer, depositing a second layer of material over the anti-reflective layer, and etching the second layer and the anti-reflective layer. The method can also include monitoring an optical signal from the etching process and stopping the etching process at a predetermined time after observing the optical signal from a plasma enhanced optical excitation of the anti-reflective coating and thereby detecting an endpoint of the etching process.
    Type: Application
    Filed: May 4, 2006
    Publication date: November 8, 2007
    Inventor: Anthony DiCarlo
  • Publication number: 20070037301
    Abstract: A method for monitoring precision of placement of semiconductor wafers in a semiconductor processing apparatus includes measuring thickness of an insulating film on a surface of a semiconductor substrate before etching a portion of the insulating film from the surface of the semiconductor substrate. The method further includes re-measuring the thickness of the insulating film to determine etch rates for the film at selected locations on the surface of the semiconductor wafer, and based on the determined etch rates, determining misalignment of the semiconductor wafer.
    Type: Application
    Filed: August 15, 2005
    Publication date: February 15, 2007
    Inventor: Igor Jekauc
  • Patent number: 7169625
    Abstract: A method and apparatus for automatic determination of semiconductor plasma chamber matching a source of fault are provided. Correlated plasma attributes are measured for process used for calibration both in a chamber under study and in a reference chamber. Principal component analysis then is performed on the measured correlated attributes so as to generate steady principal components and transitional principal components; and these principal components are compared to reference principal components associated with a reference chamber. The process used for calibration includes a regular plasma process followed by a process perturbation of one process parameter. Similar process perturbation runs are conducted several times to include different perturbation parameters. By performing inner products of the principal components of chamber under study and the reference chamber, matching scores can be reached. Automatic chamber matching can be determined by comparing these scores with preset control limits.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: January 30, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Matthew F. Davis, Lei Lian
  • Patent number: 7166480
    Abstract: A particle control device and a particle control method are capable of controlling the occurrences of particles in a vacuum reactor. The particle control device is used in a vacuum processing apparatus having a vacuum reactor, a gas delivery unit for supplying processing gases to the vacuum reactor, and a sample table for supporting a sample in the vacuum reactor, wherein the apparatus subjects the sample to vacuum processing. The particle control device detects particles floating inside the vacuum reactor; generates apparatus condition data indicating a condition of the vacuum processing apparatus; and determines a component which is high in a particle occurrence probability based on detected particle data and apparatus condition data, thereby enabling display of the component selected as the particle source.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: January 23, 2007
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Daisuke Shiraishi, Akira Kagoshima, Hideyuki Yamamoto, Takeshi Arai, Hiroyuki Nakano
  • Patent number: 7115214
    Abstract: First, a substrate having at least a conducting layer is provided. Then, a CVD process is performed to form the Ti/TiN barrier layer onto the conducting layer. An examination procedure is followed, and if particles are detected in the Ti/TiN barrier layer, then a rework procedure is performed to remove the Ti/TiN barrier layer and to reform a new Ti/TiN barrier layer.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: October 3, 2006
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Ching-Hua Chen, Yi-Chung Cheng