For Structural Parameters, E.g., Thickness, Line Width, Refractive Index, Temperature, Warp, Bond Strength, Defects, Optical Inspection, Electrical Measurement Of Structural Dimensions, Metallurgic Measurement Of Diffusions (epo) Patents (Class 257/E21.53)
  • Publication number: 20130056791
    Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.
    Type: Application
    Filed: November 1, 2012
    Publication date: March 7, 2013
    Inventors: Kazuhiro SHIMIZU, Hajime Akiyama, Naoki Yasuda
  • Patent number: 8390131
    Abstract: A semiconductor device that includes an electrode of one material and a conductive material of lower resistivity formed over the electrode and a process for fabricating the semiconductor device.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: March 5, 2013
    Assignee: International Rectifier Corporation
    Inventors: Sven Fuchs, Mark Pavier
  • Publication number: 20130052756
    Abstract: A heating device is provided according to an embodiment. The heating device comprises a heater, a temperature detecting part, a wafer warpage detecting part and a controlling part. The heater heats a wafer. The temperature detecting part detects a temperature of the wafer. The wafer warpage detecting part detects warpage of the wafer. The controlling part controls the heater based on a detection result of the wafer warpage detecting part before controlling the heater based on a detection result of the temperature detecting part.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro Okujo, Masato Fukumoto
  • Publication number: 20130050686
    Abstract: A device includes one or more reflector components. Each reflector component comprises layer pairs of epitaxially grown reflective layers and layers of a non-epitaxial material, such as air. Vias extend through at least some of the layers of the reflector components. The device may include a light emitting layer.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Inventors: Thomas Wunderer, Christopher L. Chua, Brent S. Krusor, Noble M. Johnson
  • Publication number: 20130052758
    Abstract: Approaches for substantially removing bulk aluminum nitride (AlN) from one or more layers epitaxially grown on the bulk AlN are discussed. The bulk AlN is exposed to an etchant during an etching process. During the etching process, the thickness of the bulk AlN can be measured and used to control etching.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Inventors: Brent S. Krusor, Christopher L. Chua, Thomas Wunderer, Noble M. Johnson, Bowen Cheng
  • Publication number: 20130049021
    Abstract: Methods for fabricating semiconductor devices such as LED chips with emission wavelength correction and devices fabricated using these methods. Different embodiments include sequential coating methods that provide two or more coatings or layers of conversion material over LEDs, which can be done at the wafer level. The methods are particularly applicable to fabricating LED chips that emit a warm white light, which typically requires covering LEDs with one or more wavelength conversion materials such as phosphors. In one embodiment, a base wavelength conversion material is applied to the semiconductor devices. A portion of the base conversion material is removed. At least two different tuning wavelength conversion materials are also applied to the semiconductor devices, either before or after the application of the base conversion material.
    Type: Application
    Filed: August 26, 2011
    Publication date: February 28, 2013
    Inventors: JAMES IBBETSON, Bernd Keller, Ronan Letoquin, Matthew Donofrio, Michael Bergmann
  • Publication number: 20130045548
    Abstract: A method for depositing a semiconductor layer on a multiplicity of substrates. The process chamber height (H), which is defined by the spacing between a process chamber ceiling (8) and a process chamber floor (9) is variable and influences the growth rate of the layer. The layer thickness is measured continuously or at in short intervals on at least one substrate (5) in each process chamber (2) while the layer is growing. The process chamber height (H) is varied by means of a controller (12) and an adjusting member (6), so that layers having the same layer thickness are deposited in the process chambers.
    Type: Application
    Filed: April 16, 2011
    Publication date: February 21, 2013
    Inventors: Johannes K├Ąppeler, Adam Boyd
  • Publication number: 20130045547
    Abstract: In a plasma processing apparatus in which a wafer is processed while supplying radio frequency power to electrodes disposed in a sample stage in a processing chamber within a reactor via a matching box, by matching a specific value of power at transition points of data values of at least two kinds among characteristic data including light emission intensity of the plasma, magnitude of its time variation, a matching position of the matching box, and a change of a value of a voltage of the radio frequency power supplied to the electrodes detected by varying the power to a plurality of values during the processing with a value detected by using characteristic data which is detected during the processing executed on a wafer of the same kind in a different reactor, the differences of the states inside the processing chamber or plasma among a plurality of semiconductor processing apparatuses or reactors are reduced.
    Type: Application
    Filed: September 20, 2011
    Publication date: February 21, 2013
    Inventors: Masaru IZAWA, Kouichi Yamamoto, Kenji Nakata, Atsushi Itou
  • Patent number: 8373244
    Abstract: By forming thermocouples in a contact structure of a semiconductor device, respective extension lines of the thermocouples may be routed to any desired location within the die, without consuming valuable semiconductor area in the device layer. Thus, an appropriate network of measurement points of interest may be provided, while at the same time allowing the application of well-established process techniques and materials. Hence, temperature-dependent signals may be obtained from hot spots substantially without being affected by design constraints in the device layer.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: February 12, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Anthony Mowry, Casey Scott, Roman Boschke
  • Publication number: 20130034918
    Abstract: According to the invention, a monitoring device (12) is created for monitoring a thinning of at least one semiconductor wafer (4) in a wet etching unit (5), wherein the monitoring device (12) comprises a light source (14), which is designed to emit coherent light of a light wave band for which the semiconductor wafer (4) is optically transparent. The monitoring device (12) further comprises a measuring head (13), which is arranged contact-free with respect to a surface of the semiconductor wafer (4) to be etched, wherein the measuring head (13) is designed to irradiate the semiconductor wafer (4) with the coherent light of the light wave band and to receive radiation (16) reflected by the semiconductor wafer (4). Moreover, the monitoring device (12) comprises a spectrometer (17) and a beam splitter, via which the coherent light of the light wave band is directed to the measuring head (13) and the reflected radiation is directed to the spectrometer (17).
    Type: Application
    Filed: January 10, 2011
    Publication date: February 7, 2013
    Inventors: Claus Dusemund, Martin Schoenleber, Berthold Michelt, Christoph Dietz
  • Patent number: 8367431
    Abstract: In a manufacturing method of a semiconductor photonic device substrate, before multi-layer films different in material composition are successively and gradually crystal-grown in one chamber, an inter-layer growth rate model showing a relation in growth rate between each layer is defined, a growth rate of a film corresponding to at least one or more layers is obtained by actual crystal growth using an individual substrate, a growth rate of a film corresponding to other layers is estimated from the obtained growth rate by the inter-layer growth rate model, and a growth time is determined in accordance with a film thickness of each layer of the semiconductor photonic device substrate based on the actually obtained growth rate and the estimated growth rate. These steps are carried out by using a computer system connected to an MOCVD equipment, and then, a crystal growth of the semiconductor photonic device substrate is performed.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: February 5, 2013
    Assignee: Hitachi Cable, Ltd.
    Inventors: Toshihiro Morisawa, Takehiko Tani, Hisataka Nagai, Takashi Furuya
  • Publication number: 20130029434
    Abstract: A method of fabricating a semiconductor device includes performing a first period of operation and a second period of operation at first equipment and second equipment. The first period of operation includes performing a first patterning process at each of the first equipment and the second equipment, generating first inspection data of the first equipment and first inspection data of the second equipment, generating first differential data of the second equipment including differentials of the first inspection data of the first equipment and the first inspection data of the second equipment, and calibrating a configuration of the second equipment with reference to the first differential data of the second equipment.
    Type: Application
    Filed: July 23, 2012
    Publication date: January 31, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Jang-Sun KIM
  • Publication number: 20130026608
    Abstract: The invention relates to a process for manufacturing a semiconductor structure comprising a functionalized layer on a support substrate, comprising the following steps: (a) implanting ionic species in a source substrate comprising the said functionalized layer and a sacrificial buffer layer located under the functionalized layer relative to the direction of implantation, to a depth delimiting the thickness of an upper part of the source substrate comprising the functionalized layer and at least part of the buffer layer; (b) bonding the source substrate to the support substrate; (c) fracturing the source substrate and transferring the upper part of the source substrate to the support substrate; (d) removing the buffer layer by selective etching with respect to the functionalized layer.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 31, 2013
    Applicant: SOITEC
    Inventor: Ionut Radu
  • Publication number: 20130029435
    Abstract: A laser resonator and method for forming the laser resonator are provided. The method comprises placing a housing for the laser resonator in an alignment fixture, attaching a bond plate to an optical component of the laser resonator, attaching a first end of an alignment arm to the bond plate attached to the optical component, attaching a second end of the alignment arm to the alignment fixture such that the optical component is disposed over the housing, aligning, via the alignment fixture and the alignment arm, the optical component relative to the housing, and bonding the aligned optical component to the housing. The first end of the alignment arm may removed once the aligned optical component is bonded to the housing.
    Type: Application
    Filed: October 1, 2012
    Publication date: January 31, 2013
    Applicant: DRS RSTA, INC.
    Inventor: DRS RSTA, INC.
  • Patent number: 8361819
    Abstract: Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: January 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yu-Sik Kim
  • Publication number: 20130023069
    Abstract: A method for checking an ion implantation condition when ions are implanted over an entirety of one surface of a semiconductor wafer having an insulator film on the one surface, the method including checking whether the ions are implanted over the entirety of the one surface of the semiconductor wafer by directly or indirectly observing light emitted when the one surface of the semiconductor wafer is irradiated with an ion beam of the implanted ions throughout the ion implantation.
    Type: Application
    Filed: March 28, 2011
    Publication date: January 24, 2013
    Inventor: Isao Yokokawa
  • Publication number: 20130023065
    Abstract: Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed.
    Type: Application
    Filed: July 22, 2011
    Publication date: January 24, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Rhone Wang, Tzu-Cheng Lin, Yu-Jen Cheng, Chih-Wei Lai, Hung-Pin Chang, Tsang-Jiuh Wu
  • Publication number: 20130023067
    Abstract: A method is described for improving the uniformity over a predetermined substrate area of a spectral response of photonic devices fabricated in a thin device layer. The method includes (i) establishing an initial device layer thickness map for the predetermined area, (ii) establishing a linewidth map for the predetermined area, and (iii) establishing an etch depth map for the predetermined area. The method further includes, based on the initial device layer thickness map, the linewidth map and the etch depth map, calculating an optimal device layer thickness map and a corresponding thickness correction map for the predetermined substrate area taking into account photonic device design data. Still further, the method includes performing a location specific corrective etch process in accordance with the thickness correction map.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 24, 2013
    Applicant: IMEC
    Inventors: Philippe Absil, Shankar Kumar Selvaraja
  • Publication number: 20130017629
    Abstract: According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral structure, forming a stacked layer structure conformally covering the concave region, the stacked layer structure including a plurality of layers sequentially stacked and having a lowest top surface in the cell array region and a highest top surface in the peripheral circuits region, forming a planarization stop layer that conformally covers the stacked layer structure, and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the thin layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 17, 2013
    Inventors: Myungjung Pyo, Hyo-Jung Kim, JongHeun Lim, Kyunghyun Kim, Byoungmoon Yoon, JaHyung Han
  • Publication number: 20130011936
    Abstract: An etching method. The method includes etching a first plurality of silicon wafers in a first enchant, each silicon wafer having SiO2 and Si3N4 deposited thereon, where the etching includes dissolving a quantity of the SiO2 and a quantity of the Si3N4 in the first etchant. A quantity of insoluble SiO2 precipitates. A ratio of a first etch rate of Si3N4 to a first etch rate of SiO2 is determined to be less than a predetermined threshold. A portion of the first etchant is combined with a second etchant to form a conditioned etchant. A second plurality of silicon wafers is etched in the conditioned etchant. A ratio of a second etch rate of Si3N4 to a second etch rate of SiO2 in the conditioned etchant is greater than the threshold. A method for exchanging an etching bath solution and a method for forming a selective etchant are also disclosed.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: International Business Machines Corporation
    Inventors: Russell Herbert Arndt, Paul F. Findeis, Charles Jesse Taft
  • Patent number: 8350393
    Abstract: The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: January 8, 2013
    Assignee: Wintec Industries, Inc.
    Inventor: Kong-Chen Chen
  • Publication number: 20130001645
    Abstract: Provided is a semiconductor epitaxial substrate which has low semiconductor layer mosaicity and is suitable for the production of a semiconductor device. Specifically provided is a semiconductor epitaxial substrate formed by epitaxially growing a graded buffer layer which is compositionally graded such that the lattice constant increases in stages within a range from a first lattice constant to a second lattice constant larger than the first lattice constant, and a semiconductor layer produced from a semiconductor crystal having the second lattice constant on a semiconductor substrate having the first lattice constant. The angle formed by the (mnn) plane (m and n are integers except m=n=0) of the semiconductor layer and the (mnn) plane of the semiconductor substrate is set to +0.05┬░ or more when the direction that rotates clockwise from the [100] direction to the [011] direction is positive.
    Type: Application
    Filed: March 1, 2011
    Publication date: January 3, 2013
    Inventors: Koji Kakuta, Tatsuya Nozaki, Susumu Kanai
  • Publication number: 20130005056
    Abstract: Provided is a method for processing a wafer edge portion using photolithograph equipment. The method includes placing a wafer on a support plate, inspecting a bead removal state of an edge portion of the wafer placed on the support plate, and exposing the edge portion of the wafer placed on the support plate to light. The inspecting of the bead removal state is performed by capturing first images from the wafer placed on the support plate and inspecting the first images.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 3, 2013
    Applicant: SEMES CO., LTD.
    Inventors: Duk Sik Kim, Wonkwon Shin
  • Publication number: 20120329178
    Abstract: The present invention generally relates to an optical system that is able to reliably deliver a uniform amount of energy across an anneal region contained on a surface of a substrate. The optical system is adapted to deliver, or project, a uniform amount of energy having a desired two-dimensional shape on a desired region on the surface of the substrate. An energy source for the optical system is typically a plurality of lasers, which are combined to form the energy field.
    Type: Application
    Filed: July 29, 2011
    Publication date: December 27, 2012
    Inventors: Stephen Moffatt, Douglas E. Holmgren, Samuel C. Howells, Edric Tong, Bruce E. Adams, Jiping Li, Aaron Muir Hunter
  • Patent number: 8338918
    Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
  • Publication number: 20120322169
    Abstract: A focus through a projection lens is corrected to prevent the occurrence of a dimensional error in a pattern due to defocusing. At least one automatic focus correction mark is formed over each of chip patterns formed in a reticle used for exposure. Using one of the automatic focus correction marks located in the center portion of an actual device region, automatic correction of the focus of exposure light is performed. In this manner, a variation in the focus of the exposure light through the center portion of the projection lens, which is more likely to reach a high temperature than an end portion of the projection lens, is detected and corrected.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 20, 2012
    Inventors: Naoyuki TERAMOTO, Megumu FUKAZAWA, Masayuki KUMASHIRO, Kiyoshi KAWAGASHIRA
  • Publication number: 20120315712
    Abstract: A method for detecting embedded voids present in a structure formed in or on a semiconductor substrate is described. The method includes performing a processing step P1 for forming the structure; measuring the mass M1 of the substrate; performing thermal treatment; measuring the mass M2 of the substrate; calculating the mass difference between the mass of the substrate measured before and after the performed thermal treatment; and deducing the presence of embedded voids in the structure by comparing the mass difference with a pre-determined value.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 13, 2012
    Applicant: IMEC
    Inventors: Leonardus Leunissen, Sandip Halder, Eric Beyne
  • Publication number: 20120313169
    Abstract: FIN-FET ICs with adjustable FIN-FET channel widths are formed from a semiconductor layer (42). Fins (36) may be etched from the layer (42) and then some (46) locally shortened or the layer (42) may be locally thinned and then fins (46) of different fin heights etched therefrom. Either way provides fins (46) and FIN-FETs (40) with different channel widths W on the same substrate (24). Fin heights (H) are preferably shortened by implanting selected ions (A, B, C, etc.) through a mask (90, 90?, 94, 94?, 97, 97?) to locally enhance the etch rate of the layer (42) or some of the fins (36). The implant(s) (A, B, C, etc.) is desirably annealed and then differentially etched. This thins part(s) (42-i) of the layer (42) from which the fins (46) are then etched or shortens some of the fins (46) already etched from the layer (42). For silicon, germanium is a suitable implant ion.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 13, 2012
    Inventors: Jeremy Wahl, Kingsuk Maitra
  • Publication number: 20120309117
    Abstract: A method for manufacturing a semiconductor device wherein a semiconductor element is sealed with mold resin, a MOS structure is on an upper side of the semiconductor chip, and a PN junction region is on a back side of the semiconductor chip, comprises: obtaining an in-plane distribution of impurity concentration of the PN junction region in the semiconductor chip before encapsulation so that an in-plane distribution of breakdown voltage and leakage current of the semiconductor chip become uniform after encapsulation; forming the PN junction region having the obtained in-plane distribution of impurity concentration on the back side of the semiconductor chip; and sealing the semiconductor chip with the resin after forming the PN junction region.
    Type: Application
    Filed: January 26, 2012
    Publication date: December 6, 2012
    Inventors: Yuichiro SUZUKI, Atsushi Narazaki, Yoshiaki Terasaki
  • Publication number: 20120306030
    Abstract: A method of balancing a microelectromechanical system comprises determining if a microelectromechanical system is balanced in a plurality of orthogonal dimensions, and if the microelectromechanical system is not balanced, selectively depositing a first volume of jettable material on a portion of the microelectromechanical system to balance the microelectromechanical system in the plurality of orthogonal dimensions. A jettable material for balancing a microelectromechanical system comprises a vehicle, and a dispersion of nano-particles within the vehicle, in which the total mass of jettable material deposited on the microelectromechanical system is equal to the weight percentage of nano-particles dispersed within the vehicle multiplied by the mass of jettable material deposited on the microelectromechanical system.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 6, 2012
    Inventors: Pavel Kornilovich, Vladek Kasperchik, James William Stasiak
  • Patent number: 8304261
    Abstract: A thermal treatment apparatus having a first light source emitting a first light having light diffusion property, a reflectance measuring unit irradiating a treatment target with the light from plural directions by the first light source and determining a light reflectance of the treatment target, a light irradiation controller adjusting an intensity of a second light of a second light source on the basis of the light reflectance, the second light has diffusion property, and a thermal treatment unit irradiating the treatment target with the second light having adjusted the intensity of the second light by the light irradiation controller.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: November 6, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tomohiro Kubo
  • Publication number: 20120276663
    Abstract: According to an embodiment, equipment for manufacturing a semiconductor device includes a first block, a plurality of stamp pins, a second block and a plurality of springs. The first block includes a plurality of first through-holes penetrating from a first major surface to a second major surface. The stamp pins are inserted into each of the first through-holes from the first major surface, each of the stamp pins having an end projected from the second major surface and being capable of moving forward and backward in the insertion direction. The second block has a plurality of second through-holes with an inner diameter larger than an inner diameter of the first through-holes, the second through-holes being disposed so as to overlap with the first through-holes; and the springs are disposed in each of the second through-holes, for biasing the stamp pins in the insertion direction.
    Type: Application
    Filed: January 26, 2012
    Publication date: November 1, 2012
    Inventors: Tsutomu MIYAHARA, Masahiro OGUSHI
  • Patent number: 8298838
    Abstract: A method for staining a sample includes the following steps. A test device is provided. The test device is sampled to obtain a sample. The sample includes a substrate, an active area disposed within the substrate and having a first doped substrate region and a second doped substrate region, at least one gate disposed between the first doped substrate region and the second doped substrate region, and an exposed shallow trench isolation embedded in the substrate and surrounding the active area. A first staining procedure is then carried out to selectively remove the shallow trench isolation to form a first void and to entirely expose the active area. A second staining procedure is subsequently carried out to selectively stain the first doped substrate region and the second doped substrate region to form a second void.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: October 30, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Po-Fu Chou, Yu-Wen Liu
  • Publication number: 20120268722
    Abstract: In one an embodiment, there is provided an assembly comprising at least one detector. Each of the at least one detector includes a substrate having a doped region of a first conduction type, a layer of dopant material of a second conduction type located on the substrate, a diffusion layer formed within the substrate and in contact with the layer of dopant material and the doped region of the substrate, wherein a doping profile, which is representative of a doping material concentration of the diffusion layer, increases from the doped region of the substrate to the layer of dopant material, a first electrode connected to the layer of dopant material, and a second electrode connected to the substrate. The diffusion layer is arranged to form a radiation sensitive surface.
    Type: Application
    Filed: February 17, 2012
    Publication date: October 25, 2012
    Applicant: ASML Netherlands B.V.
    Inventors: Stoyan NIHTIANOV, Arie Johan Van Der Sijs, Bearrach Moest, Petrus Wilhelmus Josephus Maria Kemper, Marc Antonius Maria Haast, Gerardus Wilhelmus Petrus Baas, Lis Karen Nanver, Francesco Sarubbi, Antonius Andreas Johannes Schuwer, Gregory Micha Gommeren, Martijn Pot, Thomas Ludovicus Maria Sholtes
  • Publication number: 20120267802
    Abstract: The invention relates to a substrate for use in a lithography system, said substrate being provided with an at least partially reflective position mark comprising an array of structures, the array extending along a longitudinal direction of the mark, characterized in that said structures are arranged for varying a reflection coefficient of the mark along the longitudinal direction, wherein said reflection coefficient is determined for a predetermined wavelength. In an embodiment a specular reflection coefficient varies along the substrate, wherein high order diffractions are substantially absorbed by the substrate. A position of a beam on a substrate can thus be determined based on the intensity of its reflection in the substrate. The invention further relates to a positioning device and lithography system for cooperation with the substrate, and a method of manufacture of the substrate.
    Type: Application
    Filed: April 23, 2012
    Publication date: October 25, 2012
    Inventors: Guido De Boer, Niels Vergeer
  • Publication number: 20120270343
    Abstract: A polishing method and a method for forming a gate are provided. The method includes forming a dummy gate on a semiconductor substrate including a sacrificial oxide layer and a polysilicon layer which covers the sacrificial oxide layer, forming spacers around the dummy gate, and successively forming a silicon nitride layer and a dielectric layer covering the silicon nitride layer. The method further includes polishing the dielectric layer until the silicon nitride layer is exposed, polishing the silicon nitride layer on a fixed abrasive pad until the polysilicon layer is exposed by using a polishing slurry with a PH value ranging from 10.5 to 11 and comprising an anionic surfactant or a zwitterionic surfactant. Additionally, the method includes forming an opening after removing the dummy gate, and forming a gate in the opening. The method eliminates potential erosion and dishing caused in the polishing of the silicon nitride layer.
    Type: Application
    Filed: September 23, 2011
    Publication date: October 25, 2012
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: LI JIANG, MINGQI LI
  • Publication number: 20120270342
    Abstract: Methods and systems are provided for fabricating a semiconductor device. An exemplary method involves forming a feature of a semiconductor device in a first region of a layer of material on a semiconductor substrate and forming a test structure in a second region of the layer of material. The test structure is formed concurrently to forming the feature, and a dimension of the feature is determined using the test structure.
    Type: Application
    Filed: April 22, 2011
    Publication date: October 25, 2012
    Inventor: Dmytro CHUMAKOV
  • Patent number: 8293544
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: October 23, 2012
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Debora Chyiu Hyia Poon, Alex Kh See, Francis Benistant, Benjamin Colombeau, Yun Ling Tan, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 8293629
    Abstract: Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: October 23, 2012
    Assignee: OmniVision Technologies, Inc.
    Inventors: Duli Mao, Hsin-Chih Tai, Vincent Venezia, Yin Qian, Howard E. Rhodes
  • Publication number: 20120261563
    Abstract: A method of forming a standard mask for an inspection system is provided, the method comprising providing a substrate within a chamber, and providing a tetraethylorthosilicate (TEOS) precursor within the chamber. The method further includes reacting the TEOS precursor with an electron beam to form silicon oxide particles of controlled size at one or more controlled locations on the substrate, the silicon oxide particles disposed as simulated contamination defects.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 18, 2012
    Inventors: Chien-Hung Lai, Biow-Hiem Ong, Chia-Shih Lin, Jong-Yuh Chang, Chih-Chiang Tu
  • Publication number: 20120264237
    Abstract: A method for designing, fabricating, and predicting a desired structure in and/or on a host material through defining etch masks and etching the host material is provided. The desired structure can be micro- or nanoscale structures, such as suspended nanowires and corresponding supporting pillars, and can be defined one layer at a time. Arbitrary desired structures can also be defined and obtained through etching. Further, given the desired structure, a starting structure can be predicted where etching of the starting structure yields the desired structure.
    Type: Application
    Filed: June 13, 2011
    Publication date: October 18, 2012
    Inventors: Michael SHEARN, Michael David HENRY, Axel SCHERER
  • Patent number: 8288176
    Abstract: The disclosure relates to a method of aligning a set of patterns on a substrate, which includes depositing on the substrate's surface a set of silicon nanoparticles, which includes a set of ligand molecules including a set of carbon atoms. The method involves forming a first set of regions where the nanoparticles are deposited, while the remaining portions of the substrate surface define a second set of regions. The method also includes densifying the set of nanoparticles into a thin film to form a set of silicon-organic zones on the substrate's surface, wherein the first and the second set of regions have respectively first and second reflectivity values, such that the ratio of the second reflectivity value to the first reflectivity value is greater than about 1.1.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: October 16, 2012
    Assignee: Innovalight, Inc.
    Inventors: Andreas Meisel, Michael Burrows, Homer Antoniadis
  • Patent number: 8288174
    Abstract: An Electrostatic Post Exposure Bake (EPEB) subsystem comprising an Electrostatic Bake Plate (EBP) configured in a processing chamber in an EPEB subsystem, wherein the EPEB wafer comprises an exposed masking layer having unexposed regions and exposed regions therein and the EPEB wafer is developed using the EBP.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: October 16, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Benjamen M. Rathsack, Brian Head, Steven Scheer
  • Patent number: 8288178
    Abstract: A lead frame is provided that includes a base metal, a plated layer provided on a part of the surface of the base metal, and a thermal history monitor portion that discolors under heat load applied thereto, provided at another part of the base metal surface. A method of manufacturing a semiconductor device includes an assembly process including mounting a semiconductor chip on the lead frame, performing a wire bonding process thereby connecting the semiconductor chip and the lead frame, and encapsulating with a resin the wire-bonded semiconductor chip and the lead frame, and then performing an appearance check after the assembly process to inspect whether the thermal history monitor portion has discolored under heat load applied through the assembly process, thereby deciding whether an abnormality has emerged through the thermal history.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: October 16, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshinari Fukumoto
  • Publication number: 20120256166
    Abstract: The invention relates to a process for deposition of elongated nanoparticles from a liquid carrier onto a substrate, and to electronic devices prepared by this process.
    Type: Application
    Filed: November 16, 2010
    Publication date: October 11, 2012
    Inventors: Lichun Chen, Michael Coelle, Mark John Goulding
  • Publication number: 20120248506
    Abstract: The present invention relates to integrating an inertial mechanical device on top of a CMOS substrate monolithically using IC-foundry compatible processes. The CMOS substrate is completed first using standard IC processes. A thick silicon layer is added on top of the CMOS. A subsequent patterning step defines a mechanical structure for inertial sensing. Finally, the mechanical device is encapsulated by a thick insulating layer at the wafer level. Comparing to the incumbent bulk or surface micromachined MEMS inertial sensors, the vertically monolithically integrated inertial sensors have smaller chip size, lower parasitics, higher sensitivity, lower power, and lower cost.
    Type: Application
    Filed: June 12, 2012
    Publication date: October 4, 2012
    Applicant: MCUBE, INC.
    Inventor: XIAO (CHARLES) YANG
  • Publication number: 20120248580
    Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first main surface side of the first semiconductor substrate and a first main surface side of the second semiconductor substrate being bonded to each other; and a warpage correction layer which is formed on at least one or more selected from the first main surface side of the first semiconductor substrate, the first main surface side of the second semiconductor substrate, a second main surface side of the first semiconductor substrate, and a second main surface side of the second semiconductor substrate.
    Type: Application
    Filed: March 2, 2012
    Publication date: October 4, 2012
    Inventors: Hiroyasu Matsugai, Kiyotaka Tabuchi
  • Publication number: 20120244647
    Abstract: The present invention provides a die bonder capable of stripping a die without fail, or a highly reliable die bonder or pick-up method using the die bonder. When a die to be stripped out of plural dies (semiconductor chips) bonded to a dicing film is to be tossed and stripped from the dicing film, the dicing film corresponding to predetermined positions out of the peripheral portion of the die is tossed to form stripping start points and then, the dicing film corresponding to portions other than the above predetermined positions is tossed to strip the die from the dicing film.
    Type: Application
    Filed: September 2, 2011
    Publication date: September 27, 2012
    Applicant: Hitachi High-Tech Instruments Co., Ltd.
    Inventors: Naoki OKAMOTO, Keita Yamamoto
  • Publication number: 20120244646
    Abstract: According to embodiments, there is provided a manufacturing method of a semiconductor device includes forming a semiconductor thin film on a substrate; processing the thin film to a predetermined shape; executing an ion implantation process on the thin film processed to the predetermined shape; executing an anneal treatment on the thin film on which the ion implantation process has been executed to create a resistor element; and adjusting both or any one of a process condition of the ion implantation process and a treatment condition of the anneal treatment based on at least any one of a film forming condition and a film formation result of the forming and a film process result of the processing.
    Type: Application
    Filed: January 18, 2012
    Publication date: September 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Takashi KYUHO
  • Publication number: 20120241955
    Abstract: Methods, systems, and apparatuses are described for the assembly of integrated circuit (IC) packages. A substrate panel is formed that includes a plurality of substrates. The substrate panel is singulated to separate the plurality of substrates. At least a subset of the separated substrates is attached to a surface of a carrier. One or more dies are attached to each of the substrates on the carrier. The dies and the substrates are encapsulated on the carrier with a molding compound. The carrier is detached from the encapsulated dies and substrates to form a molded assembly that includes the molding compound encapsulating the dies and substrates. A plurality of interconnects is attached to each of the substrates at a surface of the molded assembly. The molded assembly is singulated to form a plurality of IC packages. Each IC package includes at least one of the dies and a substrate.
    Type: Application
    Filed: March 25, 2011
    Publication date: September 27, 2012
    Applicant: Broadcom Corporation
    Inventors: Edward Law, Rezaur R. Khan, Edmund Law