For Structural Parameters, E.g., Thickness, Line Width, Refractive Index, Temperature, Warp, Bond Strength, Defects, Optical Inspection, Electrical Measurement Of Structural Dimensions, Metallurgic Measurement Of Diffusions (epo) Patents (Class 257/E21.53)
  • Patent number: 8912079
    Abstract: Provided is a compound semiconductor deposition method of adjusting the luminous wavelength of a compound semiconductor of a ternary or higher system in a nanometer order in depositing the compound semiconductor on a substrate.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: December 16, 2014
    Assignees: The University of Tokyo, V Technology Co., Ltd.
    Inventors: Motoichi Ohtsu, Takashi Yatsui, Tadashi Kawazoe, Shunsuke Yamazaki, Koichi Kajiyama, Michinobu Mizumura, Keiichi Ito
  • Patent number: 8908161
    Abstract: Approaches for substantially removing bulk aluminum nitride (AlN) from one or more layers epitaxially grown on the bulk AlN are discussed. The bulk AlN is exposed to an etchant during an etching process. During the etching process, the thickness of the bulk AlN can be measured and used to control etching.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: December 9, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Brent S. Krusor, Christopher L. Chua, Thomas Wunderer, Noble M. Johnson, Bowen Cheng
  • Patent number: 8895325
    Abstract: A system and method are disclosed for aligning substrates during successive process steps, such as ion implantation steps, is disclosed. Implanted regions are created on a substrate. After implantation, an image is obtained of the implanted regions, and a fiducial is provided on the substrate in known relation to at least one of the implanted regions. A thermal anneal process is performed on the substrate such that the implanted regions are no longer visible but the fiducial remains visible. The position of the fiducial may be used in downstream process steps to properly align pattern masks over the implanted regions. The fiducial also may be applied to the substrate before any ion implanting of the substrate is performed. The position of the fiducial with respect to an edge or a corner of the substrate may be used for aligning during downstream process steps. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: November 25, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: John W. Graff, Benjamin B. Riordon, Nicholas P. T. Bateman
  • Patent number: 8877642
    Abstract: Fabricating of one or more semiconductor devices with critical gate dimension control is facilitated by: providing a multilayer stack structure over a substrate; etching through the multilayer stack structure, with critical gate dimension control, to define multiple gate lines; providing a protective layer over the multiple gate lines; and patterning and cutting one or more gate lines of the multiple gate lines to facilitate defining multiple gate structures of the one or more semiconductor devices. Etching through the multilayer stack structure is facilitated by lithographically patterning the multilayer stack structure, and critical dimension feedback control is provided to at least one of the lithographically patterning or the etching through the multilayer stack structure.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: November 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Xiang Hu
  • Patent number: 8877525
    Abstract: Mechanisms are provided for chip (e.g., semiconductor chip) identification (e.g., low cost secure identification). In one example, a method of manufacturing for implementing integrated chip identification is provided. In another example, a method of using a chip with an integrated identification is provided.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Dirk Pfeiffer
  • Patent number: 8853087
    Abstract: A target space ratio of a monitor pattern on a substrate for inspection is determined to be different from a ratio of 1:1. A range of space ratios in a library is determined to include the target space ratio and not include a space ratio of 1:1. The monitor pattern is formed on a film to be processed by performing predetermined processes on the substrate for inspection. Sizes of the monitor pattern are measured. The sizes of the monitor pattern are converted into sizes of a pattern of the film to be processed having a space ratio of 1:1, and processing conditions of the predetermined processes are compensated for based on the sizes of the converted pattern of the film to be processed. After that, the predetermined processes are performed on a wafer under the compensated conditions to form a pattern having a space ratio of 1:1 on the film to be processed.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: October 7, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Keisuke Tanaka, Machi Moriya
  • Patent number: 8815723
    Abstract: A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method also includes performing an ion implantation process to the back surface of the silicon substrate and performing a green laser annealing process to the implanted back surface of the silicon substrate. The green laser annealing process uses an annealing temperature greater than or equal to about 1100° C. for a duration of about 100 to about 400 nsec. After performing the green laser annealing process, a silicon polishing process is performed on the back surface of the silicon substrate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shou Shu Lu, Hsun-Ying Huang, I-Chang Lin, Chia-Chi Hsiao, Yung-Cheng Chang
  • Patent number: 8796684
    Abstract: A method is described for obtaining information for use in modeling of a lithographic process. A pattern feature is formed on a target portion of a substrate by projecting a beam of radiation onto the target portion of the substrate. For that target portion the lithographic process is characterized by one or both of a first property that varies in a first direction along a surface of the substrate, and a second property that varies in a second direction along a surface of the substrate. A property of the pattern feature is measured. Using the measured property of the pattern feature and at least one of the first and second properties, information is obtained for use in modeling the process. The lithographic process may be or include the projection of the beam of radiation onto the surface of the substrate.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: August 5, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Nicole Schoumans, Everhardus Cornelis Mos, Birgitt Noëlle Cornelia Liduine Hepp, Remco Jochem Sebastiaan Groenendijk
  • Patent number: 8790541
    Abstract: The present invention herein provides a method for preparing a dispersion of fluorinated nanodiamond particles, which can be used in, for instance, an abrasive, a lubricant, and a heat-exchanging fluid medium, which is stable over a long period of time on the order of not less than 120 hours and which has a viscosity, as determined at 20° C., of not less than 3 cP. This dispersion can be prepared by blending fluorinated nanodiamond particles with a first liquid having a viscosity, as determined at 20° C., of not higher than 2.5 cP to thus form a suspension, classifying the suspension to give a classified suspension, and then blending the classified suspension with a second liquid having a viscosity value, as determined at 20° C., of not less than 4 cP.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: July 29, 2014
    Assignee: Central Glass Co., Ltd.
    Inventor: Akifumi Yao
  • Patent number: 8765495
    Abstract: A method of forming a pattern of doped region includes the following steps. At first, a device layout pattern including a gate layout pattern and a doped region layout pattern is provided to a computer system. Subsequently, the device layout pattern is split into a plurality of sub regions, and the sub regions have different pattern densities of the gate layout pattern. Then, at least an optical proximity correction (OPC) calculation is respectively performed on the doped region layout pattern in each of the sub regions to respectively form a corrected sub doped region layout pattern in each of the sub regions. Afterwards, the corrected sub doped region layout patterns are combined to form a corrected doped region layout pattern, and the corrected doped region layout pattern is outputted onto a mask through the computer system.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: July 1, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Hsiu Lee, Guo-Xin Hu, Qiao-Yuan Liu, Yen-Sheng Wang
  • Patent number: 8765494
    Abstract: An organic EL device (OELD) having a defective portion is irradiated with a laser beam; first luminance of light emitted from the OELD is measured after the OELD is irradiated with the laser beam, while supplying, to the OELD, a first amount of current with which the OELD in a normal state would emit light having luminance corresponding to a first grayscale level smaller than a reference level; the OELD is re-irradiated with the laser beam when the first luminance is smaller than a threshold; and second luminance of light emitted from the OELD is measured when the first luminance is greater than or equal to the threshold, while supplying, to the OELD, a second amount of current with which the OELD in the normal state would emit light having luminance corresponding to a second grayscale level greater than or equal to the reference level.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: July 1, 2014
    Assignee: Panasonic Corporation
    Inventors: Tomomi Hiraoka, Yasuo Segawa
  • Patent number: 8759119
    Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: June 24, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shigeyuki Maruyama, Yasuyuki Itoh, Tetsurou Honda, Kazuhiro Tashiro, Makoto Haseyama, Kenichi Nagashige, Yoshiyuki Yoneda, Hirohisa Matsuki
  • Patent number: 8748199
    Abstract: Methods and systems are provided for fabricating a semiconductor device. An exemplary method involves forming a feature of a semiconductor device in a first region of a layer of material on a semiconductor substrate and forming a test structure in a second region of the layer of material. The test structure is formed concurrently to forming the feature, and a dimension of the feature is determined using the test structure.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: June 10, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventor: Dmytro Chumakov
  • Patent number: 8735182
    Abstract: A method for detecting embedded voids present in a structure formed in or on a semiconductor substrate is described. The method includes performing a processing step P1 for forming the structure; measuring the mass M1 of the substrate; performing thermal treatment; measuring the mass M2 of the substrate; calculating the mass difference between the mass of the substrate measured before and after the performed thermal treatment; and deducing the presence of embedded voids in the structure by comparing the mass difference with a pre-determined value.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: May 27, 2014
    Assignee: IMEC
    Inventors: Leonardus Leunissen, Sandip Halder, Eric Beyne
  • Patent number: 8734536
    Abstract: A temperature-adjusted spectrometer can include a light source and a temperature sensor.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: May 27, 2014
    Assignee: First Solar, Inc
    Inventors: Markus E. Beck, Ming Lun Yu
  • Patent number: 8728832
    Abstract: Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a second dielectric material on the continuous monolayer of the first dielectric material without exposing the substrate to an air break.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: May 20, 2014
    Assignee: ASM IP Holdings B.V.
    Inventors: Petri Raisanen, Michael Givens, Mohith Verghese
  • Patent number: 8716039
    Abstract: According to the invention, a monitoring device (12) is created for monitoring a thinning of at least one semiconductor wafer (4) in a wet etching unit (5), wherein the monitoring device (12) comprises a light source (14), which is designed to emit coherent light of a light wave band for which the semiconductor wafer (4) is optically transparent. The monitoring device (12) further comprises a measuring head (13), which is arranged contact-free with respect to a surface of the semiconductor wafer (4) to be etched, wherein the measuring head (13) is designed to irradiate the semiconductor wafer (4) with the coherent light of the light wave band and to receive radiation (16) reflected by the semiconductor wafer (4). Moreover, the monitoring device (12) comprises a spectrometer (17) and a beam splitter, via which the coherent light of the light wave band is directed to the measuring head (13) and the reflected radiation is directed to the spectrometer (17).
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: May 6, 2014
    Assignee: Precitec Optronik GmbH
    Inventors: Claus Dusemund, Martin Schoenleber, Berthold Michelt, Christoph Dietz
  • Patent number: 8716038
    Abstract: Several embodiments of semiconductor systems and associated methods of color corrections are disclosed herein. In one embodiment, a method for producing a light emitting diode (LED) includes forming an (LED) on a substrate, measuring a base emission characteristic of the formed LED, and selecting a phosphor based on the measured base emission characteristic of the formed LED such that a combined emission from the LED and the phosphor at least approximates white light. The method further includes introducing the selected phosphor onto the LED via, for example, inkjet printing.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: May 6, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kevin Tetz, Charles M. Watkins
  • Publication number: 20140117521
    Abstract: A lead frame for assembling a semiconductor device has a die pad surrounded by lead fingers. Each of the lead fingers has a proximal end close to but spaced from an edge of the die pad and a distal end farther from the die pad. A semiconductor die is attached to a surface of the die pad. The die has die bonding pads on its upper surface that are electrically connected to the proximal ends of the lead fingers with bond wires. An encapsulation material covers the bond wires, semiconductor die and the proximal ends of the lead fingers. Prior to assembly, hot spots of the die are determined and the lead fingers closest to the hot spots are selected to project closer to the die than the other lead fingers. These longer lead fingers assist in dissipating the heat at the die hot spot.
    Type: Application
    Filed: October 29, 2012
    Publication date: May 1, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chetan Verma, Piyush Kumar Mishra, Cheong Chiang Ng
  • Patent number: 8710489
    Abstract: To provide an epitaxial substrate for electronic devices, in which current flows in a lateral direction, which enables accurate measurement of the sheet resistance of HEMTs without contact, and to provide a method of efficiently producing the epitaxial substrate for electronic devices, the method characteristically includes the steps of forming a barrier layer against impurity diffusion on one surface of a high-resistance Si-single crystal substrate, forming a buffer as an insulating layer on the other surface of the high-resistance Si-single crystal substrate, producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate, and measuring resistance of the main laminate of the epitaxial substrate without contact.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: April 29, 2014
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tetsuya Ikuta, Daisuke Hino, Ryo Sakamoto, Tomohiko Shibata
  • Patent number: 8698227
    Abstract: A mesa-type bidirectional Shockley diode delimited on its two surfaces by a peripheral groove filled with a glassivation including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; a region of the first conductivity type in each of the layers of the second conductivity type; a buried region of the first conductivity type under each of the regions of the first conductivity type, at the interface between the substrate and the corresponding layer of the second conductivity type, each buried region being complementary in projection with the other; and a peripheral ring under the external periphery of each of the glassivations, of same doping profile as the buried regions.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: April 15, 2014
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Yannick Hague, Samuel Menard
  • Patent number: 8679864
    Abstract: A method for determining one or more characteristics of a partially processed integrated circuit includes a step for providing a substrate material. The method further includes a step for forming at least one opening within the substrate material. The opening can be characterized by an opening characteristic that includes a depth and a width associated with an unknown volume. The method includes a step for providing a fill material and processing the fill material to cause a first portion of the fill material to enter the opening and occupy an entirety of the unknown volume associated with the opening characteristic while a second portion of the fill material remains outside of the unknown volume. Moreover, the method includes a step for processing the second portion of the fill material using one or more processes to determine a spatial characteristic associated with the unknown volume.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: March 25, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Li Xu
  • Publication number: 20140080233
    Abstract: The embodiments describe methods and apparatuses for combinatorial optimization of interlayer parameters for capacitor stacks. The capacitor stacks may include a substrate, an insulating layer disposed on the substrate, a ruthenium disposed electrode on the insulating layer, and an interlayer disposed on the ruthenium electrode, where the interlayer is configured to prevent etching of the electrode when growing a high-k dielectric using an ozone-based precursor. The parameters for forming the interlayer may include interlayer thickness, precursor chemistry, oxidant strength, precursor purge times, oxidant purge times, and other suitable parameters. Each of these parameters may be evaluated through deposition of the capacitor stacks through a combinatorial optimization process. Thus, a plurality of different parameters may be evaluated with a single substrate to ascertain associated properties of Ruthenium electrode etching in a combinatorial manner.
    Type: Application
    Filed: September 19, 2012
    Publication date: March 20, 2014
    Applicant: Intermolecular, Inc.
    Inventor: Venkat Ananthan
  • Publication number: 20140080229
    Abstract: A semiconductor processing device and a method of operating the same. The method may include measuring at least one property of a semiconductor wafer and determining a recipe for processing the semiconductor wafer based on the at least one property. The semiconductor wafer may be processed with a plurality of chemical mechanical polishing (CMP) modules based on the determined recipe, wherein the recipe comprises a value of at least one parameter for use by each of the plurality of CMP modules. The measurements may be made in situ or by an inline metrology device. The recipe and various parameters associated with the recipe may be determined by a controller of the semiconductor processing device.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: STMicroelectronics, Inc.
    Inventor: John H. Zhang
  • Patent number: 8673793
    Abstract: A method for calculating an offset value for aligned deposition of a second pattern onto a first pattern, comprising steps of: (a) loading a substrate with the first pattern on a surface of the substrate into a pattern recognition device at an original position inside the pattern recognition device; (b) determining a coordinate of a prescribed point of the first pattern by the pattern recognition device; (c) superimposing the second pattern onto the first pattern on the surface of the substrate; (d) bringing back the substrate with the first pattern and the second pattern into the original position inside the pattern recognition device; (e) determining a coordinate of a prescribed point of the second pattern by the pattern recognition device; wherein the prescribed point of the first pattern corresponds to the prescribed point of the second pattern; and (f) calculating the offset value between the first pattern and the second pattern.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: March 18, 2014
    Inventor: Andreas Meisel
  • Patent number: 8673656
    Abstract: Provided is a method and a device for measuring a temperature which can recognize the temperature of a semiconductor layer directly with high precision when the semiconductor layer is formed by deposition. The quantity of laser light transmitted to a semiconductor layer is monitored by a photodetector by using laser light having a wavelength ?s at which the transmittance of light changes abruptly when the temperature of the semiconductor layer reaches Ts during or after deposition. When heat being given to the semiconductor layer is changed, the quantity of laser light monitored by the photodetector changes abruptly when the temperature of the semiconductor layer reaches Ts at a time A, B or C. Consequently, the fact that the temperature of the semiconductor layer reached Ts at a time A, B or C can be recognized exactly, and an error in temperature information observed by a device for measuring temperature variations can be calibrated, for example.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: March 18, 2014
    Assignee: YSystems, Ltd.
    Inventor: Lacroix Yves
  • Patent number: 8673709
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
  • Patent number: 8674355
    Abstract: A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Chi Tseng, Heng-Hsin Liu, Shu-Cheng Kuo, Chien-Chang Lee, Chun-Hung Lin
  • Publication number: 20140065734
    Abstract: The formation of overlap areas in sophisticated semiconductor devices is a critical aspect which may not be efficiently evaluated on the basis of conventional measurement and design strategies. For this reason, the present disclosure provides measurement techniques and systems in which overlying device patterns are transformed into the same material layer, thereby forming a combined pattern which is accessible by well-established defect inspection techniques. Upon geometrically modulating some of these combined patterns, a systematic evaluation of overlap process windows may be accomplished.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: Lothar Bauch
  • Patent number: 8647892
    Abstract: A method for process control is disclosed. The method includes performing an etching process on a semiconductor substrate forming a structure and a test structure having a pattern and a releasing mechanism coupled to the pattern; and monitoring the pattern of the test structure to determine whether the etching process is complete.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chih Liang, Wen-Chuan Tai, Chun-Ren Cheng
  • Publication number: 20140027902
    Abstract: Generally, the subject matter disclosed herein relates to repairing anomalous stiff pillar bumps that may be detected above a metallization system of a semiconductor chip or wafer. One illustrative method disclosed herein includes, among other things, forming a pillar bump above a metallization system of a semiconductor chip, and forming a plurality of notches in the pillar bump, wherein the plurality of notches are adapted to adjust a flexibility of the pillar bump when the pillar bump is exposed to a lateral force.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
  • Publication number: 20140030827
    Abstract: Methods and systems to method to determine an adhesion force of an underfill material to a chip assembled in a flip-chip module are provided. A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate. The method also includes forming a block from the layer of underfill material. The method further includes measuring a force required to shear the block from a surface of the flip-chip module.
    Type: Application
    Filed: July 30, 2012
    Publication date: January 30, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maxime CADOTTE, Marie-Claude PAQUET, Julien SYLVESTRE
  • Patent number: 8623673
    Abstract: A test structure and method for monitoring process uniformity. Embodiments of the invention include test structures having a first metallization layer, a second metallization layer formed above the first metallization layer, a defect-generating region in a first metallization layer, a defect-dispersing region in the second metallization layer above the defect-generating region; and a defect-detecting region in the second metallization layer adjacent to the defect-dispersing region. The defect-generating region of the exemplary embodiment may have zero pattern density, uniform non-zero pattern density, or non-uniform non-zero pattern density. The defect-detecting region may include a test pattern such as, a comb-serpentine structure. Embodiments may include more than one defect-generating region, more than one defect-dispersing region, or more than one defect-detecting region.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Tze-Man Ko, Yiheng Xu, Shaoning Yao
  • Patent number: 8624266
    Abstract: A main surface of a silicon carbide substrate is inclined by an off angle in an off direction from {0001} plane of a hexagonal crystal. The main surface has such a characteristic that, among emitting regions emitting photoluminescent light having a wavelength exceeding 650 nm of the main surface caused by excitation light having higher energy than band-gap of the hexagonal silicon carbide, the number of those having a dimension of at most 15 ?m in a direction perpendicular to the off direction and a dimension in a direction parallel to the off direction not larger than a value obtained by dividing penetration length of the excitation light in the hexagonal silicon carbide by a tangent of the off angle is at most 1×104 per 1 cm2. Accordingly, reverse leakage current can be reduced.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: January 7, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Tsubasa Honke
  • Publication number: 20130341620
    Abstract: In accordance with an embodiment of the present invention, a method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Albert Birner, Tobias Herzig
  • Patent number: 8610284
    Abstract: A semiconductor device includes: a semiconductor substrate, first and second internal electrodes provided on a surface of the semiconductor substrate; a first through electrode which penetrates through the semiconductor substrate in a thickness direction and is electrically connected to the first internal electrode; and a second through electrode connected to the second internal electrode, and the second internal electrode is thinner than the first internal electrode. The second through electrode may penetrate through the second internal electrode.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: December 17, 2013
    Assignee: Panasonic Corporation
    Inventor: Takahiro Nakano
  • Publication number: 20130330847
    Abstract: The present disclosure provides a method and system for characterizing a pattern loading effect. A method may include performing a reflectivity measurement on a semiconductor wafer and determining an anneal process technique based on the reflectivity measurement. The determining the anneal process technique may include determining a spatial distance for a reflectivity change using a reflectivity map generated using the reflectivity measurement. This spatial distance is compared with the thermal diffusion length associated with each of the plurality of anneal process techniques. In an embodiment, a thermal profile map and/or a device performance map may be provided.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 12, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. ("TSMC")
    Inventors: Chun Hsiung Tsai, Sheng-Wen Yu, De-Wei Yu
  • Publication number: 20130330843
    Abstract: A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH3); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 12, 2013
    Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael P. Chudzik, Min Dai, Jinping Liu, Paul A. Ronsheim, Joseph F. Shepard, JR., Shahab Siddiqui
  • Patent number: 8604337
    Abstract: A method to determine the cleanness of a semiconductor substrate and the quantity/density of pin holes that may exist within a patterned antireflective coating (ARC) is provided. Electroplating is employed to monitor the changes in the porosity of the ARC caused by the pin holes during solar cell manufacturing. In particular, electroplating a metal or metal alloy to form a metallic grid on an exposed front side surface of a substrate also fills the pin holes. The quantity/density of metallic filled pin holes (and hence the number of pin holes) in the patterned ARC can then be determined.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: John M. Cotte, Laura L. Kosbar, Deborah A. Neumayer, Xiaoyan Shao
  • Patent number: 8602838
    Abstract: A chemical mechanical polishing method is provided. The chemical mechanical polishing method includes steps of providing a plurality of semiconductor elements to be polished, obtaining a respective dimension of the each semiconductor element to be polished, and polishing the each semiconductor element according to the respective dimension thereof.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: December 10, 2013
    Assignee: Mcronix International Co., Ltd.
    Inventors: Meng-Yi Shen, Liang-Yu Hu, Tsung-Hsuan Ho, Sheng-I Tseng
  • Publication number: 20130313718
    Abstract: A method of processing a substrate having integrated circuitry includes forming through-substrate vias partially through the substrate from a first side of the substrate. At least one through-substrate structure is formed partially through the substrate from the first substrate side. The at least one through-substrate structure extends deeper into the substrate than do the through-substrate vias. Substrate material is removed from a second side of the substrate to expose the through-substrate vias and the at least one through-substrate structure on the second substrate side. Additional implementations are disclosed. Integrated circuit substrates are disclosed independent of method of manufacture.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 28, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Sony Varghese, Andrew Carswell, Kozaburo Sakai, Andrey V. Zagrebelny, Wayne Huang, Jin Lu, Suresh Ramakrishnan
  • Patent number: 8592261
    Abstract: A semiconductor device may be designed in the following manner. A stacked layer of a silicon oxide film and an organic film is provided over a substrate, deuterated water is contained in the organic film, and then a conductive film is formed in contact with the organic film. Next, an inert conductive material that does not easily generate a deuterium ion or a deuterium molecule is selected by measuring the amount of deuterium that exists in the silicon oxide film.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: November 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kaoru Hatano, Satoshi Seo
  • Patent number: 8592229
    Abstract: A method for forming a dual damascene structure is disclosed. First a substrate is provided. There are an etching stop layer and an interlayer dielectric layer disposed on the substrate in order. The interlayer dielectric layer has a thickness A. Second, the interlayer dielectric layer is patterned to form a first opening. Later, a photo resist layer with a thickness B is formed on the interlayer dielectric layer. Then, the photo resist layer is patterned by a light source to construct a patterned photo resist layer. Later, the interlayer dielectric layer is again patterned by the patterned photo resist to pattern the interlayer dielectric layer to construct a second opening on the first opening by means of a light source and the photo resist layer so as to form a dual damascene structure. The light source has a periodic parameter C so that (A+B)/C?X/2, where X is an odd number.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: November 26, 2013
    Assignee: United Microelectronics Corp.
    Inventor: Yong-Gang Xie
  • Publication number: 20130302917
    Abstract: A method for forming a multilayer structure comprises the steps of: depositing a first polymerizable layer on a substrate; applying microwave energy to the polymerizable layer while monitoring at least one property of the layer; and, ending the application of microwave energy when the monitored property indicates that the polymerizable layer has reached a desired degree of cure. The property monitored may be optical, e.g., Raman spectrum, or electrical, e.g., dielectric loss. This process control strategy lowers the overall thermal budget, and is especially suitable for curing polymer films on silicon. The method may be used repetitively to cure multiple layers of polymeric material when a thicker film is needed.
    Type: Application
    Filed: May 11, 2012
    Publication date: November 14, 2013
    Inventors: Iftikhar Ahmad, Hubbard Robert
  • Patent number: 8581249
    Abstract: A semiconductor substrate includes a wafer, a first stepped structure formed of plural stepped parts formed on a surface of the wafer with a first area occupation ratio, a second stepped structure formed of plural stepped parts formed on the surface of the wafer with a second, different area occupation ratio, and an interlayer insulation film formed on the surface so as to cover the first and second stepped structures, the interlayer insulation film having a planarized top surface, wherein there are provided at least first and second film-thickness monitoring patterns for monitoring film thickness on the surface in a manner covered by the interlayer insulation film, a first pattern group is formed on the surface such that the first pattern group comprises plural patterns disposed so as to surround the first film-thickness monitoring pattern, a second pattern group is formed on the surface such that the second pattern group comprises plural patterns disposed so as to surround the second film-thickness monitori
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: November 12, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tetsuo Yaegashi, Kouichi Nagai
  • Publication number: 20130292807
    Abstract: Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a second dielectric material on the continuous monolayer of the first dielectric material without exposing the substrate to an air break.
    Type: Application
    Filed: May 7, 2012
    Publication date: November 7, 2013
    Applicant: ASM IP HOLDINGS B.V.
    Inventors: Petri Raisanen, Michael Givens, Mohith Verghese
  • Publication number: 20130295697
    Abstract: A semiconductor device, such as a semiconductor die, is disclosed including embedded temperature sensors for scanning the junction temperature, Tj, at one or more locations of the semiconductor die while the die is operating. Once a temperature of a hot spot is detected that is above a temperature specified for the die or package containing the die, the die/package may be discarded. Alternatively, the functionality of the die may be altered in a way that reduces the temperature of the hot spots.
    Type: Application
    Filed: May 3, 2012
    Publication date: November 7, 2013
    Inventors: Deny Hanan, Eddie Redmard, Itai Dror
  • Publication number: 20130288400
    Abstract: A system and method are disclosed for aligning substrates during successive process steps, such as ion implantation steps, is disclosed. Implanted regions are created on a substrate. After implantation, an image is obtained of the implanted regions, and a fiducial is provided on the substrate in known relation to at least one of the implanted regions. A thermal anneal process is performed on the substrate such that the implanted regions are no longer visible but the fiducial remains visible. The position of the fiducial may be used in downstream process steps to properly align pattern masks over the implanted regions. The fiducial also may be applied to the substrate before any ion implanting of the substrate is performed. The position of the fiducial with respect to an edge or a corner of the substrate may be used for aligning during downstream process steps. Other embodiments are described and claimed.
    Type: Application
    Filed: April 27, 2012
    Publication date: October 31, 2013
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: John W. Graff, Benjamin B. Riordon, Nicholas P.T. Bateman
  • Publication number: 20130280827
    Abstract: A method of controlling a polishing operation includes polishing a substrate, during polishing obtaining a sequence over time of measured spectra from the substrate with an in-situ optical monitoring system, for each measured spectrum from the sequence of measured spectra applying a Fourier transform to the measured spectrum to generate a transformed spectrum thus generating a sequence of transformed spectra, for each transformed spectrum identifying a peak of interest from a plurality of peaks in the transformed spectrum, for each transformed spectrum determining a position value for the peak of interest in the transformed spectrum thus generating a sequence of position values, and determining at least one of a polishing endpoint or an adjustment of a pressure to the substrate from the sequence of position values.
    Type: Application
    Filed: April 23, 2012
    Publication date: October 24, 2013
    Inventors: Dominic J. Benvegnu, Boguslaw A. Swedek
  • Publication number: 20130280828
    Abstract: PICA test methods are shown that includes forming semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size; forming logic circuits to control the semiconductor devices; activating the one or more semiconductor devices by providing an input signal; and suppressing light emissions from one or more of the activated semiconductor devices by providing one or more select signals to the logic circuits.
    Type: Application
    Filed: May 3, 2012
    Publication date: October 24, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: HERSCHEL A. AINSPAN, Seongwon Kim, Franco Stellari, Alan J. Weger