For Structural Parameters, E.g., Thickness, Line Width, Refractive Index, Temperature, Warp, Bond Strength, Defects, Optical Inspection, Electrical Measurement Of Structural Dimensions, Metallurgic Measurement Of Diffusions (epo) Patents (Class 257/E21.53)
  • Patent number: 8564143
    Abstract: An overlay mark is described, including N (N?2) groups of first x-directional linear patterns each defined from a different one of N pre-layers, N groups of second x-directional linear patterns of a current layer, N groups of first y-directional linear patterns each defined from a different one of the N pre-layers, and N groups of second y-directional linear patterns of the current layer. Each group of second x-directional linear patterns is disposed together with one group of first x-directional linear patterns, wherein the second linear patterns and the x-directional linear patterns are arranged alternately. Each group of second y-directional linear patterns is disposed together with one group of first y-directional linear patterns, wherein the second linear patterns and the first linear patterns are arranged alternately.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: October 22, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Ting Chen, Chien-Hao Chen, Yuan-Chi Pai, Chun-Chi Yu
  • Patent number: 8563335
    Abstract: A method of controlling a polishing operation includes polishing a substrate, during polishing obtaining a sequence over time of measured spectra from the substrate with an in-situ optical monitoring system, for each measured spectrum from the sequence of measured spectra applying a Fourier transform to the measured spectrum to generate a transformed spectrum thus generating a sequence of transformed spectra, for each transformed spectrum identifying a peak of interest from a plurality of peaks in the transformed spectrum, for each transformed spectrum determining a position value for the peak of interest in the transformed spectrum thus generating a sequence of position values, and determining at least one of a polishing endpoint or an adjustment of a pressure to the substrate from the sequence of position values.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: October 22, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Dominic J. Benvegnu, Boguslaw A. Swedek
  • Patent number: 8563430
    Abstract: A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: October 22, 2013
    Assignee: SK hynix Inc.
    Inventors: Sang-Jin Byeon, Jun-Gi Choi
  • Publication number: 20130267047
    Abstract: The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 10, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: I-Chang Shih, Chung-min Fu, Ying-Chou Cheng, Yung-Fong Lu, Feng-Yuan Chiu, Chiu Hsiu Chen
  • Publication number: 20130258759
    Abstract: An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second CVdd nodes, the first and second CVss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon. In another embodiment, a word line is formed and bit lines and a CVdd and a CVss line are formed overlying the SRAM cell and coupled to the corresponding ones of the nodes. Methods are disclosed for forming the cell structure.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Publication number: 20130256659
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches.
    Type: Application
    Filed: April 1, 2012
    Publication date: October 3, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chi-Ming Tsai, Liang-Guang Chen, Han-Hsin Kuo, Fu-Ming Huang, Hao-Jen Liao, Ming-Chung Liang
  • Patent number: 8546154
    Abstract: An apparatus and method to inspect a defect of a substrate. Since a recess of an under layer of a substrate is darker than a projection of a top layer, a ratio of a value of a secondary electron signal (of an SEM) of the under layer to a value of the top layer may be increased to improve a pattern image used to inspect an under layer defect. Several conditions under which electron beams are irradiated may be set, and the pattern may be scanned under such conditions. Secondary electron signals may be generated according to the conditions and converted into image data to display various pattern images. Scan information on the images may be stored with positional information on the substrate. Each of scan information on the pattern images may be calculated to generate a new integrated image.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Ji-Young Shin, Young-Nam Kim, Jong-An Kim, Hyung-Suk Cho, Yu-Sin Yang
  • Publication number: 20130252350
    Abstract: A method of generating care areas is disclosed. An artwork file of a layout of a product is provided and a cell tree of the layout is formed. The cell tree includes a plurality of cells of the layout arranged in a hierarchical order. The method also includes defining care areas in the artwork file of the layout.
    Type: Application
    Filed: March 26, 2012
    Publication date: September 26, 2013
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Hun Chow LEE, Shyue Fong QUEK, Seng-Keong Victor LIM, Fang Hong GN
  • Patent number: 8535986
    Abstract: An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: September 17, 2013
    Assignee: Infineon Technologies AG
    Inventors: Liang Kng Ian Koh, Richard Mangapul Sinaga
  • Patent number: 8530247
    Abstract: A method for semiconductor processing is provided, wherein a semiconductor wafer having undergone polishing is provided. The semiconductor wafer has an active region positioned between one or more moat regions, wherein the one or more moat regions have an oxide disposed therein. A top surface of the active region is recessed from a top surface of the moat region, therein defining a step having a step height associated therewith. A step height is measured, and a photoresist is formed over the semiconductor wafer. A modeled step height is further determined, wherein the modeled step height is based on the measured step height and a desired critical dimension of the photoresist. A dosage of energy is determined for patterning the photoresist, wherein the determination of the dosage of energy is based, at least in part, on the modeled step height. The photoresist is then patterned using the determined dosage of energy.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: September 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Brian Douglas Reid, James David Bernstein, Hongyu Yue, Howie Hui Yang, Mark Boehm
  • Patent number: 8530883
    Abstract: Light emitting devices comprise excitation sources arranged to excite quantum dots which fluoresce to emit light. In an embodiment, a device is manufactured by a process which involves applying an acoustic field is applied to a fluid containing quantum dots, to cause the quantum dots to accumulate at locations which are adjacent to excitation sources, and then initiating a phase transition of the fluid to trap the quantum dots in the locations adjacent to the excitation sources. The quantum dots are illuminated during the process and the resulting fluorescence is optically monitored to provide indicators of quantum dot distribution in the fluid. These indicators are used as feedback for controlling aspects of the process, such as initiating the phase transition.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: September 10, 2013
    Assignee: Light-Based Technologies Incorporated
    Inventors: Yohann Sulaiman, Richard MacKellar, Allan Brent York
  • Patent number: 8519260
    Abstract: A method to determine the cleanness of a semiconductor substrate and the quantity/density of pin holes that may exist within a patterned antireflective coating (ARC) is provided. Electroplating is employed to monitor the changes in the porosity of the ARC caused by the pin holes during solar cell manufacturing. In particular, electroplating a metal or metal alloy to form a metallic grid on an exposed front side surface of a substrate also fills the pin holes. The quantity/density of metallic filled pin holes (and hence the number of pin holes) in the patterned ARC can then be determined.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: John M. Cotte, Laura L. Kosbar, Deborah A. Neumayer, Xiaoyan Shao
  • Patent number: 8518722
    Abstract: A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: August 27, 2013
    Assignee: Global Unichip Corporation
    Inventors: Chien-Wen Chen, Chia-Jen Kao, Jui-Cheng Chuang
  • Patent number: 8513045
    Abstract: A laser system with multiple laser pulses for removing material from a solar cell being fabricated. The laser system includes a single pulse laser source and a multi-pulse generator. The multi-pulse generator receives a single pulse laser beam from the single pulse laser source and converts the single pulse laser beam into a multi-pulse laser beam. A laser scanner scans the multi-pulse laser beam onto the solar cell to remove material from the solar cell.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: August 20, 2013
    Assignee: SunPower Corporation
    Inventors: John Viatella, Gabriel Harley, Thomas Pass
  • Publication number: 20130210172
    Abstract: A wafer thinning apparatus includes a first metrology tool configured to measure an initial thickness of the wafer. The wafer thinning apparatus further includes a controller connected to the first metrology tool, and configured to determine a polishing time based on the initial thickness, a predetermined thickness and a material removal rate. The wafer thinning apparatus further includes a polishing tool connected to the controller configured to polish the wafer for a period of time equal to the polishing time. The wafer thinning apparatus includes a second metrology tool connected to the controller and the polishing tool, and configured to measure a polished thickness. The controller is configured to update the material removal rate based on the polished thickness, the predetermined thickness and the polishing time.
    Type: Application
    Filed: February 10, 2012
    Publication date: August 15, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Hsuan Chen, Kei-Wei CHEN, Ying-Lang WANG, Kuo-Hsiu WEI
  • Patent number: 8507297
    Abstract: A wafer containing a plurality of electro-optical devices, each device being enclosed in chamber that has a translucent cover. An X-Y matrix of pairs of interconnections on the wafer are connected to the circuitry of the electro-optical devices for addressing the electro-optical devices. The pairs of interconnections extend outside of the chambers enclosing the devices to testing areas on the periphery of the wafer. Testing is done by signals applied through the interconnections while simultaneously exposing the devices to light through the translucent covers.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: August 13, 2013
    Assignee: Spatial Photonics, Inc.
    Inventors: Shaoher X. Pan, Vlad Novotny
  • Publication number: 20130203188
    Abstract: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves forming a first feature of the semiconductor device structure on a substrate of semiconductor material, obtaining a first measurement for the semiconductor device structure from a first metrology tool, obtaining a second measurement of the first feature of the semiconductor device structure from a second metrology tool, and determining a hybrid measurement for the first feature based at least in part on the first measurement and the second measurement.
    Type: Application
    Filed: February 3, 2012
    Publication date: August 8, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Alok Vaid, Ned R. Saleh, Matthew J. Sendelbach, Narender Rana
  • Patent number: 8502290
    Abstract: Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 6, 2013
    Assignee: OmniVision Technologies, Inc.
    Inventors: Duli Mao, Hsin-Chih Tai, Vincent Venezia, Yin Qian, Howard E. Rhodes
  • Patent number: 8501500
    Abstract: The present invention discloses a method for monitoring the removal of a polycrystalline silicon dummy gate, comprising the steps of: forming a polycrystalline silicon dummy gate structure on a surface of a wafer; determining a measurement target and an error range of mass of the wafer; and measuring the mass of the wafer by a mass measurement tool after polycrystalline silicon dummy gate removal to determine whether the polycrystalline silicon dummy gate has been completely removed. According to the measurement method of the present invention, the full wafer may be quickly and accurately measured without requiring a specific test structure, to effectively monitor and determine whether the polysilicon dummy gate is thoroughly removed, meanwhile said measurement method gives feedback directly, quickly and accurately without causing any damage to the wafer.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: August 6, 2013
    Assignee: The Institute of Microelectronics, Chinese Academy of Science
    Inventors: Tao Yang, Chao Zhao, Junfeng Li, Jiang Yan, Dapeng Chen
  • Publication number: 20130196455
    Abstract: Systems and methods are disclosed for performing laser annealing in a manner that reduces or minimizes wafer surface temperature variations during the laser annealing process. The systems and methods include annealing the wafer surface with first and second laser beams that represent preheat and anneal laser beams having respective first and second intensities. The preheat laser beam brings the wafer surface temperate close to the annealing temperature and the anneal laser beam brings the wafer surface temperature up to the annealing temperature. The anneal laser beam can have a different wavelength, or the same wavelength but different orientation relative to the wafer surface. Reflectivity maps of the wafer surface at the preheat and anneal wavelengths are measured and used to select first and second intensities that ensure good anneal temperature uniformity as a function of wafer position.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 1, 2013
    Inventors: Xiaohua Shen, Yun Wang, Xiaoru Wang
  • Patent number: 8497142
    Abstract: Methods of forming conductive patterns include forming a conductive layer including a metal element on a substrate. The conductive layer is partially etched to generate a residue including an oxide of the metal element and to form a plurality of separately formed conductive layer patterns. A cleaning gas is inflowed onto the substrate including the conductive layer pattern. The metal compound is evaporated to remove the metal element contained in the residue and to form an insulating interface layer on the conductive layer pattern and a surface portion of the substrate through a reaction of a portion of the cleaning gas and oxygen. The residue may be removed from the conductive layer pattern to suppress generation of a leakage current.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: July 30, 2013
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Jun-Kyu Yang, Young-Geun Park, Ki-Hyun Hwang, Han-Mei Choi, Dong-Chul Yoo
  • Patent number: 8497141
    Abstract: A method of manufacturing a semiconductor device capable of largely increasing the yield and a semiconductor device manufactured by using the method is provided. After a semiconductor layer is formed on a substrate, as one group, a plurality of functional portions with at least one parameter value different from each other is formed in the semiconductor layer for every unit chip area. Then, a subject that is changed depending on the parameter value is measured and evaluated and after that, the substrate is divided for every chip area so that a functional portion corresponding with a given criterion as a result of the evaluation is not broken. Thereby, at least one functional portion corresponding with a given criterion can be formed by every chip area by appropriately adjusting each parameter value.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: July 30, 2013
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Kayoko Kikuchi, Rintaro Koda, Norihiko Yamaguchi
  • Patent number: 8492175
    Abstract: A method is provided for assembling a stack of surface-mount devices (SMDs) on a substrate. The method provides a substrate, die, or printed circuit board (PCB) with a top surface having a landing pad and a first reference feature. An alignment jig is placed overlying the substrate top surface. The alignment jig second reference feature is aligned with respect to the substrate first reference feature. A first SMD is placed overlying the substrate landing pad. The first SMD third reference feature is aligned with respect to the alignment jig second reference feature. A second SMD is placed overlying the substrate top surface. Then, the alignment jig first boundary feature is mated with the second SMD second boundary feature. In response to the mating, the second SMD first interface is aligned over an underlying SMD active element.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: July 23, 2013
    Assignees: Applied Micro Circuits Corporation, Volex PLC
    Inventor: Robert James Fanfelle
  • Patent number: 8471368
    Abstract: This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: June 25, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yu Wang, Tiesheng Li, Sung-Shan Tai, Hong Chang
  • Publication number: 20130157389
    Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes forming a first structure in a first layer by a first exposure and determining placement information of the first structure. The method further includes forming a second structure in a second layer overlying the first layer by a second exposure and determining placement information of the second structure. The method further includes forming a third structure including first and second substructures in a third layer overlying the second layer by a third exposure.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
  • Publication number: 20130147035
    Abstract: A semiconductor device has a semiconductor die with composite bump structures over a surface of the semiconductor die. A conductive layer is formed over the substrate. The conductive layer has a channel in an interconnect site of the conductive layer. The channel extends beyond a footprint of the composite bump structures. The semiconductor die is disposed over the substrate. The bump material of the composite bump structures is melted. The composite bump structures are pressed over the interconnect site of the conductive layer so that the melted bump material flows into the channel. Electrical continuity between the composite bump structures and conductive layer is detected by a presence of the bump material in the channel. No electrical continuity between the composite bump structures and conductive layer is detected by an absence of the bump material in the channel. The electrical continuity can be detected by visual inspection or X-ray.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Jen Yu Chen, Chien Chen Lee, Yi Wen Huang, Ke Jung Jen
  • Publication number: 20130142478
    Abstract: An apparatus includes a slider structure having a top surface and a bottom surface opposite from the top surface. The apparatus includes a waveguide with an input facet at the top surface and an output proximate the bottom surface. A laser having an output facet is positioned proximate the input facet of the waveguide and include a second plurality of pads facing a first plurality of pads on the top surface of the slider. A bonding material is disposed between individual ones of the first and second plurality of pads such that a reflow of the bonding material induces relative movement between the laser and the top surface to align the input and output facets.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: David A. Sluzewski, Scott E. Olson
  • Publication number: 20130137197
    Abstract: Methods for quantitatively measuring the performance of a plasma immersion process are provided herein. In some embodiments, a method of quantitatively measuring the performance of a plasma immersion process, using a first substrate comprising an oxide layer deposited atop a silicon layer, may include subjecting the first substrate to a plasma immersion process in a first plasma immersion chamber to form a doped oxide layer atop the first substrate; and determining a thickness of the doped oxide layer by shining a beam of light upon a reflective surface of the doped oxide layer; detecting reflected beams of light off of the reflective surface of the doped oxide layer; and analyzing the reflected beams of light to determine the thickness of the doped oxide layer on the first substrate.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: APPLIED MATERIALS, INC.
    Inventors: DAPING YAO, PETER I. PORSHNEV, MARTIN A. HILKENE, MATTHEW D. SCOTNEY-CASTLE, MANOJ VELLAIKAL
  • Patent number: 8450123
    Abstract: Experience shows that, in a material containing oxygen as a main component, an excess or deficiency of trace amounts of oxygen with respect to a stoichiometric composition, or the like affects properties of the material. An oxygen diffusion evaluation method of an oxide film stacked body includes the steps of: measuring a quantitative value of one of oxygen isotopes of a substrate including a first oxide film and a second oxide film which has an existence proportion of an oxygen isotope different from an existence proportion of an oxygen isotope in the first oxide film in a depth direction, by secondary ion mass spectrometry; and evaluating the one of the oxygen isotopes diffused from the first oxide film to the second oxide film.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: May 28, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Okazaki, Keitaro Imai, Atsuo Isobe, Shunpei Yamazaki
  • Publication number: 20130127064
    Abstract: In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 23, 2013
    Inventors: Douglas M. Reber, Lawrence N. Herr
  • Publication number: 20130122610
    Abstract: A die bonding apparatus and a die bonding method are provided, which are capable of simultaneously bonding a plurality of dies from a first placement area onto a substrate disposed on a second placement area. The die bonding apparatus includes a die sucking device which is movably located above the first placement area and a second placement area. The die sucking device includes a plurality of nozzles. The nozzles can suck the dies disposed on the first placement area, and then simultaneously bond the dies onto the substrate.
    Type: Application
    Filed: May 1, 2012
    Publication date: May 16, 2013
    Applicant: WALSIN LIHWA CORPORATION
    Inventors: Jun-Wei Chung, Wei-Cheng Lou, Jung-Kun Wu, Chung-I Chiang
  • Publication number: 20130115720
    Abstract: A method and apparatus for determining grain size of a surface. A light source is directed at the surface. Reflected light from the surface is detected. A peak surface grain wavelength is determined from the reflected light. The peak surface grain wavelength is converted to a grain size. Grain size of a semiconductor surface is used as a feedback input to control a manufacturing process.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 9, 2013
    Inventors: Arnold Allenic, Oleh Petro Karpenko, Erel Milshtein, Ming L. Yu
  • Patent number: 8431421
    Abstract: A semiconductor chip including a test pattern is provided. The semiconductor chip includes a semiconductor substrate; a through-wafer via in the semiconductor substrate; and a plurality of conductive patterns over the semiconductor substrate and adjacent to each other. The bottom surfaces of the plurality of conductive patterns and a top surface of the through-wafer via are substantially coplanar. The through-wafer via is at least adjacent to the plurality of conductive patterns. The semiconductor chip further includes a plurality of bonding pads on a surface of the semiconductor chip, each being connected to one of the plurality of conductive patterns.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: April 30, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chih-Hua Chen
  • Publication number: 20130099387
    Abstract: A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.
    Type: Application
    Filed: October 20, 2011
    Publication date: April 25, 2013
    Applicant: INVENSAS CORP.
    Inventors: Terrence Caskey, Ilyas Mohammed
  • Patent number: 8426857
    Abstract: A method for producing a semiconductor device comprising a process step of forming a device configuration pattern in a device formation region in a chip formation region on a film side of a semiconductor wafer having the film for forming a pattern, and forming inspection patterns in a plurality of inspection regions in the chip formation region, and an inspection step, wherein the inspection patterns have a repeat pattern and a uniform pattern formed in a first inspection region in the plurality of inspection regions, the inspection step has at least a pattern inspection step including a first inspection to measure a parameter of the repeat pattern, by using an optical measurement method capable of measuring a three-dimensional pattern shape, and a second inspection to measure a film thickness of the uniform pattern by using an optical measurement method capable of measuring the film thickness.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: April 23, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Noritaka Kamikubo
  • Patent number: 8420498
    Abstract: An alignment method of chips that are formed on a surface of a semiconductor wafer with alignment marks corresponding to the chips includes the steps of irradiating an alignment mark corresponding to a predetermined alignment chip in a predetermined area including the chips with a laser light; detecting reflected waves from the alignment mark of the predetermined alignment chip to obtain a position of the alignment mark of the predetermined alignment chip; irradiating an alignment mark of an alternative chip different from the predetermined alignment chip with the laser light in case of not being able to obtain the position of the alignment mark of the predetermined alignment chip; obtaining a position of the alignment mark of the alternative chip by detecting the reflected waves from the alignment mark of the alternative chip; and aligning the chips in the predetermined area based on positions of alignment marks including the position of the alignment mark of the alternative chip.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: April 16, 2013
    Assignee: Mitsumi Electric Co., Ltd.
    Inventor: Yukihiro Tanemura
  • Publication number: 20130089935
    Abstract: The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a wafer shape change value at each of the points, generating a set of slope of shape change values at each of the points, calculating a set of process tool correctables utilizing the generated set of slope of shape change values, generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables, defining a plurality of metric analysis regions distributed across the surface, and then generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region.
    Type: Application
    Filed: May 21, 2012
    Publication date: April 11, 2013
    Applicant: KLA-TENCOR CORPORATION
    Inventors: Pradeep Vukkadala, Sathish Veeraraghavan, Jaydeep K. Sinha
  • Publication number: 20130087915
    Abstract: There is provided a system and method for a copper stud bump wafer level package. There is provided a semiconductor package comprising a semiconductor die having a plurality of bond pads on an top surface thereof, a plurality of metallic stud bumps mechanically and electrically coupled to said plurality of bond pads, and a plurality of solder balls mechanically and electrically coupled to said plurality of metallic stud bumps. Advantageously, the metallic stud bumps may be provided using standard wirebonding equipment, avoiding the conventional wafer level package requirement for photolithography and deposition steps to provide a multi-layer metallic routing structure. As a result, reduced cycle times, lower cost, and reduced complexity may be provided. Alternative fabrication processes utilizing metallic stud bumps may also support multi-die packages with dies from different wafers and packages with die perimeter pads wirebonded to substrates.
    Type: Application
    Filed: October 10, 2011
    Publication date: April 11, 2013
    Applicant: CONEXANT SYSTEMS, INC.
    Inventors: Robert W. Warren, Nic Rossi, Hyun Jung Lee
  • Publication number: 20130089934
    Abstract: A system and method for controlling saturated vapor pressure of a precursor material is provided. An embodiment comprises generating a calibration curve and utilizing the calibration curve to control a temperature of the precursor material in order to control its saturated vapor pressure. Alternatively, the calibration curve may be substituted for a real time sensor which can take readings in real time and adjust the temperature and saturated vapor pressure based upon the real time readings.
    Type: Application
    Filed: October 7, 2011
    Publication date: April 11, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ke-Chih Liu, Chia-Ming Tsai, Yen-Yu Chen
  • Publication number: 20130084660
    Abstract: A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method also includes performing an ion implantation process to the back surface of the silicon substrate and performing a green laser annealing process to the implanted back surface of the silicon substrate. The green laser annealing process uses an annealing temperature greater than or equal to about 1100° C. for a duration of about 100 to about 400 nsec. After performing the green laser annealing process, a silicon polishing process is performed on the back surface of the silicon substrate.
    Type: Application
    Filed: December 22, 2011
    Publication date: April 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shou Shu Lu, Hsun-Ying Huang, I-Chang Lin, Chia-Chi Hsiao, Yung-Cheng Chang
  • Publication number: 20130084654
    Abstract: A method of forming a semiconductor device. A substrate having first and second materials is provided, wherein the second material is occluded by the first material. The substrate is etched using a first non-plasma etch process that etches the first material at a higher rate relative to a rate of etching the second material. The first non-plasma etch process exposes the second material that is overlying at least a portion of the first material. The second material is then etched using a plasma containing a reactive gas, which exposes the at least a portion of the first material. The first material including the at least a portion of the first material that was exposed by etching the second material are etched using a second non-plasma etch process.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: Tokyo Electron Limited
    Inventors: Richard H. Gaylord, Blaze J. Messer, Kaushik A. Kumar
  • Publication number: 20130078746
    Abstract: Correction of reticle defects, such as EUV reticle defects, is accomplished with a second exposure. Embodiments include obtaining a reticle with a first pattern corresponding to a design for a wafer pattern, detecting dark defects and/or design/OPC weak spots in the first pattern, exposing a resist covered wafer using the reticle, and exposing the wafer using a second reticle with a second pattern or a second image field with openings corresponding to the dark defects, with a repair pattern on the reticle or on another reticle, or with a programmed e-beam or laser writer.
    Type: Application
    Filed: September 24, 2011
    Publication date: March 28, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventor: Arthur Hotzel
  • Patent number: 8404498
    Abstract: A method of forming a semiconductor thin film includes: a step of forming an amorphous semiconductor thin film over a transparent substrate; a step of forming a crystalline semiconductor thin film by irradiating the amorphous semiconductor thin film with laser light to provide heat treatment and thereby crystallizing the amorphous semiconductor thin film; and an inspection step of inspecting the crystalline semiconductor thin film. The inspection step includes a step of obtaining a transmission image of the crystalline semiconductor thin film by irradiating the crystalline semiconductor thin film with light from a rear side of the transparent substrate and taking an image, and a screening step of performing screening of the crystalline semiconductor thin film based on the obtained transmission image.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: March 26, 2013
    Assignee: Sony Corporation
    Inventors: Hirohisa Amago, Nobuhiko Umezu
  • Patent number: 8399275
    Abstract: According to one embodiment, a method for manufacturing a semiconductor light emitting device is disclosed. The method can include forming a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, a second insulating layer, a transparent material and a phosphor layer. The transparent material is formed on the first major surface of a semiconductor layer selected from the plurality of semiconductor layers on the basis of an emission spectrum of a light obtained from the first major surface side. The transparent material transmits the light. The phosphor layer is formed on the transparent material and the first major surface of the plurality of the semiconductor layers.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: March 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Akimoto, Akihiro Kojima, Miyuki Izuka, Yoshiaki Sugizaki, Hiroshi Koizumi, Tomomichi Naka, Yasuhide Okada
  • Patent number: 8399264
    Abstract: The present disclosure relates to the field of microelectronic substrate fabrication and, more particularly, to alignment inspection for vias formed in the microelectronic substrates. The alignment inspection may be achieved by determining the relative positions of fluorescing and non-fluorescing elements in a microelectronic substrate.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: March 19, 2013
    Assignee: Intel Corporation
    Inventors: Zhihua Zou, Liang Zhang, Sheng Li, Tamil Selvamuniandy
  • Patent number: 8399263
    Abstract: An expansion/contraction measuring apparatus includes a transport section which transports a flexible substrate along a surface of the substrate; a detecting section detecting first and second marks which are formed on the substrate while being separated from each other by a predetermined spacing distance in a transport direction of the substrate and which are moved, in accordance with the transport of the substrate, to first and second detection areas disposed on a transport route for the substrate respectively; a substrate length setting section which sets a length of the substrate along the transport route between the first and second detection areas to a reference length; and a deriving section which derives information about expansion/contraction of the substrate in relation to the transport direction based on a detection result of the first and second marks. Accordingly, the expansion/contraction state of an expandable/contractible substrate is measured highly accurately.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: March 19, 2013
    Assignee: Nikon Corporation
    Inventors: Tohru Kiuchi, Hideo Mizutani
  • Publication number: 20130062603
    Abstract: A test structure for measuring a Micro-Electro-Mechanical System (MEMS) cavity height structure and calibration method. The method includes forming a sacrificial cavity material over a plurality of electrodes and forming an opening into the sacrificial cavity material. The method further includes forming a transparent or substantially transparent material in the opening to form a transparent or substantially transparent window. The method further includes tuning a thickness of the sacrificial cavity material based on measurements obtained through the transparent or substantially transparent window.
    Type: Application
    Filed: September 13, 2011
    Publication date: March 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey C. Maling, Anthony K. Stamper, Eric J. White
  • Publication number: 20130064500
    Abstract: A laser diode includes a junction surface configured to interface with an integrated optics slider. Cathode and anode electrical junctions are disposed on the junction surface. The cathode and anode electrical junctions are configured for electrical and mechanical coupling to the integrated optics slider. At least one test pad is disposed on the junction surface that is physically separate from and electrically coupled to one of the cathode and anode electrical junctions. The test pad is configured to be contacted by a test probe and is not configured for electrical or mechanical coupling to the integrated optics slider.
    Type: Application
    Filed: September 13, 2011
    Publication date: March 14, 2013
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventor: Scott E. Olson
  • Patent number: 8394708
    Abstract: A method and system for assembling a quasicrystalline heterostructure. A plurality of particles is provided with desirable predetermined character. The particles are suspended in a medium, and holographic optical traps are used to position the particles in a way to achieve an arrangement which provides a desired property.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: March 12, 2013
    Assignees: New York University, The Trustees of Princeton University
    Inventors: David G. Grier, Yael Roichman, Weining Man, Paul Michael Chaikin, Paul Joseph Steinhardt
  • Publication number: 20130058045
    Abstract: A heatsink may include an area in thermal contact with a semiconductor microchip surface and a first trench of a first depth. The first trench may be substantially continuous around the area. A first substance, such as ferrite, may be positioned in the first trench to attenuate electromagnetic interference. A second trench having a second depth may be formed around and further from the area than the first trench. A second substance may be positioned in the second trench.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Don A. Gilliland