For Structural Parameters, E.g., Thickness, Line Width, Refractive Index, Temperature, Warp, Bond Strength, Defects, Optical Inspection, Electrical Measurement Of Structural Dimensions, Metallurgic Measurement Of Diffusions (epo) Patents (Class 257/E21.53)
  • Publication number: 20120235208
    Abstract: A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.
    Type: Application
    Filed: March 15, 2011
    Publication date: September 20, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hui Chen, Ruey-Bin Sheen, Yung-Chow Peng, Po-Zeng Kang, Chung-Peng Hsieh
  • Publication number: 20120235142
    Abstract: There are provided a semiconductor light emitting diode chip, a method of manufacturing thereof, and a method for quality control using the same. The semiconductor light emitting diode chip includes a substrate; a light emitting diode in one area of the substrate and at least one fuse signature circuit formed in the other area of substrate so as to be electrically insulated from the light emitting diode. The fuse signature circuit includes a circuit unit having unique electrical characteristic value corresponding to wafer based process information and a plurality of electrode pads connected to the circuit unit. The semiconductor light emitting diode chip may include chip information marking representing information.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 20, 2012
    Inventors: Young Hee SONG, Seong Jae HONG, Seong Deok HWANG
  • Publication number: 20120231557
    Abstract: The present invention aims to provides a method of manufacturing a film for a semiconductor device in which a dicing film, a die bond film, and a protecting film are laminated in this order, including the steps of: irradiating the die bond film with a light ray having a wavelength of 400 to 800 nm to detect the position of the die bond film based on the obtained light transmittance and punching the dicing film out based on the detected position of the die bond film, and in which T2/T1 is 0.04 or more, wherein T1 is the light transmittance of the portion where the dicing film and the protecting film are laminated and T2 is the light transmittance of the portion where the dicing film, the die bond film, and the protecting film are laminated.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 13, 2012
    Inventors: Koichi INOUE, Miki MORITA, Yuichiro SHISHIDO
  • Publication number: 20120228743
    Abstract: Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.
    Type: Application
    Filed: May 24, 2012
    Publication date: September 13, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: O Seo Park, Wai-Kin Li
  • Publication number: 20120231560
    Abstract: A semiconductor light-emitting device having a thinned structure comprises a thinned structure formed between a semiconductor light-emitting structure and a carrier. The manufacturing method comprises the steps of forming a semiconductor light-emitting structure above a substrate; attaching the semiconductor light-emitting structure to a support; thinning the substrate to form a thinned structure; forming or attaching a carrier to the thinned substrate; and removing the support.
    Type: Application
    Filed: May 23, 2012
    Publication date: September 13, 2012
    Inventors: Min-Hsun Hsieh, Chih-Chiang Lu, Chien-Yuan Wang, Yen-Wen Chen, Jui-Hung Yeh, Shih-Chin Hung, Yu-Wei Tu, Chun-Yi Wu, Wei-Chih Peng
  • Publication number: 20120231562
    Abstract: A semiconductor manufacturing apparatus includes: a treatment chamber treating a treated film of a wafer using a desired chemical fluid; a film thickness measurement unit measuring an initial film thickness of the treated film before treatment and a final film thickness of the treated film after treatment; and a main body controlling unit calculating a treatment speed of the chemical fluid from the initial film thickness, the final film thickness, and a chemical fluid treatment time taken from the initial film thickness to the final film thickness to calculate a chemical fluid treatment time for a wafer to be treated next from the calculated treatment speed.
    Type: Application
    Filed: February 29, 2012
    Publication date: September 13, 2012
    Applicant: SONY CORPORATION
    Inventors: Yukari Takeya, Hayato Iwamoto, Yoshiya Hagimoto, Eizo Motooka
  • Publication number: 20120231558
    Abstract: A method and system are disclosed for determining at least one optical characteristic of a substrate, such as a semiconductor wafer. Once the optical characteristic is determined, at least one parameter in a processing chamber may be controlled for improving the process. For example, in one embodiment, the reflectivity of one surface of the substrate may first be determined at or near ambient temperature. From this information, the reflectance and/or emittance of the wafer during high temperature processing may be accurately estimated. The emittance can be used to correct temperature measurements using a pyrometer during wafer processing. In addition to making more accurate temperature measurements, the optical characteristics of the substrate can also be used to better optimize the heating cycle.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 13, 2012
    Applicant: Mattson Technology, Inc
    Inventor: Paul Janis Timans
  • Publication number: 20120231559
    Abstract: A method of forming a semiconductor thin film includes the steps of: forming an amorphous semiconductor thin film on a substrate; forming a crystalline semiconductor thin film partially in each element region by applying laser light to the amorphous semiconductor thin film to selectively perform a heating process on the amorphous semiconductor thin film, thereby crystallizing the amorphous semiconductor thin film in a region irradiated with the laser light; and inspecting the crystallinity degree of the crystalline semiconductor thin film. The step of inspecting includes the steps of determining a contrast between the luminance of a crystallized region and the luminance of a non-crystallized region by applying light to the crystalline semiconductor thin film and the amorphous semiconductor thin film, and performing screening of the crystalline semiconductor thin film on the basis of the determined contrast.
    Type: Application
    Filed: May 22, 2012
    Publication date: September 13, 2012
    Applicant: SONY CORPORATION
    Inventors: Nobuhiko UMEZU, Koichi TSUKIHARA, Hirohisa AMAGO, Go MATSUNOBU, Katsuya SHIRAI
  • Publication number: 20120225503
    Abstract: A method is provided including depositing a layer of material on a substrate, during deposition of the material, at a predetermined depth, laterally implanting a first dopant and a second dopant in the material, the second dopant being different from the first dopant, etching the material, during etching, detecting the positions and intensities of the first and second dopants, and calculating lateral homogeneity of the material in situ from the intensities of the first and second dopants.
    Type: Application
    Filed: May 15, 2012
    Publication date: September 6, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Dmytro CHUMAKOV, Peter BAARS
  • Publication number: 20120225501
    Abstract: Provided is a three-dimensional semiconductor device. The three-dimensional semiconductor device includes a body in which a plurality of semiconductor chips or packages are stacked, a protective substrate configured to protect an outer layer chip or package of the body and configured to transmit a laser beam, and a fuse pattern portion having a pattern of a fuse function formed to cut off an electrical connection of a defective chip or package by the laser beam penetrating the protective substrate when at least one of the chips or packages is defective.
    Type: Application
    Filed: May 11, 2012
    Publication date: September 6, 2012
    Applicant: EPWORKS CO., LTD.
    Inventor: Gu-Sung Kim
  • Publication number: 20120220058
    Abstract: A method of fabricating a semiconductor device includes preparing a layout of the semiconductor device, obtaining contrast of an exposure image of the layout through a simulation under a condition of using a crosspole illumination system, separating the layout into a plurality of sub-layouts based on the contrast of the exposure image, forming a photomask having a mask pattern corresponding to the plurality of sub-layouts, and performing an exposure process using the photomask under an exposure condition of using a dipole illumination system.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 30, 2012
    Inventors: Jee-eun JUNG, Kyoung-yun Baek, Seong-woon Choi
  • Patent number: 8252609
    Abstract: A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semiconductor surface into at least one amorphous surface region After or contemporaneously with the crystal damaging, the amorphous surface region is recrystallized by recrystallization annealing that anneals the wafer for a time ?5 seconds at a temperature sufficient for recrystallization of the amorphous surface region. A subsequent photolithography step is facilitated due to the reduction in average wafer curvature provided by the recrystallization.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: August 28, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Brian K. Kirkpatrick, Steven L. Prins, Amitabh Jain
  • Patent number: 8252608
    Abstract: A sample with at least a first structure and a second structure is measured and a first model and a second model of the sample are generated. The first model models the first structure as an independent variable and models the second structure. The second model of the sample models the second structure as an independent variable. The measurement, the first model and the second model together to determine at least one desired parameter of the sample. For example, the first structure may be on a first layer and the second structure may be on a second layer that is under the first layer, and the processing of the sample may at least partially remove the first layer, wherein the second model models the first layer as having a thickness of zero.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: August 28, 2012
    Assignee: Nanometrics Incorporated
    Inventors: Ye Feng, Zhuan Liu
  • Publication number: 20120214259
    Abstract: Experience shows that, in a material containing oxygen as a main component, an excess or deficiency of trace amounts of oxygen with respect to a stoichiometric composition, or the like affects properties of the material. An oxygen diffusion evaluation method of an oxide film stacked body includes the steps of: measuring a quantitative value of one of oxygen isotopes of a substrate including a first oxide film and a second oxide film which has an existence proportion of an oxygen isotope different from an existence proportion of an oxygen isotope in the first oxide film in a depth direction, by secondary ion mass spectrometry; and evaluating the one of the oxygen isotopes diffused from the first oxide film to the second oxide film.
    Type: Application
    Filed: August 19, 2011
    Publication date: August 23, 2012
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Okazaki, Keitaro Imai, Atsuo Isobe, Shunpei Yamazaki
  • Publication number: 20120208302
    Abstract: There is provided a method for manufacturing a SiC semiconductor device achieving improved performance. The method for manufacturing the SiC semiconductor device includes the following steps. That is, a SiC semiconductor is prepared which has a first surface having at least a portion into which impurities are implanted. By cleaning the first surface of the SiC semiconductor, a second surface is formed. On the second surface, a Si-containing film is formed. By oxidizing the Si-containing film, an oxide film constituting the SiC semiconductor device is formed.
    Type: Application
    Filed: February 25, 2011
    Publication date: August 16, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Satomi Itoh, Hiromu Shiomi, Yasuo Namikawa, Keiji Wada, Mitsuru Shimazu, Toru Hiyoshi
  • Patent number: 8242499
    Abstract: A method of producing a semiconductor device includes the steps of preparing an SOQ (Silicon On Quartz) substrate in which a semiconductor layer is formed on a quartz substrate; forming a plurality of semiconductor device forming regions in the SOQ substrate; forming a crack inspection pattern in the SOQ substrate; inspecting the crack inspection pattern to detect a crack in the crack inspection pattern in a first inspection step; and inspecting the semiconductor device forming regions to detect a crack in the semiconductor device forming regions in a second inspection step when the crack is detected in the crack inspection pattern in the first inspection step.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: August 14, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Toshio Nagata
  • Patent number: 8241988
    Abstract: A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: August 14, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-ho Kwon, Chang-ki Hong, Bo-un Yoon, Jae-dong Lee, Sang-jin Kim
  • Publication number: 20120202300
    Abstract: A method for assembling integrated circuit (IC) devices includes dispensing a die attach adhesive onto a surface of a workpiece using a die bonding system, and placing an IC die on the die attach adhesive at surface of the workpiece to form an IC device. A pre-cure bond line thickness (pre-cure BLT) value is automatically optically measured for the die attach adhesive. The IC device is unloaded from the die bonding system after automatically optically measuring. The method can include comparing the pre-cure BLT value to a pre-cure BLT specification range, and if the pre-cure BLT value is outside the pre-cure BLT specification range, adjusting at least one die attach adhesive dispensing parameter based on the pre-cure BLT value for subsequent assembling. The adjusting can be automatic adjusting and the adjustment can be to the Z height parameter of the bond arm.
    Type: Application
    Filed: February 3, 2011
    Publication date: August 9, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Frank Yu, Eric Hsieh, Twu Ares, Wei-Lung Hsu
  • Publication number: 20120199830
    Abstract: Temperatures in microelectronic integrated circuit packages and components may be measured in situ using carbon nanotube networks. An array of carbon nanotubes strung between upstanding structures may be used to measure local temperature. Because of the carbon nanotubes, a highly accurate temperature measurement may be achieved. In some cases, the carbon nanotubes and the upstanding structures may be secured to a substrate that is subsequently attached to a microelectronic package.
    Type: Application
    Filed: April 16, 2012
    Publication date: August 9, 2012
    Inventors: Nachiket R. Raravikar, Neha Patel
  • Publication number: 20120202303
    Abstract: The disclosure provides a customized manufacturing method for an optoelectrical device. The customized manufacturing method comprises the steps of providing a manufacturing flow including a front-end flow, a customized module subsequent to the front-end flow, and a pause step between the front-end flow and the customized module, processing a predetermined amount of semi-manufactured products queued at the pause step, tuning the customized module in accordance with a customer's request, and processing the semi-manufactured products by the tuned customized module to fulfill the customer's request.
    Type: Application
    Filed: April 23, 2012
    Publication date: August 9, 2012
    Applicant: EPISTAR CORPORATION
    Inventor: Min-Hsun Hsieh
  • Publication number: 20120202301
    Abstract: A disclosed method of forming a mask pattern includes forming a first resist film on a film to be etched, opening portions on the first resist film at a predetermined pitch, a first film on the first resist film so as to cover sidewalls of the first opening portions, a second resist film, second opening portions alternately arranged with the first opening portions on the second resist film, and a second film on the second resist film so as to cover sidewalls of the second opening portions, and removing a part of the second film so that the second film is left as first sidewall portions, a part of the first resist film using the first sidewall portions as a mask to form third opening portions, and a part of the first film while leaving the first film as second sidewall portions to form fourth opening portions.
    Type: Application
    Filed: January 23, 2012
    Publication date: August 9, 2012
    Applicant: Tokyo Electron Limited
    Inventor: Hidetami YAEGASHI
  • Patent number: 8236580
    Abstract: A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in an inert atmosphere; (c) submerging, for a present duration of time, the substrate into an aqueous solution, the aqueous solution to be monitored for copper contamination; and (d) determining an amount of copper adsorbed from the aqueous solution by the region of the substrate.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jay Sanford Burnham, Joseph Kerry Vaughn Comeau, Leslie Peter Crane, James Randall Elliott, Scott Alan Estes, James Spiros Nakos, Eric Jeffrey White
  • Publication number: 20120193669
    Abstract: A method for manufacturing an optoelectronic semiconductor component, comprising: providing a semiconductor chip in a composite wafer, comprising an active side for emitting a primary radiation and a contact terminal which is arranged on the active side; depositing a coupling element on the active side; attaching a luminescence conversion element, for converting part of the primary radiation into a secondary radiation, to the coupling element.
    Type: Application
    Filed: September 27, 2010
    Publication date: August 2, 2012
    Inventors: Hans-Christoph Gallmeier, Michael Kruppa, Raimund Schwarz, Guenter Spath
  • Publication number: 20120190138
    Abstract: According to one embodiment, semiconductor manufacturing apparatus includes a first member that holds a first semiconductor substrate; a second member that holds a second semiconductor substrate in a state where a bonding surface of the second semiconductor substrate faces a bonding surface of the first semiconductor substrate; a distance detecting unit that detects a distance between the bonding surface of the first semiconductor substrate and the bonding surface of the second semiconductor substrate; an adjusting unit that adjusts the distance between the bonding surface of the first semiconductor substrate and the bonding surface of the second semiconductor substrate to a predetermined value by moving at least one of the first and second members based on a detection result of the distance detecting unit; and a third member that forms the bonding start point between the first semiconductor substrate and the second semiconductor substrate.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 26, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa TANIDA, Satoshi Hongo, Naoko Yamaguchi, Kenji Takahashi, Hideo Numata
  • Publication number: 20120190137
    Abstract: Provided is a cross section observation method, including the steps of: forming a marker layer at a base material, the marker layer having a conductivity different from that of another portion of the base material; forming a sample, by performing treatment on the base material at which the marker layer is formed; and detecting secondary electrons generated by emitting electrons to a cross section of the sample.
    Type: Application
    Filed: January 24, 2011
    Publication date: July 26, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Satomi ITO, Takeyoshi MASUDA
  • Patent number: 8216879
    Abstract: A method for manufacturing a semiconductor device or apparatus having at least a semiconductor as a component, characterized by including irradiating the semiconductor with light having a longer wavelength than the absorption edge wavelength of the semiconductor to change the threshold voltage of the semiconductor device or apparatus, and checking the threshold voltage of the semiconductor device or apparatus, after or during irradiation with the light, to determine whether the threshold voltage is in a predetermined range, during manufacturing the semiconductor device or apparatus.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: July 10, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuyuki Kaji, Masato Ofuji, Yasuyoshi Takai, Takehiko Kawasaki, Norio Kaneko, Ryo Hayashi
  • Publication number: 20120168823
    Abstract: The present application discloses a semiconductor device and a method for forming the same. The method comprises: providing a first semiconductor layer and forming a first STI in the first semiconductor layer; determining a selected region in the first semiconductor layer, and making a portion of the first semiconductor layer in the selected region recessed; and in the selected region, epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the material of the second semiconductor layer is different from that of the first semiconductor layer. According to the present invention, a structure with a second semiconductor layer selectively epitaxially grown and embedded in the first semiconductor layer can be formed by a simple process, and defects generated during the epitaxial growth process can be further reduced.
    Type: Application
    Filed: April 25, 2011
    Publication date: July 5, 2012
    Inventors: Zhijiong Luo, Haizhou Yin, Huilong Zhu
  • Publication number: 20120168719
    Abstract: To provide an epitaxial substrate for electronic devices, in which current flows in a lateral direction, which enables accurate measurement of the sheet resistance of HEMTs without contact, and to provide a method of efficiently producing the epitaxial substrate for electronic devices, the method characteristically includes the steps of forming a barrier layer against impurity diffusion on one surface of a high-resistance Si-single crystal substrate, forming a buffer as an insulating layer on the other surface of the high-resistance Si-single crystal substrate, producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate, and measuring resistance of the main laminate of the epitaxial substrate without contact.
    Type: Application
    Filed: July 13, 2010
    Publication date: July 5, 2012
    Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Tetsuya Ikuta, Daisuke Hino, Ryo Sakamoto, Tomohiko Shibata
  • Publication number: 20120161155
    Abstract: A main surface of a silicon carbide substrate is inclined by an off angle in an off direction from {0001} plane of a hexagonal crystal. The main surface has such a characteristic that, among emitting regions emitting photoluminescent light having a wavelength exceeding 650 nm of the main surface caused by excitation light having higher energy than band-gap of the hexagonal silicon carbide, the number of those having a dimension of at most 15 ?m in a direction perpendicular to the off direction and a dimension in a direction parallel to the off direction not larger than a value obtained by dividing penetration length of the excitation light in the hexagonal silicon carbide by a tangent of the off angle is at most 1×104 per 1 cm2. Accordingly, reverse leakage current can be reduced.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 28, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin HARADA, Tsubasa Honke
  • Patent number: 8206996
    Abstract: A method for providing a process indicator for an etching chamber is provided. A wafer with a blanket etch layer is provided into the etching chamber. A blanket etch is performed on the blanket etch layer. A blanket deposition layer is deposited over the blanket etch layer after performing the blanket etch has been completed. A thickness of the blanket etch layer and a thickness of the blanket deposition layer is measured. The measured thicknesses are used to determine a process indicator.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: June 26, 2012
    Assignee: Lam Research Corporation
    Inventors: Keren Jacobs Kanarik, Jorge Luque, Nicholas Webb
  • Publication number: 20120153402
    Abstract: When forming sophisticated transistors requiring an embedded semiconductor alloy, the cavities may be formed with superior uniformity on the basis of, for instance, crystallographically anisotropic etch steps by providing a uniform oxide layer in order to reduce process related fluctuations or queue time variations. The uniform oxide layer may be formed on the basis of an APC control regime.
    Type: Application
    Filed: September 21, 2011
    Publication date: June 21, 2012
    Applicant: GLOBAL FOUNDRIES Inc.
    Inventors: Stephan Kronholz, Andreas Ott, Ina Ostermay
  • Publication number: 20120156811
    Abstract: A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads. In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic. In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 21, 2012
    Applicant: Advanced Inquiry Systems, Inc.
    Inventor: Morgan T. Johnson
  • Publication number: 20120156809
    Abstract: An exposure apparatus includes a light emission part 10 generating EUV light by plasma excitation of a predetermined atom, a condenser part 20 condensing the EUV light emitted from the light emission part, an exposure part 30 irradiating a substrate via a mask with the EUV light condensed by the condenser part, a first plasma position monitor 11a detecting the position of an emission point of the EUV light within the light emission part, and a light emission part drive unit 13 adjusting the position of the light emission part. The exposure apparatus determines a first shift amount between the emission point detected by the plasma position monitor and a reference light emission position, and drives the light emission part drive unit according to the first shift amount.
    Type: Application
    Filed: November 29, 2011
    Publication date: June 21, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Seiichiro SHIRAI
  • Publication number: 20120153281
    Abstract: A semiconductor target for determining a relative shift between two or more successive layers of a substrate is provided. The target comprises a plurality of first structures formed in a first layer, and the first structures have a first center of symmetry (COS). The target further comprises a plurality of second structures formed in a second layer, and the second structures have second COS. The difference between the first COS and the second COS corresponds to an overlay error between the first and second layer and wherein the first and second structures have a 180° rotational symmetry, without having a 90° rotational symmetry, with respect to the first and second COS, respectively.
    Type: Application
    Filed: February 28, 2012
    Publication date: June 21, 2012
    Applicant: KLA-TENCOR TECHNOLOGIES CORPORATION
    Inventor: Mark GHINOVKER
  • Patent number: 8202739
    Abstract: A semiconductor device is formed by implanting recess markers in a material during deposition and using the recess markers during etching of the material for precise in-situ removal rate definition and removal homogeneity-over-radius definition. An embodiment includes depositing a layer of material on a substrate, implanting first and second dopants in the material at first and second predetermined times during deposition of the material, etching the material, detecting the depths of the first and second dopants during etching, calculating the removal rate of the material in situ from the depths of the first and second dopants, and determining from the removal rate a stop position for etching.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: June 19, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dmytro Chumakov, Peter Baars
  • Publication number: 20120149136
    Abstract: In the fabrication of a semiconductor integrated circuit device, a 2D-3D inspection technique for solder printed on a substrate is provided which permits easy preparation of data and easy visual confirmation of a defective portion. In a substrate inspecting step, first, a 3D inspection is performed, followed by execution of 2D inspection, whereby a 2D picked-up image of the portion of a pad determined to be defective can be displayed on a larger scale simultaneously with the end of inspection, thereby providing an environment for efficient visual confirmation of the defect. Further, by subjecting a raw substrate to measurement at the time of preparing inspection data, a relation between an original height measurement reference generated automatically by the inspection system and the height of a pad upper surface is checked, whereby it is possible to measure the height and volume of printed solder based on the pad upper surface.
    Type: Application
    Filed: February 17, 2012
    Publication date: June 14, 2012
    Inventor: Norio WATANABE
  • Publication number: 20120146159
    Abstract: The overlay mark and method for making the same are described. In one embodiment, a semiconductor overlay structure includes gate stack structures formed on the semiconductor substrate and configured as an overlay mark, and a doped semiconductor substrate disposed on both sides of the gate stack structure that includes at least as much dopant as the semiconductor substrate adjacent to the gate stack structure in a device region. The doped semiconductor substrate is formed by at least three ion implantation steps.
    Type: Application
    Filed: November 10, 2011
    Publication date: June 14, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Cheng WANG, Ming-Chang WEN, Chun-Kuang CHEN, Yao-Ching KU
  • Publication number: 20120150478
    Abstract: In a method of testing an object, a first test pattern for testing a first device in the object may be set in a tester. A second test pattern for testing a second device in the object may be set in a test head electrically connected between the tester and the object. The first test pattern may be provided to the first device through the test head and the second test pattern may be provided to the second device by the test head to simultaneously test the first device and the second device. Thus, the first device and the second device different from each other may be simultaneously tested without changing test conditions in the tester, so that a time for testing the object may be reduced.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 14, 2012
    Inventors: Ki-Jae Song, Sung-Soo Lee
  • Publication number: 20120149137
    Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.
    Type: Application
    Filed: February 17, 2012
    Publication date: June 14, 2012
    Applicant: Intermolecular, Inc
    Inventors: Gaurav Verma, Kurt Weiner, Prashant Phatak, Imran Hashim, Sandra Malhotra, Tony Chiang
  • Publication number: 20120149135
    Abstract: A semiconductor device manufacturing method includes: forming a first pattern in a first film to be processed on a semiconductor substrate; measuring a first distance, which is a dimension in a predetermined direction in the first pattern; forming a second film to be processed on the first pattern; forming a second pattern in a photoresist formed on the second film to be processed; and measuring a second distance, which is a dimension in a predetermined direction in the second pattern. Whether or not the second pattern is defective is determined based on either the first distance or a value calculated from the first and second distances.
    Type: Application
    Filed: December 5, 2011
    Publication date: June 14, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Takashi SUGIMURA, Shinji YANAGI
  • Patent number: 8198688
    Abstract: Latchup is prevented from occurring accompanying increasingly finer geometries of a chip. NchMOSFET N1 and PchMOSFET P1 form a CMOS circuit including: NchMOSFET N2 whose gate, drain and back gate are connected to back gate of N1 and PchMOSFET P2 whose gate, drain and back gate are connected to back gate of P1. Source of N2 is connected to source of N1. Source of P2 is connected to source of P1. N2 is always connected between the grounded source of N1 and the back gate of N1, while P2 is connected between source of P1 connected to a power supply and the back gate of P1. Each of N2 and P2 functions as a voltage limiting element (a limiter circuit).
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: June 12, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Mototsugu Okushima
  • Publication number: 20120138924
    Abstract: According to an embodiment, a method for measuring an impurity concentration profile uses a wafer including a semiconductor layer. The method includes measuring an impurity concentration profile in a depth direction from each surface of a plurality of first portions, each of the first portions being included in any one of a plurality of first regions provided in the semiconductor layer. Each of the first regions has a different size and is surrounded by a second region including a second portion having a different structure from the first portion. The method includes determining a change between the impurity concentration profiles measured in the first regions.
    Type: Application
    Filed: September 1, 2011
    Publication date: June 7, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kazuya NISHIHORI
  • Patent number: 8193648
    Abstract: An integrated alignment and overlay mark for detecting the exposed errors of the photolithography process between a pre-layer and a current layer is disclosed. The integrated alignment and overlay mark includes an alignment mark and an overlay mark in the same shot region. The alignment mark is formed surrounding the overlay mark; therefore, the gap or the orientation between the pre-layer and the current layer can be calculated in order to check the alignment accuracy of photolithography process.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: June 5, 2012
    Assignee: Inotera Memories, Inc.
    Inventors: Yuan Ku Lan, Chung-Yuan Lee
  • Patent number: 8193008
    Abstract: A method of forming a semiconductor thin film includes the steps of: forming an amorphous semiconductor thin film on a substrate; forming a crystalline semiconductor thin film partially in each element region by applying laser light to the amorphous semiconductor thin film to selectively perform a heating process on the amorphous semiconductor thin film, thereby crystallizing the amorphous semiconductor thin film in a region irradiated with the laser light; and inspecting the crystallinity degree of the crystalline semiconductor thin film. The step of inspecting includes the steps of determining a contrast between the luminance of a crystallized region and the luminance of a non-crystallized region by applying light to the crystalline semiconductor thin film and the amorphous semiconductor thin film, and performing screening of the crystalline semiconductor thin film on the basis of the determined contrast.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: June 5, 2012
    Assignee: Sony Corporation
    Inventors: Nobuhiko Umezu, Koichi Tsukihara, Hirohisa Amago, Go Matsunobu, Katsuya Shirai
  • Patent number: 8193061
    Abstract: This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: June 5, 2012
    Assignee: Alpha & Omega Semiconductor Incorporated
    Inventors: Yu Wang, Tiesheng Li, Sung-Shan Tai, Hong Chang
  • Publication number: 20120135549
    Abstract: Polishing a nitride semiconductor monocrystalline wafer leaves it with a process-transformed layer. The process-transformed layer has to be etched to be removed. The chemical inertness of nitride semiconductor materials has, however, precluded suitable etching. Although potassium hydroxide, for example, or sulfuric acid have been proposed as GaN etchants, their ability to corrosively remove material from the Ga face is weak. Dry etching utilizing a halogen plasma is carried out in order to remove the process-transformed layer. The Ga face can be etched off with the halogen plasma. Nevertheless, owing to the dry etching, a problem arises again—surface contamination due to metal particles. To address the problem, wet etching with, as the etchant, solutions such as HF+H2O2, H2SO4+H2O2, HCl+H2O2, or HNO3, which are nonselective for Ga/N faces, have metal etching capability, and have an oxidation-reduction potential of 1.2 V or more, is performed.
    Type: Application
    Filed: February 6, 2012
    Publication date: May 31, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Masahiro Nakayama, Naoki Matsumoto
  • Publication number: 20120136601
    Abstract: A method and system includes a first substrate and a second substrate, each substrate comprising a predetermined baseline transmittance value at a predetermine wavelength of light, processing regions on the first substrate by combinatorially varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production, performing a first characterization test on the processed regions on the first substrate to generate first results, processing regions on a second substrate in a combinatorial manner by varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production based on the first results of the first characterization test, performing a second characterization test on the processed regions on the second substrate to generate second results, and determining whether at least one of the first substrate and the second substrate meet a predetermined quality threshold based on the second res
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Inventors: Charlene Chen, Tony P. Chiang, Chi-I Lang, Yun Wang
  • Publication number: 20120135546
    Abstract: The present disclosure relates to the field of microelectronic substrate fabrication and, more particularly, to alignment inspection for vias formed in the microelectronic substrates. The alignment inspection may be achieved by determining the relative positions of fluorescing and non-fluorescing elements in a microelectronic substrate.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Inventors: Zhihua Zou, Liang William Zhang, Sheng Li, Tamil Selvy Selvamuniandy
  • Publication number: 20120135547
    Abstract: A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.
    Type: Application
    Filed: February 9, 2011
    Publication date: May 31, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ming-Che Hsieh, John H. Lau, Ra-Min Tain
  • Patent number: RE43652
    Abstract: In a substrate processing control method, a first process acquires a first-reflectance-spectrum of a beam reflected from the first-fine-structure and a second-reflectance-spectrum of a beam reflected from the second-fine-structure for each of varying-pattern-dimensions of the first-fine-structure when the pattern-dimension of the first-fine-structure is varied. A second process acquires reference-spectrum-data for each of the varying-pattern-dimensions of the first-fine-structure by overlapping the first-reflectance-spectrum with the second-reflectance-spectrum. A third process actually measures beams reflected from the first and the second-fine-structure, respectively, after irradiating light beam on to the substrate and acquiring reflectance-spectrums of the actual-measured beams as actual-measured spectrum data.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: September 11, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Susumu Saito, Akitaka Shimizu