Abstract: Techniques for processing power transistor devices are provided. In one aspect, the curvature of a power transistor device comprising a device film formed on a substrate is controlled by thinning the substrate, the device having an overall residual stress attributable at least in part to the thinning step, and applying a stress compensation layer to a surface of the device film, the stress compensation layer having a tensile stress sufficient to counterbalance at least a portion of the overall residual stress of the device. The resultant power transistor device may be part of an integrated circuit.

Abstract: A template inspection method for performing defect inspection of a template, by bringing a pattern formation surface of a template used to form a pattern close to a first fluid coated on a flat substrate, filling the first fluid into a pattern of the template, and by performing optical observation of the template in a state that the first fluid is sandwiched between the template and the substrate, wherein a difference between an optical constant of the first fluid and an optical constant of the template is larger than a difference between an optical constant of air and the optical constant of the template.

Abstract: [Problems] To provide a semiconductor wafer processing apparatus and reference angular position detection method able to suitably detect a reference angular position for a semiconductor wafer for which a reference angular position is set and a semiconductor wafer for which a reference angular position is suitably set. [Means for Solving Problems] A semiconductor wafer (100) is formed at part of an outer circumference edge part (101) with a crystal orientation detection flat surface (102) vertical to the diametrical direction at a position forming a predetermined angle with the crystal orientation.

Abstract: A system of testing semiconductor devices includes a classification module configured to classify a plurality of lots into a plurality of groups; an apparatus assignment module configured to assign a plurality of testing apparatuses to each of the groups; and a test recipe creation module configured to create a test recipe to test defects in a second group other than a first group specified in the groups, the test recipe including a definition of testing positions in the second group defined by a rule different from the first group.

Abstract: According to an exemplary embodiment, a method for site-specific trimming of a wafer to provide a target parameter value for a plurality of devices on the wafer includes performing a first measurement of a parameter at a subset of the number of devices on the wafer. The method further includes forming a top layer over the wafer after performing the first measurement. The method further includes performing a second measurement of the parameter at the subset of the devices on the wafer after forming the top layer. The method further includes determining an amount of the top layer to remove across the wafer to provide the target parameter value for the devices by utilizing the first and second measurements of the parameter. The method can be utilized to, for example, achieve a more uniform characteristic frequency for bulk acoustic wave (BAW) filters.

Abstract: A method of evaluating damage of a compound semiconductor member, comprising: a step of performing spectroscopic ellipsometry measurement on a surface of the compound semiconductor member; and a step of evaluating damage on the surface of the compound semiconductor member, using a spectrum in a wavelength band containing a wavelength corresponding to a bandgap of the compound semiconductor member, in a spectrum of an optical constant obtained by the spectroscopic ellipsometry measurement.

Abstract: A method for the protection of the information in a multi-project wafer (MPW) is provided. First, a substrate is provided. There are a first die and a second die on the substrate. Second, a first wafer process is performed on the substrate. The first wafer process includes performing a wafer procedure by using a non-destructive energy source and destroying the first die by using a destructive energy source. Later, a second wafer process is performed to finish the second die.

Abstract: An object of the present invention is to improve use efficiency of a semiconductor substrate without lowering efficiency of a fabrication process. Another object of the present invention is to achieve cost reduction by effective use of a semiconductor substrate whose thickness is reduced due to repeated use in a process of manufacturing an SOI substrate. In a process of manufacturing an SOI substrate, a semiconductor substrate is used as a bond substrate a predetermined number of times, or as long as it meets predetermined conditions. In a case where a first single crystal semiconductor substrate cannot be used as a bond substrate, it is bonded to a second single crystal semiconductor substrate. Then, a stacked-layer substrate formed from the first single crystal semiconductor substrate and the second single crystal semiconductor substrate bonded to each other is used as a bond substrate in a process of manufacturing an SOI substrate.

Abstract: One embodiment of the present invention sets forth a computer-implemented method for tuning laser scribe parameters during the fabrication of a solar module. The method includes analyzing the visual appearance of a laser scribe to extract various morphological parameters related to the quality of a laser scribe process used to produce the scribe. Based on the morphological parameters, the laser scribe parameters may be modified in-situ to achieve settings that are optimal for performing laser scribing in each layer of the solar module. As a result, laser scribe process cycle time may be minimized while providing better indication of the laser scribe process stability and quality relative to the prior art approaches.

Abstract: A side of a correction target pattern is divided into a plurality of segments. A space between each of the divided segments or an imaginary segment extended from both the ends of the segment to outer sides and a side of an adjacent pattern adjacent to the segment is measured. An overlapping distance between each of the divided segments or the imaginary segment extended from both the ends of the segment to the outer sides and the side of the adjacent pattern is measured. A shift amount of the segment is corrected based on the overlapping distance.

Abstract: A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.

Abstract: A silicon processing method includes: forming a mask pattern on a principal plane of a single-crystal silicon substrate; and applying crystal anisotropic etching to the principal surface to form a structure including a (111) surface and a crystal surface equivalent thereto and having width W1 and length L1. The principal plane includes a (100) surface and a crystal surface equivalent thereto or a (110) surface and a crystal surface equivalent thereto. A determining section for determining the width W1 of the structure is formed in the mask pattern. The width of the determining section for the width W1 of the mask pattern is width W2. The width of the mask pattern other than the determining section is larger than the width W2 over a length direction of the mask pattern.

Abstract: Measuring the amount of unreacted polysilicon gate material in a fully silicided (FUSI) nickel silicide gate process for metal oxide semiconductor (MOS) transistors in an integrated circuit (IC) to guide process development and monitor IC production requires a statistically significant sample size and an economical procedure. A method is disclosed which includes a novel deprocessing sequence of oxidizing the nickel followed by removing the nickel silicide by acid etching, acquiring an SEM image of a deprocessed area encompassing a multitude of gates, forming a quantifiable mask of the original gate area in the SEM image, forming a quantifiable image of the unreacted polysilicon area in the SEM image, and computing a fraction of unreacted polysilicon.

Abstract: A lead frame is provided that includes a base metal, a plated layer provided on a part of the surface of the base metal, and a thermal history monitor portion that discolors under heat load applied thereto, provided at another part of the base metal surface. A method of manufacturing a semiconductor device includes an assembly process including mounting a semiconductor chip on the lead frame, performing a wire bonding process thereby connecting the semiconductor chip and the lead frame, and encapsulating with a resin the wire-bonded semiconductor chip and the lead frame, and then performing an appearance check after the assembly process to inspect whether the thermal history monitor portion has discolored under heat load applied through the assembly process, thereby deciding whether an abnormality has emerged through the thermal history.

Abstract: A film thickness prediction method of predicting a film thickness of a second processed layer after planarization includes the steps of: creating first to third actual measurement databases; obtaining a reference film thickness of a second processed layer formed on a region in which no circuit pattern exists; segmenting a first processed layer to be formed on a substrate into grid-like meshes, and obtaining a pattern area ratio occupied by a circuit pattern to be formed on a first processed layer in each mesh and further obtaining a circumferential length of the circuit pattern in each mesh; obtaining an initial thickness of the second processed layer in each mesh; and predicting the film thickness of the second processed layer after planarization from an initial film thickness predicted value and an amount of planarization Hij of the second processed layer in the mesh.

Abstract: In a substrate processing control method, a first process acquires a first-reflectance-spectrum of a beam reflected from the first-fine-structure and a second-reflectance-spectrum of a beam reflected from the second-fine-structure for each of varying-pattern-dimensions of the first-fine-structure when the pattern-dimension of the first-fine-structure is varied. A second process acquires reference-spectrum-data for each of the varying-pattern-dimensions of the first-fine-structure by overlapping the first-reflectance-spectrum with the second-reflectance-spectrum. A third process actually measures beams reflected from the first and the second-fine-structure, respectively, after irradiating light beam on to the substrate and acquiring reflectance-spectrums of the actual-measured beams as actual-measured spectrum data.

Abstract: A surface emitting laser configured by laminating on a substrate a lower reflection mirror, an active layer and an upper reflection mirror includes, in a light emitting section of the upper reflection mirror, a structure for controlling reflectance that is configured by a low reflectance region and a convex high reflectance region formed in the central portion of the low reflectance region, and which oscillates at a wavelength of ?, wherein the upper reflection mirror is configured by a multilayer film reflection mirror based on a laminated structure formed by laminating a plurality of layers, and an absorption layer causing band-to-band absorption is provided in the laminated structure.

Abstract: A surface emitting laser which is configured by laminating on a substrate a lower reflection mirror, an active layer, and an upper reflection mirror, which includes, in a light emitting section of the upper reflection mirror, a structure for controlling reflectance that is configured by a low reflectance region and a concave high reflectance region formed in the central portion of the low reflectance region, and which oscillates at a wavelength of ?, wherein the upper reflection mirror is configured by a multilayer film reflection mirror based on a laminated structure formed by laminating a plurality of layers, the multilayer film reflection mirror includes a phase adjusting layer which has an optical thickness in the range of ?/8 to 3?/8 inclusive in a light emitting peripheral portion on the multilayer film reflection mirror, and an absorption layer causing band-to-band absorption is provided in the phase adjusting layer.

Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

Abstract: A blank wafer is placed in an etch chamber. A layer is deposited over the blank wafer, comprising providing a deposition gas, forming the deposition gas into a deposition plasma, and stopping the deposition gas. The blank wafer with the deposited layer is removed from the etch chamber. The thickness of the deposited layer is measured. Wafer temperature accuracy is calculated from the measured thickness of the deposited layer. The etch chamber is compensated according to the calculated wafer temperature accuracy. A wafer with an etch layer over the wafer and a patterned mask over the etch layer is placed into the etch chamber. The etch layer is etched in the etch chamber.

Abstract: According to an aspect of the present invention, there is provided a template including: a template substrate; patterns for forming device patterns on a wafer substrate; and a charging monitoring pattern, a size of the charging monitoring pattern being equal to a largest pattern in the patterns for forming the device patterns.

Abstract: There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of semiconductor chips, resin layers which are disposed on surfaces of the semiconductor chips in which the electrode pads are formed and expose the internal connection terminals, and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals, a wiring substrate on which the plurality of semiconductor apparatuses are stepwise stacked, the wiring substrate electrically connected to the plurality of semiconductor apparatuses, and a sealing resin with which the plurality of semiconductor apparatuses are sealed.

Abstract: A method for fabricating a CMOS image sensor includes developing a semiconductor substrate provided with metal pads with tetramethylammonium hydroxide (TMAH), to etch the metal pads. In accordance with the method, it is possible to realize normal output of materials, which were previously scrapped due to problems including pad corrosion, appearance defects and bonding pad issues which may occur in the process of fabricating CMOS image sensors. As a result, advantageously, it is possible to reduce wafer scrap and improve product yield.

Abstract: A method of monitoring a heat treatment of a microtechnological substrate includes placement of the substrate to be treated in a heating zone and applying a heat treatment to the substrate, under predetermined temperature conditions, while monitoring the change over the course of time in the vibratory state of the substrate, and detecting a fracture in the substrate by detecting a peak characteristic in the vibratory state over the course of time.

Abstract: In an optical pulse generating apparatus including a metal layer having an incident/reflective surface adapted to receive incident light and output its reflective light as an optical pulse signal, a dielectric layer formed on an opposite surface of the metal layer opposing the incident/reflective surface, and a dielectric layer exciting unit for exciting the dielectric layer on a time basis, the incident light exciting surface plasmon resonance light in the metal layer while the dielectric layer is excited on a time basis, so that an extinction coefficient of the dielectric layer is made negative.

Abstract: Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer over the blocking layer; and inspecting optically at least one wavelength at least one inspection area, the blocking layer extending substantially throughout the inspection area. An inspection method including adhering an optical absorbing layer to a semiconductor process wafer, where the absorbing layer is configured to substantially absorb a range of wavelengths of light; applying at least one layer over the absorbing layer; and inspecting optically at least one wavelength at least one inspection area of the process wafer. A manufacturing method including ascertaining if a defect is present within a photoresist layer, and changing a semiconductor manufacturing process to prevent the defect, if the defect is present.

Abstract: A method of manufacturing a semiconductor device includes: forming a groove portion in a dicing region of an insulating layer and forming a via hole in an internal circuit formation region; providing a first resist film on the insulating layer; providing a second resist film to cover the first resist film; forming an interconnect opening in a region covering an internal circuit formation region of the second resist film and forming a position aligning opening in a region covering the dicing region of the second resist film; and detecting a positional relationship between the groove portion and the position aligning opening so as to detect whether the interconnect opening of the second resist film exists at a predetermined position with respect to the via hole of the insulating layer. In selective removing of the second resist film, the position aligning opening is formed such that a region of the position aligning opening covers the groove portion of the insulating layer.

Abstract: The invention relates to the fabrication of integrated circuits in general, and notably the circuits of image sensors intended to form the electronic core of photographic apparatus or cameras. The chip is first aligned with respect to the package and then the package is aligned with respect to the optical system. The alignment of the chip with respect to the package is done optically. The alignment of the package with respect to the system is done mechanically with respect to the edges of the package. According to the invention, provision is made for optical marks to be provided on the package, these marks each having an edge aligned with a lateral edge of the package, so as to minimize the positioning errors which would be due to inaccurate positioning of the chip with respect to the edges of the package.

Abstract: Disclosed is a method involving repeatedly measuring a pressure within a flow of processing gas that is provided in a semiconductor processing apparatus for treatment of a semiconductor substrate, such as a semiconductor wafer. The flow of processing gas is made to extend between a surface of the substrate and a surface of a processing body. From the pressure measurements the occurrence of an event that is related to a variation in the position of the substrate's surface relative to the surface of the processing body is determined.

Abstract: Dicing lines extending longitudinally and transversely, and chip areas surrounded by the dicing lines are formed in a resist mask. Critical-dimension patterns are formed in the dicing lines so as to be paired while placing the center line thereof in between. The dimensional measurement of the resist film having these patterns formed therein is made under a CD-SEM, by specifying a measurement-target chip area out of a plurality of chip areas, and by specifying a position of a critical-dimension pattern on the left thereof. Then, the distance of two linear portions configuring the critical-dimension pattern is measured, wherein a portion at a point of measurement on the measurement-target chip area side as viewed from the center line of the dicing line is measured.

Abstract: A method is provided for laser optically marking integrated circuit (IC) packages in a non-destructive manner. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. An acute angle is defined between a laser optical path and an IC package planar surface. The IC package surface is scanned with a laser, and in response to ablating the IC package surface, a legible mark on the planar surface.

Abstract: Apparatus and method for manufacturing a semiconductor device through a layer material dimension analysis increase productivity. The method includes performing a semiconductor manufacturing process of at least one reference substrate and at least one target substrate in a semiconductor process device, detecting a reference spectrum and a reference profile for the reference substrate, determining a relation function between the detected reference spectrum and reference profile, detecting a real-time spectrum of the target substrate, and determining in real time a real-time profile of the target substrate processed in the semiconductor process device by using the detected real-time spectrum as a variable in the determined relation function.

Abstract: A semiconductor substrate includes a wafer, a first stepped structure formed of plural stepped parts formed on a surface of the wafer with a first area occupation ratio, a second stepped structure formed of plural stepped parts formed on the surface of the wafer with a second, different area occupation ratio, and an interlayer insulation film formed on the surface so as to cover the first and second stepped structures, the interlayer insulation film having a planarized top surface, wherein there are provided at least first and second film-thickness monitoring patterns for monitoring film thickness on the surface in a manner covered by the interlayer insulation film, a first pattern group is formed on the surface such that the first pattern group comprises plural patterns disposed so as to surround the first film-thickness monitoring pattern, a second pattern group is formed on the surface such that the second pattern group comprises plural patterns disposed so as to surround the second film-thickness monitori

Abstract: By using powerful data analysis techniques, such as PCR, PLS, CLS and the like, in combination with measurement techniques providing structural information, gradually varying material characteristics may be determined during semiconductor fabrication, thereby also enabling the monitoring of complex manufacturing sequences. For instance, the material characteristics of sensitive dielectric materials, such as ULK material, may be detected, for instance with respect to an extension of a damage zone, in order to monitor the quality of metallization systems of sophisticated semiconductor devices. The inline measurement data may be obtained on the basis of infrared spectroscopy, for instance using FTIR and the like, which may even allow directly obtaining the measurement data at process chambers, substantially without affecting the overall process throughput.

Abstract: A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data; and fabricating an integrated circuit from the reticle data.

Abstract: A semiconductor wafer is produced by a method comprising a slicing step, an one-side polishing step and a chemical treating step, in which the kerf loss is reduced and the flatness is improved.

Abstract: This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

Abstract: A virtual measuring device and a method for measuring the deposition thickness of amorphous silicon being deposited on a substrate is disclosed, where the method of measuring the deposition thickness of amorphous silicon includes predicting and adapting operations. In the predicting operation, during a process of depositing the amorphous silicon to a substrate, the deposition thickness is predicted by multiplying a predicted deposition speed to a deposition time by using a prediction model expressing a relationship between a deposition speed and a plurality of process factors that are correlated with the deposition speed obtained from the deposition thickness and the deposition time, and the predicted deposition thickness is compared with the measured deposition thickness, so that the relationship between the plurality of process factors and the deposition speed in the prediction model is compensated according to the comparison difference.

Abstract: A method of measuring LED junction temperature includes the steps of: (a) obtaining a temperature curve of an LED; (b) inputting at least one rated AC voltage to the LED; (c) measuring a temperature at a specific point on an outer packaging structure of the LED, putting the temperature measured at the specific point into the temperature curve, and calculating a junction temperature of the LED by interpolation; and (d) substituting the result from the calculation in the step (c) into a numerical analysis model to obtain temperature oscillation of the LED.

Abstract: Embodiments of the present invention provide an apparatus and method for processing substrates using a multiple screen printing chamber processing system that has an increased system throughput, improved system uptime, and improved device yield performance, while maintaining a repeatable and accurate screen printing process on the processed substrates. In one embodiment, the multiple screen printing chamber processing system is adapted to perform a screen printing process within a portion of a crystalline silicon solar cell production line in which a substrate is patterned with a desired material, and then processed in one or more subsequent processing chambers.

Abstract: A semiconductor laser device manufacturing method includes, sequentially, a first aging step S1, a first inspection step S2, a mounting step S3, a second aging step S4 and a second inspection step S5. Since the first aging step S1 on a semiconductor laser chip with a high-temperature direct current conduction is performed before the mounting step S3, threshold current and drive current of the semiconductor laser chip before mounting can be reduced.

Abstract: The invention relates to a method for bonding wafers along their corresponding surfaces.

Abstract: An overlapping margin of a second pattern for a first pattern is corrected for at least one of the first pattern and the second pattern (S50). Next, a relative distance between the first pattern and the second pattern after the overlapping margin is corrected is calculated (S60). Next, it is determined whether or not the relative distance satisfies a criterion (S70). Thus, the pattern can be verified under the consideration of the overlapping margin.

Abstract: A method of forming a semiconductor thin film includes: a step of forming an amorphous semiconductor thin film over a transparent substrate; a step of forming a crystalline semiconductor thin film by irradiating the amorphous semiconductor thin film with laser light to provide heat treatment and thereby crystallizing the amorphous semiconductor thin film; and an inspection step of inspecting the crystalline semiconductor thin film. The inspection step includes a step of obtaining a transmission image of the crystalline semiconductor thin film by irradiating the crystalline semiconductor thin film with light from a rear side of the transparent substrate and taking an image, and a screening step of performing screening of the crystalline semiconductor thin film based on the obtained transmission image.

Abstract: A method of forming a semiconductor thin film includes the steps of: forming an amorphous semiconductor thin film on a substrate; forming a crystalline semiconductor thin film partially in each element region by applying laser light to the amorphous semiconductor thin film to selectively perform a heating process on the amorphous semiconductor thin film, thereby crystallizing the amorphous semiconductor thin film in a region irradiated with the laser light; and inspecting the crystallinity degree of the crystalline semiconductor thin film. The step of inspecting includes the steps of determining a contrast between the luminance of a crystallized region and the luminance of a non-crystallized region by applying light to the crystalline semiconductor thin film and the amorphous semiconductor thin film, and performing screening of the crystalline semiconductor thin film on the basis of the determined contrast.

Abstract: An overlay mark for determining the relative shift between two or more successive layers of a substrate and methods for using such overlay mark are disclosed. In one embodiment, the overlay mark includes at least one test pattern for determining the relative shift between a first and a second layer of the substrate in a first direction. The test pattern includes a first set of working zones and a second set of working zones. The first set of working zones are disposed on a first layer of the substrate and have at least two working zones diagonally opposed and spatially offset relative to one another. The second set of working zones are disposed on a second layer of the substrate and have at least two working zones diagonally opposed and spatially offset relative to one another. The first set of working zones are generally angled relative to the second set of working zones thus forming an “X” shaped test pattern.

Abstract: Information on a transfer pattern created from a design pattern corresponding to a pattern to be formed on a substrate is acquired as pattern transfer information. The design pattern is compared with the transfer pattern and, on the basis of the feature quantity obtained from the comparison, the pattern transfer information and the design pattern are classified. A threshold value is set for the feature quantity and, on the basis of the threshold value, the pattern transfer information and the design pattern are further classified. Then, verification is conducted to see if the transfer pattern satisfies the threshold value.

Abstract: Process control monitors are disclosed that are produced using at least some of the same process steps used to manufacture a MEMS device. Analysis of the process control monitors can provide information regarding properties of the MEMS device and components or sub-components in the device. This information can be used to identify errors in processing or to optimize the MEMS device. In some embodiments, analysis of the process control monitors may utilize optical measurements.

Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.

Abstract: A method that includes forming a gate of a semiconductor device on a substrate and forming a recess for an embedded silicon-straining material in source and drain regions for the gate. In this method, a proximity value, which is defined as a distance between the gate and a closest edge of the recess, is controlled by controlling formation of an oxide layer provided beneath the gate. The method can also include feedforward control of process steps in the formation of the recess based upon values measured during the formation of the recess. The method can also apply feedback control to adjust a subsequent recess formation process performed on a subsequent semiconductor device based on the comparison between a measured proximity value and a target proximity value to decrease a difference between a proximity value of the subsequent semiconductor device and the target proximity value.