Abstract: Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.

Abstract: In a method for measuring an amount of strain of a bonded strained wafer, at least one strained layer is formed on a single crystal substrate. The bonded strained wafer is measured with respect to two asymmetric diffraction planes with diffraction plane indices (XYZ) and (?X?YZ) by an X-ray diffraction method, a reciprocal lattice space map is created from the measured data, and the amount of strain of the strained layer is calculated from the peak positions for the respective diffraction planes of the single crystal substrate and the strained layer appearing on the reciprocal lattice space map. Thereby, amounts of strain in the horizontal direction and in the vertical direction of the strained layer can be measured in a shorter time and more simply.

Abstract: A semiconductor device manufacturing method and a semiconductor device manufacturing apparatus which enable to detect an etching end-point with high accuracy are provided. In etching of a lower layer formed on a semiconductor wafer using a mask which comprises a plurality of patterns extending in a predetermined direction (line-and-space patterns) and contains at least one of a metal layer and an electrically-conductive metal compound layer, the surface of the semiconductor wafer is irradiated with inspection light, the etching is performed while monitoring the intensity of the polarized light component perpendicular to the predetermined extending direction of the line-and-space patterns and the etching is terminated at the time the intensity of the polarized light component reaches a reflected light intensity corresponding to a desired remaining thickness of the lower layer.

Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

Abstract: The invention relates to a method for picking up semiconductor chips from a wafer table and, optionally, their mounting on a substrate by means of a pick-and-place system. The position and orientation of the semiconductor chip to be mounted next are determined by means of a first camera and made available in the form of positional data relating to a first system of coordinates. The position and orientation of the substrate place on which the semiconductor chip will be mounted are determined by means of a second camera and made available in the form of positional data relating to a second system of coordinates. The conversion of coordinates of the first or second system of coordinates into coordinates of motion of the pick-and-place system occurs by means of two fixed mapping functions and two changeable correction vectors. The correction vectors are readjusted on the occurrence of a predetermined event.

Abstract: Exemplary embodiments provide methods for implementing an ultra-high temperature (UHT) anneal on silicon germanium (SiGe) semiconductor materials by co-implanting carbon into the SiGe material prior to the UHT anneal. Specifically, the carbon implantation can be employed to increase the melting point of the SiGe material such that an ultra high temperature can be used for the subsequent anneal process. Wafer warpage can then be reduced during the UHT anneal process and potential lithographic mis-alignment for subsequent processes can be reduced. Exemplary embodiments further provide an inline control method, wherein the wafer warpage can be measured to determine the litho-mis-alignment and thus to control the fabrication process. In various embodiments, the disclosed methods can be employed for the fabrication of source/drain extension regions and/or source/drain regions of transistor devices, and/or for the fabrication of base regions of bipolar transistors.

Abstract: A composite of two or more thermal interface materials (“TIMs”) is placed between a die and a heat spreader to improve cooling of the die in an integrated circuit package. The two or more TIMs vary in heat-dissipation capability depending upon the locations of die hot spots. In an embodiment, a more thermally conductive material may be positioned over one or more die hot spots, and a less thermally conductive material may be positioned abutting and/or surrounding the more thermally conductive material. The two or more TIMs may comprise a solder and a polymer. The composite TIM may be preformed as one unit or as a plurality of units. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: A thermal treatment apparatus having a first light source emitting a first light having light diffusion property, a reflectance measuring unit irradiating a treatment target with the light from plural directions by the first light source and determining a light reflectance of the treatment target, a light irradiation controller adjusting an intensity of a second light of a second light source on the basis of the light reflectance, the second light has diffusion property, and a thermal treatment unit irradiating the treatment target with the second light having adjusted the intensity of the second light by the light irradiation controller.

Abstract: A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in an inert atmosphere; (c) submerging, for a present duration of time, the substrate into an aqueous solution, the aqueous solution to be monitored for copper contamination; and (d) determining an amount of copper adsorbed from the aqueous solution by the region of the substrate.

Abstract: A defect inspecting apparatus comprising: an inspection region dividing section which divides a defect inspection region of a wafer on which a circuit pattern is formed into a plurality of inspection subregions; a pattern density calculating section which calculates the pattern density of each of the inspection subregions on the basis of design data of the circuit pattern; an inspection execution region and sensitivity rank setting section which assigns a sensitivity rank based on the pattern density to a plurality of inspection execution regions, each including a plurality of the inspection subregions; and a defect inspecting section which sets an inspection parameter on the basis of sensitivity ranks of the inspection execution regions and inspects the inspection execution regions for a defect.

Abstract: An integrated manufacturing system comprising: providing a substrate; forming a gate over the substrate; measuring a gate length of the gate; forming a first spacer adjacent the gate; measuring a spacer critical dimension of the spacer; and adjusting a dose of an implant based on the gate length and the spacer critical dimension for a source/drain region.

Abstract: The present invention is a production method for a semiconductor device equipped with a conductive film with predetermined film thickness on a sidewall of a concave portion formed in an insulating film, and comprises a step of forming the concave portion in the insulation film formed on a semiconductor substrate. Herein, the concave portion is a generic name of a via-hole and a trench. This production method comprises a step of forming a conductive film with film thickness, which is film thickness of a conductive film to be formed in the concave portion, and which is film thickness, calculated based upon the depth of the concave portion and a projected area of the sidewall of said concave portion when viewing the concave portion from the upper surface, and to be formed over the upper surface of the insulating film where the concave portion is formed. In other words, a film is formed taking the variation of configuration of these based upon a projected area of a via-hole or a trench into consideration.

Abstract: The present invention generally provides method and apparatus for non-contact temperature measurement in a semiconductor processing chamber. Particularly, the present invention provides methods and apparatus for non-contact temperature measurement for temperature below 500° C. One embodiment of the present invention provides an apparatus for processing semiconductor substrates. The apparatus comprises a target component comprises a material with higher emissivity than the one or more substrates.

Abstract: A method and system for reducing the variation in film thickness on a plurality of semiconductor wafers having multiple deposition paths in a semiconductor manufacturing process is disclosed. A film of a varying input thickness is applied to semiconductor wafers moving through various film deposition paths. The deposition path of each of the semiconductor wafers is recorded. A subset of semiconductor wafers is measured and an average film input thickness corresponding to each of the film deposition paths is calculated. If semiconductor wafer in the specific film deposition path does not have measurement data, by default it uses historical measurement data. The average film input thickness of the deposition path corresponding to a given semiconductor wafer is then used to modify the recipe of a process tool, such as a Chemical Mechanical Planarization (CMP) Process Tool. An improved manufacturing process is achieved without the use of excess measurements.

Abstract: The present invention relates to monitoring chemicals in a process chamber using a spectrometer having a plasma generator, based on patterns over time of chemical consumption. The relevant patterns may include a change in consumption, reaching a consumption plateau, absence of consumption, or presence of consumption. In some embodiments, advancing to a next step in forming structures on the workpiece depends on the pattern of consumption meeting a process criteria. In other embodiments, a processing time standard is established, based on analysis of the relevant patterns. Yet other embodiments relate to controlling work on a workpiece, based on analysis of the relevant patterns. The invention may be either a process or a device including logic and resources to carry out a process.

Abstract: Exemplary embodiments provide an infrared (IR) retinal system and method for making and using the IR retinal system. The IR retinal system can include adaptive sensor elements, whose properties including, e.g., spectral response, signal-to-noise ratio, polarization, or amplitude can be tailored at pixel level by changing the applied bias voltage across the detector. “Color” imagery can be obtained from the IR retinal system by using a single focal plane array. The IR sensor elements can be spectrally, spatially and temporally adaptive using quantum-confined transitions in nanoscale quantum dots. The IR sensor elements can be used as building blocks of an infrared retina, similar to cones of human retina, and can be designed to work in the long-wave infrared portion of the electromagnetic spectrum ranging from about 8 ?m to about 12 ?m as well as the mid-wave portion ranging from about 3 ?m to about 5 ?m.

Abstract: A microelectronic device and a method for producing the device can overcome the disadvantages of known electronic devices composed of carbon molecules, and can deliver performance superior to the known devices. An insulated-gate field-effect transistor includes a multi-walled carbon nanotube (10) having an outer semiconductive carbon nanotube layer (1) and an inner metallic carbon nanotube layer (2) that is partially covered by the outer semiconductive carbon nanotube layer (1). A metal source electrode (3) and a metal drain electrode (5) are brought into contact with both ends of the semiconductive carbon nanotube layer (1) while a metal gate electrode (4) is brought into contact with the metallic carbon nanotube layer (2). The space between the semiconductive carbon nanotube layer (1) and the metallic carbon nanotube layer (2) is used as a gate insulating layer.

Abstract: Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying a measurement structure for performing the test; implementing the measurement structure on the multiple chip wafer using a reticle including the measurement structure between copies of the multiple chips on the reticle, wherein no one of the multiple chips covers an entirety of the reticle; performing the test on the multiple chip wafer using the measurement structure to acquire data across the reticle; using data from the performing to establish an across reticle variation model; and using the across reticle variation model to predict across chip variation for at least one of the multiple chips.

Abstract: A non-destructive and simple analytical method is provided which allows in situ monitoring of plasma damage during the plasma processing such as resist stripping. If a low-k film is damaged during plasma processing, one of the reaction products is water, which is remained adsorbed onto the low-k film (into pores), if the temperature is lower than 100-150 C. A plasma (e.g. He) that emits high energy EUV photons (E>20 eV) which is able to destruct water molecules forming electronically excited oxygen atoms is used to detect the adsorbed water. The excited oxygen is detected from optical emission at 777 nm. Therefore, the higher the adsorbed water concentration (higher damage), a more intensive (oxygen) signal is detected. Therefore, intensity of oxygen signal is a measure of plasma damage in the previous strip step.

Abstract: An optical element mounting method includes: illuminating ultraviolet light onto a polymer optical waveguide device; under the ultraviolet light illumination, capturing, by an image pickup device, the polymer optical waveguide device including a light incident/exiting position of a waveguide core; and judging, from a difference between bright and dark in a captured image, that a portion brighter than other portions or a portion darker than other portions is the light incident/exiting position of the waveguide core.

Abstract: A silicon-on-insulator transfer wafer having a front surface with a circumferential lip around a circular recess is polished. In one version, the circular recess on the front surface of the wafer is masked by filling the recess with spin-on-glass. The front surface of the wafer is exposed to an etchant to preferentially etch away the circumferential lip, while the circular recess is masked by the spin-on-glass. The spin-on glass is removed, and the front surface of the transfer wafer is polished. Other methods of removing the circumferential lip include applying a higher pressure to the circumferential lip in a polishing process, and directing a pressurized fluid jet at the base of the circumferential lip.

Abstract: A substrate holding structure includes a wafer stage having a first main surface and a second main surface opposite to the first main surface. A substrate placing area is defined on the first main surface. The substrate holding structure further includes a static capacity measurement electrode having a center circular electrode and at least one circular ring electrode for measuring a combined capacity among a substrate to be placed in the substrate placing area, the center circular electrode, and the circular ring electrode; at least one temperature measurement unit; an electrode control unit connected to the center circular electrode and the circular ring electrode; a temperature control unit connected to the temperature measurement unit and the temperature adjustment unit; a storage unit; a calculation unit connected to the storage unit; and a control unit connected to the electrode control unit and the temperature control unit.

Abstract: A semiconductor manufacturing apparatus includes a processing chamber for performing a manufacturing processing on a wafer. A gas supply line for introducing a purge gas is connected to an upper portion of the processing chamber, a valve being installed on the gas supply line. A rough pumping line with a valve is connected to a lower portion of the processing chamber. Installed on the rough pumping line are a dry pump for exhausting a gas in the processing chamber and a particle monitoring unit for monitoring particles between the valve and the dry pump. In the semiconductor manufacturing apparatus, after the valve is opened, the purge gas is supplied to apply physical vibration due to shock wave in the processing chamber so that deposits are detached therefrom to be monitored as particles.

Abstract: Systems, methods, and devices that facilitate stacking dies in a multi-die stack using die support mechanisms (DSMs) are presented. DSMs are employed to place a smaller die and attached wires underneath a larger die. DSMs can be placed on each side of the smaller die where the larger die overhangs when placed above the smaller die. The DSMs can be optimally sized to provide support to the larger die to reduce overhang and sagging, while providing a buffer region to protect the smaller die and associated wires. DSMs are employed to facilitate stacking dies that are the same or similar in size by placing a DSM between the dies. The DSM can be optimally sized to provide a buffer region to protect the wires bonded to the top side of the lower die from the upper die, while minimizing overhang to provide support to the upper die.

Abstract: A semiconductor component and method for producing. The semiconductor component includes a semiconductor device and a leadframe. A package layout is defined and the orientation of electrically conductive members with respect to the semiconductor device and inner contact areas of the leadframe is altered so as to maximize the interfacial bonding area. The constraints of the standard package dimensions and the component assembly method are taken into account.

Abstract: An object is to provide a laser dicing apparatus and a laser dicing method capable of speedily performing high-quality dicing without causing any working defect even in a case where wafers varying in thickness are supplied. The laser dicing apparatus is provided with a measuring device which measures thickness of a wafer W, a recording device which stores a database in which modified region forming conditions associated with different thicknesses of the wafer W are described, and a control device which controls the laser dicing apparatus by automatically selecting, from the database, on the basis of the thickness of the wafer measured by the measuring device, the modified region forming conditions corresponding to the measured thickness of the wafer W. The optimum modified region forming conditions are thereby automatically set, so that even in a case where wafers W differing in thickness are supplied, high-quality dicing can be speedily performed without causing a working defect.

Abstract: A method and system to modify a surface composition of thin film Group IBIIIA VIA solar cell absorbers having non-uniformly distributed Group IIIA materials or graded materials, such as Indium (In), gallium (Ga) and aluminum (Al). The graded materials distribution varies between the surface and the bottom of the absorber layer such that a molar ratio of (Ga+Al)/(Ga+Al+In) is the highest at the bottom of the absorber layer and the lowest at the surface of the absorber. Within the bulk of the absorber, the molar ratio gradually changes between the bottom and the surface of the absorber. In one embodiment, the surface composition of a graded absorber layer may be modified by removing a top portion or slice of the absorber layer, where the molar ratio is low so as to expose the inner portions of the absorber layer having a higher molar ratio of graded materials.

Abstract: A method for improving within-wafer uniformity is provided. The method includes forming an electrical component by a first process step and a second process step, wherein the electrical component has a target electrical parameter. The method includes providing a first plurality of production tools for performing the first process step; providing a second plurality of production tools for performing the second process step; providing a wafer; performing the first process step on the wafer using one of the first plurality of production tools; and selecting a first route including a first production tool from the second plurality of production tools. A within-wafer uniformity of the target electrical parameter on the wafer manufactured by the first route is greater than a second route including a second production tool in the second plurality of production tools.

Abstract: Surface treatment is performed with a liquid, while shielding a semiconductor surface from light. When the method is employed for surface treatment in wet processes such as cleaning, etching and development of the semiconductor surface, increase of surface microroughness can be reduced. Thus, electrical characteristics and yield of the semiconductor device are improved.

Abstract: A structure, a system and a method are directed towards determination of a dimension of a patterned dimensionally unstable layer when the dimension is measured using an apparatus that induces a variation of the dimension. The structure, system and method use a patterned dimensionally unstable layer pattern design that correlates with an algorithm used to determine the dimension when the dimension is measured using the apparatus that induces the variation of the dimension.

Abstract: In one disclosed embodiment, the present method for determining resist suitability for semiconductor wafer fabrication comprises forming a layer of resist over a semiconductor wafer, exposing the layer of resist to patterned radiation, and determining resist suitability by using a scatterometry process prior to developing a lithographic pattern on the layer of resist. In one embodiment, the semiconductor wafer is heated in a post exposure bake process after scatterometry is performed. In one embodiment, the patterned radiation is provided by an extreme ultraviolet (EUV) light source in a lithographic process. In other embodiments, patterned radiation is provided by an electron beam, or ion beam, for example. In one embodiment, the present method determines out-gassing of a layer of resist during exposure to patterned radiation.

Abstract: An arithmetic processing part in a controller detects a position of a defect such as a chip or a crack that occurs at an outer periphery of a semiconductor wafer, and then a memory in the controller stores position information of the defect. The controller reads the position information of the defect through a network in each process. On the basis of this position information, the controller determines a direction of joining a dicing tape to the semiconductor wafer or a direction of separating a protective tape from a front face of the semiconductor wafer.

Abstract: A change rate prediction method according to which there can be eliminated the need for experimentally determining electron beam intensities for making a change rate of a specification value of a predetermined film on a substrate uniform. The distribution of the shrinkage rate of a low-k film on a wafer upon the low-k film being modified is measured while changing the inputted current value inputted to a central electron beam tube of an electron beam irradiating mechanism, the relationship between the inputted current value and the shrinkage rate measured directly below the electron beam tube is calculated, and a dose distribution calculated through simulation is converted into a low-k film shrinkage rate distribution based on the ratio between the inputted current value and the dose and a power curve giving the relationship between the inputted current value and the measured shrinkage rate.

Abstract: According to the present invention, there is provided a semiconductor device fabrication method comprising: measuring light emission intensity of at least one type of wavelength contained in light emitted from a plasma, when one of nitriding, oxidation, and impurity doping is to be performed on a surface of a semiconductor substrate in a processing vessel by using the plasma; calculating, for each semiconductor substrate, an exposure time during which the semiconductor substrate is exposed to the plasma, on the basis of the measured light emission intensity; and exposing each semiconductor substrate to the plasma on the basis of the calculated exposure time, thereby performing one of the nitriding, oxidation, and impurity doping.

Abstract: There is provided a substrate processing method and apparatus which can measure and monitor thickness and/or properties of a film formed on a substrate as needed, and quickly correct a deviation in process conditions, and which can therefore stably provide a product of constant quality. A substrate processing method for processing a substrate having a metal and an insulating material exposed on its surface in such a manner that a film thickness of the metal, with an exposed surface of the metal as a reference plane, is selectively or preferentially changed, including measuring a change in the film thickness and/or a film property of the metal during and/or immediately after processing, and monitoring processing and adjusting processing conditions based on results of this measurement.

Abstract: In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.

Abstract: An apparatus and method for inspecting wafers at a reclaim factory is described. Embodiments of the invention describe an apparatus in which a wafer ID and wafer thickness may be simultaneously measured. A wafer is placed onto a sloped surface and positioned by aligning a notch in the wafer with a pin located on the surface, and by propping the wafer against a pair of laterally opposite restraints. In one embodiment, a foot-switch is used to trigger the simultaneous wafer ID and wafer thickness measurements.

Abstract: Structures, methods, and systems for assessing bonding of electrodes in FCB packaging are disclosed. In one embodiment, a method comprises mounting a semiconductor chip with a plurality of first electrodes of a first shape to a mounted portion with a second electrode of a second shape, wherein the second shape is different from the first shape, bonding a respective on of the plurality of first electrodes and the second electrode using a first solder bump, generating an X-ray image of the first solder bump, and determining an acceptability of the bonding of the respective one of the plurality of first electrodes and the second electrode based on the X-ray image of the first solder bump.

Abstract: A semiconductor device fabrication method can improve yield of semiconductor devices and decrease (or prevent) waste of non-defective semiconductor chips. This fabrication method has a step of performing characteristic inspection after packaging a semiconductor chip every time a semiconductor chip layer is formed. The fabrication method makes another semiconductor chip layer on this semiconductor chip layer only when the inspection indicates that the semiconductor chip is a non-defective product.

Abstract: A fixturing system and microscope/video camera setup enables an operator to manipulate a photodiode into position optically using known good targets for the X and Y location and using microscope focus/defocus/refocus for locating the active area of the avalanche photodiode exactly at the focal point of the lens.

Abstract: Methods for removing poly silicon. In one example embodiment, a method for removing poly silicon that is formed on a silicon wafer includes the steps of growing the poly silicon as a silicon oxide through a thermal oxidation process and removing the silicon oxide using an etching solution.

Abstract: A microchip formed by joining a first substrate having at least one recess on its surface and a second substrate, wherein small projections of 0.5 to 30 ?m in height are formed on at least a part of the surface having the recess of the first substrate, and a coating formed of a surface processing agent is provided on at least a part of the surface having the small projections formed thereon, as well as a method of manufacturing the microchip, are provided. A microchip allowing easy inspection of the state of application or state of adhesion of liquid material such as a surface processing agent, and allowing accurate optical measurement without causing disturbance such as fluorescence, can be provided.

Abstract: A gate insulating film 3 is formed of an insulative inorganic material containing silicon and oxygen as a main material. The gate insulating film 3 contains hydrogen atoms. A part of the absorbance of infrared radiation of which wave number is in the range of 830 to 900 cm?1 is less than both the absorbance of infrared radiation at the wave number of 830 cm?1 and the absorbance of infrared radiation at the wave number of 900 cm?1 when the insulating film to which an electric field has never been applied is measured by means of Fourier Transform Infrared Spectroscopy at room temperature.

Abstract: A lithography evaluating method comprises preparing a substrate, the substrate including a semiconductor substrate and a wiring structure including at least one wiring layer formed on the semiconductor substrate, partitioning the substrate into a plurality of regions to be evaluated, and obtaining a value of property relating to the wiring structure previously, and evaluating proximity effect on each of the plurality of regions to be evaluated based on the value of the property relating to the wiring structure.

Abstract: According to various exemplary embodiments, a spring device that includes a substrate, a self-releasing layer provided over the substrate and a stressed-metal layer provided over the self-releasing layer is disclosed, wherein an amount of stress inside the stressed-metal layer results in a peeling force that is higher than an adhesion force between the self-releasing layer and the stressed-metal layer. Moreover, a method of manufacturing a spring device, according to various exemplary embodiments, includes providing a substrate, providing a self-releasing layer over the substrate and providing a stressed-metal layer over the self-releasing layer wherein an amount of stress inside the stressed-metal layer results in a peeling force that is higher than an adhesion force between the self-releasing layer and the stressed-metal layer is also disclosed in this invention.

Abstract: Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one lot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process.

Abstract: An apparatus and a method for semiconductor wafer bonding provide in-situ and real time monitoring of semiconductor wafer bonding time. Deflection of the wafer edges during the last phase of the direct bonding process indicates the end of the bonding process. The apparatus utilizes a distance sensor to measure the deflection of the wafer edges and the bonding time is measured as the time between applying the force (bonding initiation) and completion of the bonding process. The bonding time is used as a real-time quality control parameter for the wafer bonding process.

Abstract: According to one exemplary embodiment, a method for adjusting a transistor model for increased circuit simulation accuracy includes determining a first gate CD offset by matching a C-V test structure having a normalized channel current to an I-V test structure having the normalized channel current. The method further includes utilizing the first gate CD offset to adjust the transistor model for increased circuit simulation. The method also includes determining a second gate CD offset by varying I-V and C-V gate length parameters in the transistor model to cause simulated data from a test circuit to be approximately equal to measured data from the test circuit. The method further includes utilizing the second gate CD offset to adjust the transistor model.

Abstract: A method of making a monitoring pattern to measure a depth and profile of a shallow trench isolation is disclosed. An example method of making a monitoring pattern of a shallow trench isolation profile forms a first pattern on a substrate to monitor a depth of a first shallow trench isolation. In the example method, the first pattern includes a plurality of unequally spaced active regions on the substrate. The example method also forms a second pattern on the substrate to measure electrical effects associated with a depth and a profile of a second shallow trench isolation. In the example method, the second pattern includes a plurality of equally spaced active regions on the substrate and a plurality of contact regions that electrically connect the equally spaced active regions.

Abstract: A method for manufacturing a shallow trench isolation (STI) structure is provided. In the method, a substrate is initially provided. Then, a patterned pad layer and a patterned mask layer are successively formed in order on the substrate. After that, a portion of the substrate is removed by using the patterned mask layer and the patterned pad layer as a mask to form trenches in the substrate. Next, a first insulation layer is formed in the trenches. Afterwards, a protection layer is conformally formed on the substrate. Then, a second insulation layer is formed on the protection layer above the first insulation layer. Next, the patterned mask layer and the patterned pad layer are removed. Finally, a portion of the protection layer and the second insulation layer are removed.