Abstract: A test structure which can be used to detect residual conductive material such as polysilicon which can result from an under etch comprises a PMOS transistor and an OTP EPROM floating gate device. By testing the devices using different testing parameters, it can be determined whether residual conductive material remains subsequent to an etch, and where the residual conductive material is located on the device. A method for testing a semiconductor device using the test structure is also described.

Abstract: Bonded wafers are produced by a method including a step (S1) of bonding together a wafer for supporting and a wafer for active layer, thereby forming a bonded body, a step (S2) of fabricating the wafer for active layer of the bonded body, thereby forming the active layer having a first thickness, a step (S3) of sticking a plurality of the bonded bodies having the active layer formed thereon to a polishing plate and polishing the active layer down to a second thickness, a step (S4) of optically measuring the second thickness while keeping the polished bonded bodies stuck to the polishing plate, and a step (S5) of polishing again the active layer down to a third thickness in response to the second thickness measured previously.

Abstract: Disclosed is a method for producing a group III nitride crystal substrate. A group III nitride crystal is formed by a growth method using a flux. The group III nitride crystal substrate is heat treated at a temperature equal to or higher than the lowest temperature at which the flux contained inside the group III nitride crystal substrate through intrusion into the crystal during the crystal formation can be discharged to outside the group III nitride crystal substrate, and equal to or lower than the highest temperature at which the surface of the group III nitride crystal substrate is not decomposed.

Abstract: An optical element mounting method includes: illuminating ultraviolet light onto a polymer optical waveguide device; under the ultraviolet light illumination, capturing, by an image pickup device, the polymer optical waveguide device including a light incident/exiting position of a waveguide core; and judging, from a difference between bright and dark in a captured image, that a portion brighter than other portions or a portion darker than other portions is the light incident/exiting position of the waveguide core.

Abstract: In a semiconductor manufacturing method, a metal film is formed on a substrate and heat treated. The relationship between substrate warping and the heat treatment temperature during silicide formation is acquired (S1). A silicide film is formed by forming a metal film on a substrate and heat treating, including substrate measurement during heat treatment (S2). The relationship between substrate warping at heat treatment temperature is determined from the relationship between the warping of the substrate and the temperature for heat treatment and the temperature for heat treatment carried out on the substrate when the warping of the substrate is measured. The difference between found warping and the measured warping is calculated (S4). Whether the difference exceeds a predetermined value is determined (S5). If the difference exceeds a predetermined value, heat treatment conditions are adjusted (S8), but they not adjusted if the difference is no greater than the predetermined value.

Abstract: An apparatus includes a first support structure configured to support an element that has an alignment marker provided with at least one height difference. The apparatus also includes an alignment sensor comprising a light source that is configured to provide a light beam that illuminates the alignment marker; and at least one detector configured to detect the at least one height difference of the alignment marker by analyzing the light beam reflected by the alignment marker. Such an apparatus may be used to align of the element with respect to the first support structure.

Abstract: Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.

Abstract: Provided is a method for fabricating an image sensor device that includes providing a substrate having a front side and a back side; patterning a photoresist on the front side of the substrate to define an opening having a first width, the photoresist having a first thickness correlated to the first width; performing an implantation process through the opening using an implantation energy correlated to the first thickness thereby forming a first doped isolation feature; forming a light sensing feature adjacent to the first doped isolation feature, the light sensing feature having a second width; and thinning the substrate from the back side so that the substrate has a second thickness that does not exceed twice a depth of the first doped isolation feature. A pixel size is substantially equal to the first and second widths.

Abstract: The present invention provides methods of manufacturing a high efficiency solar cell. In one embodiment, in a solar cell having a grid pattern that channels current, a defect causes an undesired current flow is removed by mechanically removing a portion of the grid pattern, thereby passivating the defect by removing a segment of the solar cell adjacent the defect. The segment also includes the front and back portions of the solar cell at the location of the defect without including the defect.

Abstract: An analysis method of wafer ion implant is presented, the steps of the method comprises: (a) cleave a wafer for analysis, and (b) from these pieces of wafers determine which ones are wafer with defect and set an insulator on the wafer with defect, (c) finally, use scanning electron microscope to observe whether the ion implant on the wafer with defect was correct or not. Whereby, engineers can take less time to analyze whether the ion implant of the wafer is correct or not with 100% repeatability.

Abstract: A method of rear surface treatment is carried out by: preparing a semiconductor or device in which an integrated circuit having a plurality of electrodes is provided on the front surface of a semiconductor substrate; electrically con netting the plurality of electrodes to an anode; and electropolishing the rear surface of the semiconductor substrate by performing anodic oxidation with an electrolytic solution placed in contact with the rear surface of the semiconductor substrate.

Abstract: In the manufacturing method of the array substrate, an under layer having a surface with irregular irregularities is formed on a substrate, a metal film with irregularities profiling the surface of the under layer is formed on the under layer, a colored resist layer is formed on the metal film, the colored resist layer is patterned to form a regularly arranged colored resist pattern, an optical inspection is performed to optically detect a defect of the colored resist pattern, a defect of the colored resist pattern detected by the optical inspection is repaired; and the metal film is etched while using the resist pattern as a mask.

Abstract: A laser irradiation process includes: scanning a substrate with laser having a predetermined lasing frequency at different irradiation intensities to form a plurality of first irradiation areas corresponding to the irradiation intensities; illuminating the first irradiation areas to reflected light receive from the first irradiation areas; determining microcrystallization intensity based on the received reflected light; and determining irradiation intensity based on the thus determined microcrystallization intensity. The laser irradiation process uses the irradiation intensity for irradiating a polycrystalline film in a product semiconductor device.

Abstract: The present inventions relate to methods and apparatus for detecting and mechanically removing defects and a surrounding portion of the photovoltaic layer and the substrate in a thin film solar cell such as a Group IBIIIAVIA compound thin film solar cell to improve its efficiency.

Abstract: A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.

Abstract: A method for determining the presence of a sacrificial layer under a structure. The method includes providing at least one structure arranged above a substrate having a major surface lying in a plane, the at least one structure being clamped at at least one side. The method further includes exerting a force, such as a mechanical force, on the at least one structure. The force may have a predetermined amplitude and a component perpendicular to the substrate. Still further, the method includes determining the deflection of the at least one structure perpendicular to the plane of the substrate, and correlating the deflection of the at least one structure to the presence of a sacrificial layer between the substrate and the structure.

Abstract: Method and system for determining semiconductor characteristics. In a specific embodiment, the present invention provides a method for determining one or more characteristics of a partially processed integrated circuit. The method includes a step for providing a substrate material. The method further includes a step for forming at least one opening within the substrate material. The opening can be characterized by an opening characteristic that includes a depth and an opening width associated with an unknown volume. The method includes a step for providing fill material. Additionally, the method includes a step for processing the fill material to cause a first portion of the fill material to enter the opening and occupy an entirety of the unknown volume associated with the opening characteristic while a second portion of the fill material remains outside of the unknown volume.

Abstract: The present invention relates to a method for trimming passive devices during fabrication to account for process variations. More particularly, the present invention relates to a method by which an adjustable device layer comprised within a passive device (e.g., resistor body, capacitor electrodes) can be measured and subsequently trimmed (e.g., etched to reduce size) during processing to correct for process variations. Essentially, an operational parameter is measured for a plurality of passive devices. The measurements are used to form an adjustment map for a region of a semiconductor body (e.g., wafer) comprising information pertaining to operational parameters as a function of spatial coordinates. The adjustment map is utilized by a DMD projector configured to pattern openings into a hardmask configured over the adjustable device layer. The adjustable device layer is then etched in regions not protected by the hardmask, thereby effectively trimming the passive device according to the adjustment map.

Abstract: A method of manufacturing a semiconductor device estimates the level of erosion generated in CMP of a plug by using a monitoring pattern that defines uniformly a hole array size (split a) and the length (split b) of the space between arrays.

Abstract: A laser processing apparatus which achieves both shorter TAT and reduction in processing defects. In the apparatus, a laser radiation section, an undulation measurement section for measuring undulation of a substrate or a film thickness measuring section for measuring the thickness of a thin film formed on the substrate, and an optical inspection section for optically inspecting grooves formed by laser-processing the thin film on the substrate are fixed so that their positional relationship is kept constant.

Abstract: A semiconductor-device manufacturing method includes steps of performing a sidewall fabrication thereby forming a first pattern structure; measuring an amount of displacement of line portions of the first pattern structure; correcting an overlay specification for an overlay of the first pattern structure and a second pattern structure dynamically based on the amount of displacement; and determining whether an error in the overlay of the first pattern structure and the second pattern structure meets the corrected overlay specification.

Abstract: A method of manufacturing a semiconductor device includes depositing material on a wafer in a process chamber to form a thin film on the wafer, a by-product layer being simultaneously formed on an inner part of the process chamber, monitoring a change in thickness or mass of the by-product layer on the inner part of the process chamber during a process in the process chamber by using a QCM installed in the process chamber, and determining an end point of the process in the process chamber based on the monitored change in thickness or mass of the by-product layer in the process chamber.

Abstract: The present invention relates to methods and apparatus for providing composition control to thin compound semiconductor films for radiation detector and photovoltaic applications. In one aspect of the invention, there is provided a method in which the molar ratio of the elements in a plurality of layers are detected so that tuning of the multi-element layer can occur to obtain the multi-element layer that has a predetermined molar ratio range. In another aspect of the invention, there is provided a method in which the thickness of a sub-layer and layers thereover of Cu, In and/or Ga are detected and tuned in order to provide tuned thicknesses that are substantially the same as pre-determined thicknesses.

Abstract: A laser beam irradiation method that achieves uniform crystallization, even if a film thickness of an a-Si film or the like fluctuates, is provided. The present invention provides a laser beam irradiation method in which a non-single crystal semiconductor film is formed on a substrate having an insulating surface and a laser beam having a wavelength longer than 350 nm is irradiated to the non-single crystal semiconductor film, thus crystallizing the non-single crystal silicon film. The non-single crystal semiconductor film has a film thickness distribution within the surface of the substrate, and a differential coefficient of a laser beam absorptivity with respect to the film thickness of the non-single crystal semiconductor film is positive.

Abstract: A method of aligning a set of patterns on a substrate, the substrate including a substrate surface, is disclosed. The method includes depositing a set of silicon nanoparticles on the substrate surface, the set of nanoparticles including a set of ligand molecules including a set of carbon atoms, wherein a first set of regions is formed where the silicon nanoparticles are deposited and the remaining portions of the substrate surface define a second set of regions. The method also includes densifying the set of silicon nanoparticles into a thin film wherein a set of silicon-organic zones are formed on the substrate surface, wherein the first set of regions has a first reflectivity value and the second set of regions has a second reflectivity value. The method further includes illuminating the substrate surface with an illumination source, wherein the ratio of the second reflectivity value to the first reflectivity value is greater than about 1.1.

Abstract: An apparatus and method to inspect a defect of a semiconductor device. The amount of secondary electrons generated due to a scanning electron microscope (SEM) may depend on the topology of a pattern of a semiconductor substrate. The amount of secondary electrons emitted from a recess of an under layer is far smaller than that of secondary electrons emitted from a projection of a top layer. Since the recess is darker than the projection, a ratio of a value of a secondary electron signal of the under layer to a value of a secondary electron signal of the top layer may be increased in order to improve a pattern image used to inspect a defect in the under layer. To do this, a plurality of conditions under which electron beams (e-beams) are irradiated may be set, at least two may be selected out of the set conditions, and the pattern may be scanned under the selected conditions.

Abstract: A nondestructive testing method for an oxide semiconductor layer includes the steps of applying excitation light to an amorphous or polycrystalline target oxide semiconductor layer to be tested and measuring an intensity of photoluminescence in a wavelength region longer than a wavelength corresponding to a bandgap energy among light emitted from the target oxide semiconductor layer; and estimating a film property of the target oxide semiconductor layer on the basis of measurement results.

Abstract: An arithmetic processing part in a controller detects a position of a defect such as a chip or a crack that occurs at an outer periphery of a semiconductor wafer, and then a memory in the controller stores position information of the defect. The controller reads the position information of the defect through a network in each process. On the basis of this position information, the controller determines a direction of joining a dicing tape to the semiconductor wafer or a direction of separating a protective tape from a front face of the semiconductor wafer.

Abstract: In crystallization of a silicon film by annealing with a linear-shaped laser beam having an ununiform width of the short axis of the beam, the profile (intensity distribution) of the laser beam is evaluated, and the result is fed back to an oscillating condition of the laser beam or an optical condition which projects this onto the silicon film, whereby a display device comprising a high-quality crystalline silicon film is produced.

Abstract: A method of producing a semiconductor device includes the steps of preparing an SOQ (Silicon On Quartz) substrate in which a semiconductor layer is formed on a quartz substrate; forming a plurality of semiconductor device forming regions in the SOQ substrate; forming a crack inspection pattern in the SOQ substrate; inspecting the crack inspection pattern to detect a crack in the crack inspection pattern in a first inspection step; and inspecting the semiconductor device forming regions to detect a crack in the semiconductor device forming regions in a second inspection step when the crack is detected in the crack inspection pattern in the first inspection step.

Abstract: According to the present invention, there is disclosed a thermal detection device and method of using the device for characterizing and monitoring the dependence of pattern density on thermal absorption of a semiconductor. One or more of the devices can be disposed on a die of a test wafer. The thermal detection device comprises a silicon substrate having a test structure located substantially in the center of the silicon substrate. Frame shaped structures of polysilicon, silicon and oxide, in various configurations, form a collocated arrangement on the silicon substrate. The test wafer is subjected to a rapid thermal process and the resistance of the at least one testing structure is measured and the measured resistance of the at least one test structure is tabulated to a thermal absorption value of the at least one die.

Abstract: Methods of optimizing optical alignment in an optical package are provided. In one embodiment, the optical package includes a laser diode, a wavelength conversion device, coupling optics positioned along an optical path extending from the laser diode to the wavelength conversion device, and one or more adaptive actuators. The method involves adjusting the optical alignment of the wavelength conversion device in a non-adaptive degree of freedom by referring to a thermally-dependent output intensity profile of the laser diode and a thermally-dependent coupling efficiency profile of the optical package.

Abstract: A method of forming bare silicon substrates is described. A bare silicon substrate is measured, wherein measuring is performed by a non-contact capacitance measurement device to obtain a signal at a point on the substrate. The signal or a thickness indicated by the signal is communicated to a controller. An adjusted polishing parameter according to the signal or thickness indicated by the signal is determined. After determining an adjusted polishing parameter, the bare silicon substrate is polished on a polisher using the adjusted polishing parameter.

Abstract: A process control method includes setting first through fourth conditions, forming a first pattern by performing a first process on a semiconductor wafer, measuring the first pattern using a first measuring equipment to obtain a first result, comparing the first result with the first condition, forming a second pattern by performing a second process on the semiconductor wafer, comparing a period of the second process with the second condition, measuring the second pattern using a second measuring equipment to obtain a second result, comparing the second result with the third condition, forming a third pattern by performing a third process on the semiconductor wafer, measuring the third pattern using the a second measuring equipment to obtain a third result, and comparing the third result with the fourth condition.

Abstract: A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.

Abstract: A method of making a light emitting diode includes forming a plurality of electrically conductive members at intervals on a first surface of an epitaxial layer which generates light so that the electrically conductive members are in ohmic contact with the epitaxial layer, forming a light incident layer on the first surface at regions where none of the electrically conductive members are formed, forming a light reflecting layer on the light incident layer and the electrically conductive members, providing an adhesive on the light reflecting layer, and bonding a permanent substrate to the light reflecting layer through the adhesive and through a wafer bonding process.

Abstract: A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time.

Abstract: Methods, systems, and apparatus, including computer program products, for spectrographic monitoring of a substrate during chemical mechanical polishing are described. In one aspect, a computer-implemented method includes receiving a first sequence of current spectra of reflected light from a first zone of a substrate. A second sequence of current spectra of reflected light from a second zone of the substrate is received. Each current spectrum from the first sequence of current spectra is compared to a plurality of reference spectra from a first reference spectra library to generate a first sequence of best-match reference spectra. Each current spectrum from the second sequence of current spectra is compared to a plurality of reference spectra from a second reference spectra library to generate a second sequence of best-match reference spectra. The second reference spectra library is distinct from the first reference spectra library.

Abstract: A substrate processing method can securely form a metal film by electroless plating on an exposed surface of a base metal, such as interconnects, with increased throughput and without the formation of voids in the base metal. The substrate processing method includes: cleaning a surface of a substrate having a base metal formed in the surface with a cleaning solution comprising an aqueous solution of a carboxyl group-containing organic acid or its salt and a surfactant as an additive; bringing the surface of the substrate after the cleaning into contact with a processing solution comprising a mixture of the cleaning solution and a solution containing a catalyst metal ion, thereby applying the catalyst to the surface of the substrate; and forming a metal film by electroless plating on the catalyst-applied surface of the substrate.

Abstract: A method for manufacturing an optical device, the method includes the steps of: forming a multilayer film, including forming a first mirror above a substrate, forming an active layer above the first mirror, forming a second mirror above the active layer, forming a semiconductor layer on the second mirror, and forming a sacrificial layer on the semiconductor layer; conducting a reflection coefficient examination on the multilayer film; patterning the multilayer film to form a surface-emitting laser section having the first mirror, the active layer and the second mirror, and a diode section having the semiconductor layer; and removing at least a portion of the sacrificial layer to expose at least a portion of an upper surface of the semiconductor layer, wherein an optical film thickness of the semiconductor layer is formed to be an odd multiple or an even multiple of ?/4, where ? is a design wavelength of light emitted by the surface-emitting laser section, and an optical film thickness of the sacrificial layer

Abstract: Exemplary embodiments provide methods for implementing an ultra-high temperature (UHT) anneal on silicon germanium (SiGe) semiconductor materials by co-implanting carbon into the SiGe material prior to the UHT anneal. Specifically, the carbon implantation can be employed to increase the melting point of the SiGe material such that an ultra high temperature can be used for the subsequent anneal process. Wafer warpage can then be reduced during the UHT anneal process and potential lithographic mis-alignment for subsequent processes can be reduced. Exemplary embodiments further provide an inline control method, wherein the wafer warpage can be measured to determine the litho-mis-alignment and thus to control the fabrication process. In various embodiments, the disclosed methods can be employed for the fabrication of source/drain extension regions and/or source/drain regions of transistor devices, and/or for the fabrication of base regions of bipolar transistors.

Abstract: The semiconductor device according to an aspect of the invention includes: an internal circuit area having an internal circuit; an I/O circuit area positioned outside the internal circuit area; and an electrode pad placed across an outer edge of the I/O circuit area. In the electrode pad, an area outside the outer edge of the I/O circuit area is a bonding area, and an area inside the outer edge is a probe area.

Abstract: A method for providing a process indicator for an etching chamber is provided. A wafer with a blanket etch layer is provided into the etching chamber. A blanket etch is performed on the blanket etch layer. A blanket deposition layer is deposited over the blanket etch layer after performing the blanket etch has been completed. A thickness of the blanket etch layer and a thickness of the blanket deposition layer is measured. The measured thicknesses are used to determine a process indicator.

Abstract: When annealing of a semiconductor film is conducted using a plurality of lasers, each of the distances between laser irradiation regions is different. When a lithography step is conducted in accordance with a marker which is formed over a substrate in advance after the step, light-exposure is not correctly conducted to a portion crystallized by laser. By using a laser irradiation region obtained on a laser irradiation step as a marker, light-exposure is conducted by making a light-exposure position of a stepper coincide with a large grain size region in the laser irradiation region. A large grain size region and a poorly crystalline region are detected by utilizing a thing that scattering intensity of light is different between the large grain size region and the poorly crystalline region, thereby determining a light-exposure position.

Abstract: The present invention provides a method and apparatus for modifying process selectivities based on process state information. The method includes accessing process state information associated with at least one material removal process, determining at least one selectivity based on the process state information, and modifying at least one process parameter of said material removal process based on said at least one determined selectivity.

Abstract: A doping process, including applying pressure to at least one first phase of a semiconductor containing an electrically inactive dopant and removing the pressure to cause at least one phase transformation of the semiconductor to at least one second phase, wherein the at least one phase transformation activates the dopant so that the at least one second phase includes at least one doped phase of the semiconductor in which the dopant is electrically active.

Abstract: A method for forming a dual damascene structure is disclosed. First a substrate is provided. There are an etching stop layer and an interlayer dielectric layer disposed on the substrate in order. The interlayer dielectric layer has a thickness A. Second, the interlayer dielectric layer is patterned to form a first opening. Later, a photo resist layer with a thickness B is formed on the interlayer dielectric layer. Then, the photo resist layer is patterned by a light source to construct a patterned photo resist layer. Later, the interlayer dielectric layer is again patterned by the patterned photo resist to pattern the interlayer dielectric layer to construct a second opening on the first opening by means of a light source and the photo resist layer so as to form a dual damascene structure. The light source has a periodic parameter C so that (A+B)/C?X/2, where X is an odd number.

Abstract: Method for manufacturing a semiconductor optical device includes forming an epitaxial structure containing at least an active layer which can emit light, of a III-V group semiconductor material; forming an insulating layer over the epitaxial structure, which prevents the V group element from escaping from the epitaxial structure during heat treatment; heat treating the epitaxial structure at at least 800 degrees C.; and removing the insulating layer, thereby enhancing the reliability of the device.

Abstract: A defect inspection method includes generating and applies a charged beam to a sample with patterns; controlling a shape of the charged beam so that a beam width in a first direction perpendicular to an optical axis differs from a beam width in a second direction perpendicular to the optical axis and the first direction, while substantially maintaining a cross-sectional area of the beam; scanning the sample with the charged beam having the controlled shape; and detecting charged particles from the sample by irradiation of the charged beam and detects a defect of the patterns. Assuming that the beam width of the charged beam in the first direction is smaller than that in the second direction, the first direction is set to a direction in which an interval between adjacent patterns becomes a minimum value and the sample is scanned in the second direction.

Abstract: Techniques for processing power transistor devices are provided. In one aspect, the curvature of a power transistor device comprising a device film formed on a substrate is controlled by thinning the substrate, the device having an overall residual stress attributable at least in part to the thinning step, and applying a stress compensation layer to a surface of the device film, the stress compensation layer having a tensile stress sufficient to counterbalance at least a portion of the overall residual stress of the device. The resultant power transistor device may be part of an integrated circuit.