Abstract: An apparatus and method is described for measuring a local surface temperature of a semiconductor device under stress. The apparatus includes a substrate, and a reference MOSFET. The reference MOSFET may be disposed closely adjacent to the semiconductor device under stress. A local surface temperature of the semiconductor device under stress may be measured using the reference MOSFET, which is not under stress. The local surface temperature of the semiconductor device under stress may be determined as a function of drain current values of the reference MOSFET measured before applying stress to the semiconductor device and while the semiconductor device is under stress.

Abstract: Dicing lines extending longitudinally and transversely, and chip areas surrounded by the dicing lines are formed in a resist mask. Critical-dimension patterns are formed in the dicing lines so as to be paired while placing the center line thereof in between. The dimensional measurement of the resist film having these patterns formed therein is made under a CD-SEM, by specifying a measurement-target chip area out of a plurality of chip areas, and by specifying a position of a critical-dimension pattern on the left thereof. Then, the distance of two linear portions configuring the critical-dimension pattern is measured, wherein a portion at a point of measurement on the measurement-target chip area side as viewed from the center line of the dicing line is measured.

Abstract: A method for forming a semiconductor package provides a ball grid array, BGA, formed on a package substrate. The apices of the solder balls of the BGA are all at the same height, even if the package substrate is non-planar. Different solder ball pad sizes are used and tailored to compensate for non-planarity of the package substrate that may result from thermal warpage. Larger size solder ball pads are formed at relatively-high locations on the package substrate. An equal amount of solder is formed on each of the solder ball pads to produce solder balls having different heights and coplanar apices.

Abstract: A method for measuring a thin film thickness is provided. The method includes the following steps: providing a plurality of structures, each including a semiconductor substrate, a thin film, and a metal layer; measuring resistances of the metal layers of the plurality of structures and thicknesses of the thin films of the plurality of structures to obtain a plurality of resistance values and a plurality of corresponding thickness values; establishing a thickness-resistance table based on the plurality of resistance values and thickness values; providing a structure to be tested including a semiconductor substrate, a thin film, and a metal layer; and measuring resistance of the metal layer of the structure to be tested to determine a thickness value of the thin film of the structure to be tested according to the thickness-resistance table.

Abstract: A method is provided for fabricating a multilayer electronic device on a flexible substrate including at least a first and a second patterned layer, wherein the first patterned layer is defined with a linewidth that is smaller than the linewidth of the second patterned layer, and the second patterned layer is defined by a patterning technique which is capable of correcting for local distortions of the pattern of said first layer on top of the flexible substrate and wherein the first patterned layer is laid-out in such a way that the geometric overlap between a portion of the second layer and a portion of the first layer is insensitive against small variations of the position of the second patterned layer.

Abstract: Disclosed herein is a fabrication method for a semiconductor device, including a lithography step of connecting a plurality of mask patterns to each other to form a pattern image of an area greater than the size of the mask patterns. The lithography step includes the steps of: assuring an overlapping exposure region to be exposed in an overlapping relationship by both of two mask patterns to be connected to each other, carrying out exposure transfer of the pattern portions of the two mask patterns to the overlapping exposure region to form a first measurement mark and a second measurement mark in the overlapping exposure region, and carrying out positional displacement measurement of pattern connection by the two mask patterns based on a manner of combination of main marks and sub marks of the measurement marks formed in the overlapping exposure region.

Abstract: In the present invention, there is provided an optical proximity correction method including steps of: extracting a gate length distribution of a gate from a pattern shape of the gate of a transistor to be formed on a wafer; calculating electric characteristics of the gate; determining a gate length of a rectangular gate having electric characteristics equivalent to the calculated electric characteristics; calculating a corrective coefficient for describing an associated relationship between a statistical value of the extracted gate length distribution and the determined gate length; extracting a gate length distribution of a gate of a transistor by printing the design pattern, and calculating a gate length distribution representative value from the statistical value of the gate length distribution using the calculated corrective coefficient; and correcting the design pattern so that the calculated gate length distribution representative value will be a specification value.

Abstract: A method of processing semiconductor waters comprises forming a pattern of recesses in an exposed surface of each water in a lot, prior to an epitaxy step. At least one recessed test structure is included in the pattern of recesses. At least one dimension of the recessed test structure is determined prior to the epitaxy step, then a corresponding dimension of an epitaxial structure grown above the recessed test structure in the epitaxy step is measured. A deviation between the dimension of the recessed test structure and the dimension of the epitaxial structure is determined and, from the deviation, the process temperature at which the epitaxy step was performed is determined. In case the deviation exceeds a predetermined limit, the temperature in the process chamber is adjusted for a subsequent lot of waters to be processed.

Abstract: A semiconductor device including a capacitor formed over a semiconductor substrate and including a lower electrode, a dielectric film formed over the lower electrode and an upper electrode formed over the dielectric film, an insulation film formed over the semiconductor substrate and the capacitor, and an electrode pad formed over the insulation film and including an alloy film of aluminum and magnesium.

Abstract: A method includes illuminating at least a portion of a first grid including a first plurality of stressed material regions formed at least partially in a semiconducting material. Light reflected from the illuminated portion of the first grid is measured to generate a first reflection profile. A characteristic of the first plurality of stressed material regions is determined based on the first reflection profile. A test structure includes a first plurality of stressed material regions recessed with respect to a surface of a semiconductor layer and defining a first grid. A first plurality of exposed portions of the semiconductor layer is disposed between each of the first plurality of stressed material regions.

Abstract: A method of manufacturing a semiconductor device includes measuring a first width of a first mask pattern formed in a photomask and a second width of a second mask pattern formed in the photomask, and deciding a temperature of heat treatment of a thickening material over a resist film based on measured results.

Abstract: A semiconductor integrated circuit production method prepares an SOI layer thickness database that correlates measurement data of each SOI layer thickness with each SOI substrate identification data. The production method extracts the measurement data for each SOI substrate from the SOI layer thickness database, and carries out layer thickness adjustment surface treatment for the SOI substrates based on these data. A semiconductor integrated circuit production device includes an SOI layer thickness database storage unit for storing the SOI layer thickness database, and a layer thickness adjustment conditions control unit for extracting the measurement data for each SOI substrate from the SOI layer thickness database and deciding conditions for the layer thickness adjustment surface treatment based on these data.

Abstract: A laser crystallization apparatus which capable of correcting both shift in imaging position caused by thermal lens effect of the imaging optical system and shift due to flatness of the substrate comprises an crystallization optical system which irradiates laser light to a thin film disposed on the substrate to melt and crystallize an irradiated region of the thin film, the apparatus includes a measurement light source which is disposed outside a light path of the laser light, and which emits measurement light being illuminated the irradiated region of the thin film, and a substrate height correction system which illuminates the thin film with the measurement light through an imaging optical system in the crystallization optical system, and which detects the reflected measurement light from the thin film.

Abstract: According to the present invention, there is provided a semiconductor device fabrication method comprising: measuring light emission intensity of at least one type of wavelength contained in light emitted from a plasma, when one of nitriding, oxidation, and impurity doping is to be performed on a surface of a semiconductor substrate in a processing vessel by using the plasma; calculating, for each semiconductor substrate, an exposure time during which the semiconductor substrate is exposed to the plasma, on the basis of the measured light emission intensity; and exposing each semiconductor substrate to the plasma on the basis of the calculated exposure time, thereby performing one of the nitriding, oxidation, and impurity doping.

Abstract: A micro electro-mechanical system, which can be stably formed so as to prevent sticking of a movable part and which has a narrow gap, and a method of manufacturing the same are provided. The micro electro-mechanical system includes at least one fixed electrode formed above a principal surface of a semiconductor substrate and at least one movable electrode formed on the principal surface. The at least one movable electrode includes the movable part separated from the principal surface and the at least one fixed electrode. The movable part is movable with respect to the principal surface and the at least one fixed electrode.

Abstract: A deposition film shape simulation method for calculating a thickness of a thin-film formed by supplying deposition species on a substrate surface, includes: changing a parameter to be used in the calculation depending on the thickness of the deposited thin-film.

Abstract: A metallic electrode forming method includes: forming a bed electrode on a substrate; forming a protective film with an opening on the bed electrode to expose the bed electrode from the opening; forming a metallic film covering the protective film and the opening; mounting the substrate on an adsorption stage, and measuring a surface shape of the metallic film by a surface shape measuring means; deforming the substrate by a deforming means so that a difference between the principal surface and a cutting surface is within a predetermined range; measuring a surface shape of the principal surface, and determining whether the difference is within a predetermined range; and cutting the substrate along with the cutting surface so that the metallic film is patterned to be a metallic electrode.

Abstract: A method for aligning a micro-mirror device die having a plurality of micro-mirror devices formed on a semiconductor substrate and fixing the micro-mirror device die on the semiconductor substrate can be provided. The method comprises a first alignment step of aligning a first guide portion of the micro-mirror device die and a second guide portion of the package substrate and a fixing step of fixing the micro-mirror device die on the package substrate in a position aligned by the first alignment step using the first and second guide portions.

Abstract: Excitation light is irradiated onto a GaN layer on a silicon carbide substrate constituting a layered product that is set on a stage. Then light is emitted from a defective part caused by a structural defect of the silicon carbide substrate out of the GaN layer. By using this light luminescence phenomena, a position of a defective part of the silicon carbide substrate can be detected.

Abstract: A method of forming a monitor mark includes forming an insulating film on a semiconductor substrate, and forming a first repetitive line pattern group and a second repetitive line pattern group by patterning the insulating film on the semiconductor substrate, such that the first repetitive line pattern group and the second repetitive line pattern group face each other with a predetermined space therebetween.

Abstract: Embodiments of the invention enable detection of edge damages in semiconductor devices. To this purpose, one or more continuity structures may be provided, where each structure comprises an undulating arrangement disposed between active circuits of the semiconductor device and a perimeter of the metallization layers. The continuity structure(s) forms one or more conductive paths intersecting a plurality of metallization layers in the semiconductor device. A relative change in an electrical characteristic of the continuity structure(s) is monitored to ascertain whether or not an edge damage is present.

Abstract: A method of manufacturing a semiconductor device includes measuring the reflectance at the surface of a semiconductor substrate provided with concave portions and deciding a deposition parameter that represents a deposition condition corresponding to the measured reflectance. Then, a metal film is formed on the semiconductor substrate under a condition corresponding to the deposition parameter.

Abstract: An object is to prevent a breakage of a membrane probe and a wafer to be tested in a probe testing using a membrane probe with styluses formed by a manufacturing technology for a semiconductor integrated circuit device. Measures are: obtaining an image of a region PCA within the surface of a wafer including a region OGA pressed by a pressing member, at the center of which a chip just after probe-tested is located, by an imaging means such as a camera; comparing an image of a normal chip obtained in advance and an image of all the chips within the region PCA; and judging thereby whether an abnormal shape is caused or not in all the chips within the region PCA.

Abstract: A disclosed observation apparatus for observing a void generated in an underfill resin upon mounting a body to be mounted on a substrate via the underfill resin in flip-chip mounting includes: a mounting unit mounting the body to be mounted on the substrate; and an observation unit observing behavior of the underfill resin while the mounting unit is mounting the body to be mounted on the substrate.

Abstract: Methods and apparatus for assessing a constituent in a semiconductor substrate. Several embodiments of the invention are directed toward non-contact methods and systems for identifying an atom specie of a dopant implanted into the semiconductor substrate using techniques that do not mechanically contact the substrate with electrical leads or other types of mechanical measuring instruments. For example, one embodiment of a non-contact method of assessing a constituent in a semiconductor substrate in accordance with the invention comprises obtaining an actual reflectance spectrum of infrared radiation reflected from the semiconductor substrate, and ascertaining a plasma frequency value (?p) and a collision frequency value (?) for the semiconductor substrate based on the actual reflectance spectrum. This method can further include identifying a dopant type based on a relationship between dopant types and (a) plasma frequency values and (b) collision frequency values.

Abstract: In crystallization of a silicon film by annealing with a linear-shaped laser beam having an ununiform width of the short axis of the beam, the profile (intensity distribution) of the laser beam is evaluated, and the result is fed back to an oscillating condition of the laser beam or an optical condition which projects this onto the silicon film, whereby a display device comprising a high-quality crystalline silicon film is produced.

Abstract: There is provided a substrate processing method and apparatus which can measure and monitor thickness and/or properties of a film formed on a substrate as needed, and quickly correct a deviation in process conditions, and which can therefore stably provide a product of constant quality. A substrate processing method for processing a substrate having a metal and an insulating material exposed on its surface in such a manner that a film thickness of the metal, with an exposed surface of the metal as a reference plane, is selectively or preferentially changed, including measuring a change in the film thickness and/or a film property of the metal during and/or immediately after processing, and monitoring processing and adjusting processing conditions based on results of this measurement.

Abstract: A semiconductor manufacturing apparatus and substrate processing method is provided with which the film formed on a substrate can be controlled in thickness and quality.

Abstract: The present invention is a method for testing a contact open capable of effectively testing a contact open defect in an In-line as securing a mass productivity. The method includes the steps of: performing a photolithography process for forming a contact; forming a contact hole by performing a contact etching process after sampling at least one wafer; depositing a conductive layer on the wafer provided with the contact hole; isolating the conductive layer within the contact hole; performing a test for testing a contact open interface to check whether a remaining layer is existed in an interface between the conductive layer and a lower structure of the conductive layer; and performing a process for etching the contact of a main lot based on a test result.

Abstract: A semiconductor device and a method for controlling its patterns is described where the electrical characteristics of the patterns formed by a double patterning process may be individually controlled responsive to critical dimensions (CDs) of the patterns. The method includes controlling two or more patterns having different CDs to optimally operate the patterns. The patterns may be individually controlled by signals provided to the patterns on the basis of the pattern's CDs. The signals may be controlled by controlling the magnitudes or the application time of the signals provided to the respective patterns.

Abstract: The present invention provides a method for evaluating nanotopography of a surface of a semiconductor wafer sliced from a semiconductor ingot, the method being conducted prior to polishing of the surface, the method at least comprising: measuring a surface profile of the wafer in the direction that the wafer is sliced; determining a maximum inclination value of warp change of the wafer surface in a sectional profile in the direction that the wafer is sliced of the measured surface profile; and estimating nanotopography of the wafer surface after being polished based on the determined maximum value. As a result, there are provided a method and an apparatus for evaluating nanotopography of a surface of a semiconductor wafer, and a method for manufacturing a semiconductor wafer exhibiting good nanotopography level on the surface.

Abstract: When a design diagram of the semiconductor device by a conventional CAD tool is used, a pattern which can be formed with the ink-jet apparatus is limited; therefore, there is a possibility that some circuits of the desired semiconductor device cannot be formed as they are designed. A plurality of basic patterns which can be obtained by discharging with the ink-jet apparatus are prepared, and layout of a desired integrated circuit is performed by combining the patterns. A light-exposure mask is formed based on the layout obtained. Light exposure is performed using the light-exposure mask. Then, development is performed, and the resist film remains in the light-exposed region of which width is narrower than the diameter of the droplet landed. Liquid repellent treatment is performed to an exposed portion on the surface, and then the material droplet is dropped over the resist film.

Abstract: A two-step method for etching a fuse window on a semiconductor substrate is provided. A semiconductor substrate having thereon a fuse interconnect-wire is formed in a dielectric film stack. The dielectric film stack includes a target dielectric layer overlying said fuse interconnect-wire, an intermediate dielectric layer and a passivation layer. A photoresist layer is formed on the passivation layer with an opening that defines said fuse window. A first dry etching process is performed to non-selectively etch the passivation layer and the intermediate dielectric layer through the opening thereby exposing the target dielectric layer. The thickness of the target dielectric layer after the first dry etching process is then measured. An APC-controlled second dry etching process is performed to etch a portion of the exposed target dielectric layer, thereby reliably forming the fuse window.

Abstract: A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the first and second sets of alignment marks. A portion of the opaque layer corresponding to the location of said first set of alignment marks is opened so as to render the first set optically visible while the second set of alignment marks initially remains covered by the opaque layer. The opaque layer is patterned using the optically visible first set of alignment marks, wherein the second set of alignment marks remain available for subsequent alignment operations in the event the first set becomes damaged during patterning of the opaque layer.

Abstract: A method wherein a substrate is provided, wherein, in a scanning step, structures already applied to the substrate are detected by at least one scanning provision of a processing head, wherein the processing head is provided with at least one lighting provision, which lighting provision locally lights the applied lacquer structure in a lighting step by using the information obtained with the scanning step. Further, the invention discloses an apparatus for carrying out the method is described, which apparatus is provided with a processing head which is movable relative to a substrate carrier, wherein the processing head comprises at least one scanning provision and at least one lighting provision.

Abstract: Recessing a trench using feed forward data is disclosed. In one embodiment, a method includes providing a region on a wafer including a trench area that includes a trench and a field area that is free of any trench, and a material applied over the region so as to fill the trench in the trench area and form a step between the trench area and the field area; etching to partially etch the trench; determining a target etch duration (tD) for etching to the target depth (DT); and etching the trench to the target depth (DT) for a period approximately equal to the target etch duration (tD). The target etch duration tD may be fed forward for recessing another trench to the target depth DT. The method does not require a send ahead wafer, is fully compatible with conventional automated processes and provides in-situ etch time correction to each wafer.

Abstract: A device and method for measuring ion beam angle with respect to a substrate is disclosed. The method includes forming a plurality of shadowing structures extending substantially perpendicular from an upper surface of the substrate, directing an ion beam toward the substrate, the plurality of shadowing structures interrupting an incident angle of the ion beam to define implanted and non-implanted portions of the substrate. The method further includes measuring the dose of implanted species within the substrate, determining an implanted surface area as a function of measuring the dose of implant, determining non-implanted surface area based on the implanted surface area, and obtaining the ion beam angle as a function of the non-implanted surface area.

Abstract: The invention regards a method and a system for establishing correspondence between wafers and solar cells produced from said wafers. The method comprises for each wafer and each solar cell, providing an image of the wafer, providing an image of the cell, comparing the wafer image to the cell image, upon match between a cell image and a wafer image, assigning the current cell to the current wafer. The system comprises at least one imaging device for providing images of the wafers and the cells, a processing unit for comparing a wafer image to a cell image, and upon match between a cell image and a wafer image, assigning the current cell to the current wafer, and a memory unit.

Abstract: Provided are a method of verifying line reliability and a method of fabricating a semiconductor substrate to improve the line reliability. The semiconductor device fabricating method includes: forming an interlayer insulating layer having a via hole on a semiconductor substrate; forming a seed layer on the interlayer insulating layer; performing an ammonia plasma process on the seed layer to reduce the surface of the seed layer; and forming a copper line using the surface roughness reduced seed layer.

Abstract: The present invention provides an evaluation method for a crystal defect in a silicon single crystal wafer based on an infrared laser scattering tomograph method, wherein at least, the silicon single crystal wafer is irradiated with a laser beam, and light that enters the silicon single crystal wafer is scattered by a crystal defect, and the scattered light is detected to evaluate a Direct Surface Oxide Defect (DSOD) and a void defect smaller than the DSOD in the silicon single crystal wafer. As a result, the evaluation method for a crystal defect in a silicon single crystal wafer that can simply and precisely evaluate, e.g., a small DSOD, which can be conventionally evaluated based on a Cu deposition method alone, without requiring a wasteful cost.

Abstract: A method of deprocessing a semiconductor structure is provided. The method involves removing one or more interlevel dielectric layers and one or more metal components from a frontside of the semiconductor structure. By removing the interlevel dielectric layer and the metal component, the exposed portion of the semiconductor structure can be subjected to an inspection for defects and/or other characteristics by using an inspection tool. The inspection can aid in defect reduction strategies, among other things, when applied to new technology ramp, monitoring of baseline wafer starts, customer returns, etc.

Abstract: A method of fabricating a semiconductor device according to an embodiment of the present invention includes: forming through a first material film a second material film above a semiconductor substrate; patterning the second material film to have a predetermined pattern; trimming a width of the second material film thus patterned by performing etching; transferring a pattern of the second material film having the trimmed width on the first material film by etching the first material film; measuring a width of the first material film thus etched; and adjusting the width of the first material film to a predetermined width based on the width of the first material film thus measured.

Abstract: A method of a single wafer wet/dry cleaning apparatus comprising: a transfer chamber having a wafer handler contained therein; a first single wafer wet cleaning chamber directly coupled to the transfer chamber; and a first single wafer ashing chamber directly coupled to the transfer chamber.

Abstract: The surface of a gallium nitride single crystal substrate is processed, e.g., comprising steps by planarizing the top side and the bottom side of a gallium nitride original substrate positioned on a support bed; radiating light having wavelengths ranging from 370 to 800 nanometers (nm) onto the planarized gallium nitride original substrate; measuring transmittance of the gallium nitride original substrate; and confirming whether the transmittance is within the range of 65 to 90%. A gallium nitride single crystal substrate obtained through the method of processing the surface has high transmittance ranging from 65 to 90% measured using light having wavelengths of 370 to 800 nm. The thickness ratio (DLa/DLb) of the damage layers on the both sides of the gallium nitride single crystal substrate can be obtained within the range of 0.99 to 1.01.

Abstract: A semiconductor device is fabricated to include one or more sets of calibration patterns used to measure line pitch and line focus.

Abstract: A method for monitoring precision of placement of semiconductor wafers in a semiconductor processing apparatus includes measuring thickness of an insulating film on a surface of a semiconductor substrate before etching a portion of the insulating film from the surface of the semiconductor substrate. The method further includes re-measuring the thickness of the insulating film to determine etch rates for the film at selected locations on the surface of the semiconductor wafer, and based on the determined etch rates, determining misalignment of the semiconductor wafer.

Abstract: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.

Abstract: A method of measuring thickness of a layer in an image sensor and pattern for the same are disclosed, by which layer thickness measurement of an image sensor is enabled in the course of fabrication. Embodiments relate to a method of measuring thickness of a layer in an image sensor in which a first epitaxial layer may be formed over a semiconductor substrate. A photoresist pattern may be formed by coating and patterning photoresist over the first epitaxial layer. A plurality of trenches in the first epitaxial layer may be formed by performing a dry etch on the photoresist pattern. A doped layer may be formed at a bottom of each of the trenches by implanting antimony (Sb) using the photoresist pattern as a mask. After removing the photoresist pattern, a second epitaxial layer may be formed over the first epitaxial layer including a plurality of the trenches. The thickness of the second epitaxial layer may be measured to determine the thickness of one of the doped layers.

Abstract: Methods and systems selectively irradiate structures on or within a semiconductor substrate using multiple laser beams. The structures may be laser-severable conductive links, and the purpose of the irradiation may be to sever selected links.

Abstract: Methods and systems are provided of fabricating a compound nitride semiconductor structure. A substrate is disposed within a processing chamber into which a group-III precursor and a nitrogen precursor are flowed. A layer is deposited over the substrate with a thermal chemical-vapor-deposition process using the precursors. The substrate is transferred to a transfer chamber where a temperature and a curvature of the layer are measured. The substrate is then transferred to a second processing chamber where a second layer is deposited.