For Structural Parameters, E.g., Thickness, Line Width, Refractive Index, Temperature, Warp, Bond Strength, Defects, Optical Inspection, Electrical Measurement Of Structural Dimensions, Metallurgic Measurement Of Diffusions (epo) Patents (Class 257/E21.53)
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Publication number: 20090272901Abstract: A semiconductor substrate inspection method includes: generating a charged particle beam, and irradiating the charged particle beam to a semiconductor substrate in which contact wiring lines are formed on a surface thereof, the contact wiring lines of the semiconductor substrate being designed to alternately repeat in a plane view so that one of the adjacent contact wiring lines is grounded to the semiconductor substrate and the other of the adjacent contact wiring lines is insulated from the semiconductor substrate; detecting at least one of a secondary charged particle, a reflected charged particle and a back scattering charged particle generated from the surface of the semiconductor substrate to acquire a signal; generating an inspection image with the signal, the inspection image showing a state of the surface of the semiconductor substrate; and judging whether the semiconductor substrate is good or bad from a difference of brightness in the inspection image obtained from the surfaces of the adjacent contType: ApplicationFiled: July 8, 2009Publication date: November 5, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyuki Hayashi, Takamitsu Nagai, Tomonobu Noda, Kenichi Kadota, Hisaki Kozaki
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Publication number: 20090269864Abstract: The present invention is directed to a method for manufacturing a semiconductor device by forming an ultraviolet radiation absorbing film of a silicon-rich film above a semiconductor substrate, measuring an extinction coefficient of the ultraviolet radiation absorbing film of a silicon-rich film for ultraviolet radiation, and etching the ultraviolet radiation absorbing film of a silicon-rich film under an etching condition using an oxygen gas flow rate corresponding to the extinction coefficient.Type: ApplicationFiled: October 16, 2008Publication date: October 29, 2009Inventors: Seiji Yokoyama, Yuuichirou Sekimoto, Shinichi Imada
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Publication number: 20090269863Abstract: In a semiconductor manufacturing method, a metal film is formed on a substrate and heat treated. The relationship between substrate warping and the heat treatment temperature during suicide formation is acquired (S1). A silicide film is formed by forming a metal film on a substrate and heat treating, including substrate measurement during heat treatment (S2). The relationship between substrate warping at heat treatment temperature is determined from the relationship between the warping of the substrate and the temperature for heat treatment and the temperature for heat treatment carried out on the substrate when the warping of the substrate is measured. The difference between found warping and the measured warping is calculated (S4). Whether the difference exceeds a predetermined value is determined (S5). If the difference exceeds a predetermined value, heat treatment conditions are adjusted (S8), but they not adjusted if the difference is no greater than the predetermined value.Type: ApplicationFiled: April 24, 2009Publication date: October 29, 2009Applicant: NEC ELECTRONICS CORPORATIONInventors: Ryuji Tomita, Yosuke Sugiyama
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Publication number: 20090267241Abstract: The invention relates to a substrate with a check mark and a method of inspecting position accuracy of conductive glue dispensed on the substrate. The method is implemented on the substrate having at least one transfer pad and at least one check mark arranged near the border of the transfer pad. After the conductive glue spot is dispensed on the transfer pad, the method includes first capturing an image by a video capturing element, then determining whether the conductive glue spot exist in the image and determining whether the conductive glue spot from the image matches a predetermined standard, if not, generating a report and a warning.Type: ApplicationFiled: August 8, 2008Publication date: October 29, 2009Applicant: AU OPTRONICS CORPORATIONInventor: San-Chi Wang
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Publication number: 20090263918Abstract: Methods and apparatuses are provided for calibrating eddy current sensors. A calibration curve is formed relating thickness of a conductive layer in a magnetic field to a value measured by the eddy current sensors or a value derived from such measurement, such as argument of impedance. The calibration curve may be an analytic function having infinite number terms, such as trigonometric, hyperbolic, and logarithmic, or a continuous plurality of functions, such as lines. Such curves can reduce the number of wafers used in the calibration of the sensors while providing higher accuracy over a larger thickness range. High accuracy allows the omission of optical sensors, and use of eddy current sensors for endpoint detection, transition call detection, and closed loop control in which a process parameter is changed based on the measured magnetic flux density change in one or more processing zones.Type: ApplicationFiled: April 17, 2008Publication date: October 22, 2009Applicant: Novellus Systems, Inc.Inventors: Sudeep Kumar Lahiri, Paul Franzen
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Publication number: 20090250697Abstract: Methods for detecting a void in an element portion of a semiconductor device having an element portion and a void detection structure are disclosed. As a part of the method, an insulating film is formed on a substrate, a plurality of holes is formed in the insulating film, and a metal portion is formed on the insulating film to fill the plurality of holes. The metal portion is polished until the insulating film is exposed and a recessed portion is formed in the void detection structure. It is determined if a void exists in the element portion of the semiconductor device by determining whether or not a void is exposed at a surface of the recessed portion of the void detection structure.Type: ApplicationFiled: September 29, 2008Publication date: October 8, 2009Inventor: Takayuki ENDA
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Publication number: 20090253222Abstract: An etching process state judgment method comprising: a spectral data obtaining step, in which an optical emission spectrum distribution is obtained by monitoring optical emission during an etching process of a plurality of wafers; a peak detection step, in which peaks are detected from the optical emission spectrum distribution at a specific time point during the etching process, to obtain peak characteristics; a common peak identifying step, in which peaks common to the wafers are identified among the peaks detected in the peak detection step; and a state detection step, in which the characteristics are compared regarding the common peaks, to detect a state of each wafer in the etching process. A state (anomaly or normalcy) of an etching process is detected from optical emission spectrum distribution at the time of etching process, by a simple method without assuming substances.Type: ApplicationFiled: April 3, 2009Publication date: October 8, 2009Inventors: Toshihiro Morisawa, Shoji Ikuhara, Akira Kagoshima, Daisuke Shiraishi
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Publication number: 20090253221Abstract: The total film thickness T1N of silicon oxynitride film and silicon oxide film remaining as its underlying layer is measured. A measurement target substrate is re-oxidized, and, after the re-oxidization, the total film thickness (T2N) of the silicon oxynitride film, silicon oxide film and silicon oxide film resulting from the re-oxidization on the target substrate is measured. Separately, a reference substrate provided with silicon oxide film is re-oxidized, and, after the re-oxidization, the total film thickness T2 of the silicon oxide film and silicon oxide film resulting from the re-oxidization on the reference substrate is measured. Re-oxidization rate reduction ratio RORR of the measurement target substrate is calculated by the following formula (1) from the values of total film thicknesses T1N, T2N and T2. The nitrogen concentration of the silicon oxynitride film of the target substrate is determined from the calculated re-oxidization rate reduction ratio RORR. RORR (%)={(T2?T2N)/(T2?T1N)}×100 (1).Type: ApplicationFiled: May 17, 2007Publication date: October 8, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Jiro Katsuki, Tetsuro Takahashi, Shuuichi Ishizuka
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Patent number: 7598099Abstract: Embodiments of controlling a fabrication process using an iso-dense bias are generally described herein. Other embodiments may be described and claimed.Type: GrantFiled: November 7, 2007Date of Patent: October 6, 2009Assignee: Tokyo Electron LimitedInventors: Joerg Bischoff, Heiko Weichert
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Patent number: 7598522Abstract: A semiconductor substrate includes a wafer, a first stepped structure formed of plural stepped parts formed on a surface of the wafer with a first area occupation ratio, a second stepped structure formed of plural stepped parts formed on the surface of the wafer with a second, different area occupation ratio, and an interlayer insulation film formed on the surface so as to cover the first and second stepped structures, the interlayer insulation film having a planarized top surface, wherein there are provided at least first and second film-thickness monitoring patterns for monitoring film thickness on the surface in a manner covered by the interlayer insulation film, a first pattern group is formed on the surface such that the first pattern group comprises plural patterns disposed so as to surround the first film-thickness monitoring pattern, a second pattern group is formed on the surface such that the second pattern group comprises plural patterns disposed so as to surround the second film-thickness monitoriType: GrantFiled: September 12, 2006Date of Patent: October 6, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Tetsuo Yaegashi, Kouichi Nagai
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Publication number: 20090246894Abstract: Methods and systems for fabricating and testing semiconductor devices are disclosed. In one embodiment, a method of forming a material includes providing a first workpiece, forming a material on the first workpiece using a first process condition, and measuring a defect state of the material using a test that utilizes a monochromatic light source. If the defect state is below a predetermined value, the material is formed on at least one second workpiece using the first process condition.Type: ApplicationFiled: June 8, 2009Publication date: October 1, 2009Inventor: Hong-Jyh Li
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Publication number: 20090246893Abstract: A method for evaluating a process of manufacturing a semiconductor integrated circuit including a deposition step and a polishing step after the deposition step, the method includes: dividing the semiconductor integrated circuit into a plurality of areas; determining a deposition height after the deposition step for each of the areas; and determining a risk value for each of the areas on the basis of a difference in the deposition height between each of the areas and its adjacent areas.Type: ApplicationFiled: March 20, 2009Publication date: October 1, 2009Applicant: Fujitsu LimitedInventor: Daisuke Fukuda
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Publication number: 20090239315Abstract: A method and a system for processing a test wafer in a photolithography process are provided for processing an ith layer of the test wafer, and i is a positive integer. In the present method, a compensation value is calculated according to historical compensation behaviors of an equipment, relationships between the ith layer and other layers, and offsets generated in performing a non-photolithography process on the test wafer. Then, the test wafer is processed according to the compensation value. A determination on whether the test wafer meets a design specification is then made. Rework is performed on the test wafer if the test wafer does not meet the design specification. Accordingly, an adjustable compensation value is used to process the test wafer and avoid unnecessary rework. The possibility of rework on the test wafer is reduced so as to increase the efficiency of the photolithography process.Type: ApplicationFiled: April 30, 2008Publication date: September 24, 2009Applicant: ProMOS TECHNOLOGIES INC.Inventor: Yung-Yao Lee
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Publication number: 20090236693Abstract: Films of III-nitride for semiconductor device growth are planarized using an etch-back method. The method includes coating a III-nitride surface having surface roughness features in the micron range with a sacrificial planarization material such as an appropriately chose photoresist. The sacrificial planarization material is then etched together with the III-nitride roughness features using dry etch methods such as inductivel coupled plasma reactive ion etching. By closely matching the etch rates of the sacrificial planarization material and the III-nitride material, a planarized III-nitride surface is achieved. The etch-back process together with a high temperature annealing process yields a planarize III-nitride surface with surface roughness features reduced to the nm range. Planarized III-nitride, e.g., GaN, substrates and devices containing them are also provided.Type: ApplicationFiled: February 2, 2007Publication date: September 24, 2009Applicant: Trustees of Boston UniversityInventors: Theodore D. Moustakas, Adrian D. Williams
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Publication number: 20090230493Abstract: A solid-state imaging device includes: a solid-state imaging element having a light-receiving area; a transparent member disposed so as to oppose the light-receiving area; a supporting member configured to support the transparent member; a first mark disposed at either an upper surface of the transparent member or an upper surface of the supporting member; and a second mark disposed at an outer side of the light-receiving area, at an upper surface of the solid-state imaging element.Type: ApplicationFiled: March 10, 2009Publication date: September 17, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Naoyuki WATANABE, Takao OHNO, Susumu MORIYA, Izumi KOBAYASHI
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Publication number: 20090233385Abstract: Before a plasma doping process is performed, there is generated a plasma of a gas containing an element belonging to the same group in the periodic table as the primary element of a silicon substrate 9, e.g., a monosilane gas, in a vacuum chamber 1. Thus, the inner wall of the vacuum chamber 1 is covered with a silicon-containing film. Then, a plasma doping process is performed on the silicon substrate 9.Type: ApplicationFiled: October 4, 2007Publication date: September 17, 2009Applicant: PANASONIC CORPORATIONInventors: Tomohiro Okumura, Hisao Nagai, Yuichiro Sasaki, Katsumi Okashita, Hiroyuki Ito, Bunji Mizuno
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Publication number: 20090233109Abstract: The present invention is a method for producing a bonded wafer, comprising at least: bonding a base wafer serving as a support substrate to a bond wafer made of a silicon single crystal via an insulator film or directly bonding the wafers to provide a bonded wafer; and reducing a thickness of the bond wafer to form a thin film made of the silicon single crystal on the base wafer, wherein the thickness of the bonded wafer is reduced based on at least surface grinding while measuring the thickness of the bond wafer, and surface grinding with respect to the bond wafer is stopped when the thickness of the bond wafer reaches a target thickness. As a result, the method for producing a bonded wafer enabling a silicon single crystal thin film to precisely have a desired film thickness, a bonded wafer, and a surface grinding machine enabling a silicon single crystal thin film to precisely have a desired film thickness are provided.Type: ApplicationFiled: March 29, 2006Publication date: September 17, 2009Applicant: SHIN-ETSU HANDOTAI CO., LDT.Inventors: Keiichi Okabe, Yoshikazu Tachikawa, Susumu Miyazaki, Sigeyuki Yoshizawa, Tokio Takei
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Patent number: 7588949Abstract: The optimization of an optical metrology model for use in measuring a wafer structure is evaluated. An optical metrology model having metrology model variables, which includes profile model parameters of a profile model, is developed. One or more goals for metrology model optimization are selected. One or more profile model parameters to be used in evaluating the one or more selected goals are selected. One or more metrology model variables to be set to fixed values are selected. One or more selected metrology model variables are set to fixed values. One or more termination criteria for the one or more selected goals are set. The optical metrology model is optimized using the fixed values for the one or more selected metrology model variables. Measurements for the one or more selected profile model parameters are obtained using the optimized optical metrology model. A determination is then made as to whether the one or more termination criteria are met by the obtained measurements.Type: GrantFiled: January 29, 2007Date of Patent: September 15, 2009Assignee: Tokyo Electron LimitedInventors: Vi Vuong, Emmanuel Drege, Shifang Li, Junwei Bao
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Publication number: 20090227046Abstract: An insulating film is formed on a main surface of a substrate. A conductive film is formed on the insulating film. A lower layer resist film, an intermediate layer, an anti-reflection film and an upper layer resist film are formed on the conductive film. A focal point at a time of exposure is detected by detecting a height of the upper layer resist film. In detecting the focal point at the time of exposure, a focal point detection light is radiated on the upper layer resist film. After detecting the focal point, the upper layer resist film is exposed and developed thereby to form a resist pattern. With the resist pattern as a mask, the intermediate layer and the anti-reflection film are patterned, and the lower layer resist film is developed. With these patterns as a mask, the conductive film is etched thereby to form a gate electrode.Type: ApplicationFiled: May 15, 2009Publication date: September 10, 2009Applicant: Renesas Technology Corp.Inventor: Takeo Ishibashi
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Publication number: 20090227049Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.Type: ApplicationFiled: May 4, 2009Publication date: September 10, 2009Inventors: Tony P. Chiang, David E. Lazovsky, Thomas R. Boussie, Alexander Gorer
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Publication number: 20090227048Abstract: Disclosed is a die-bonding method having pick-and-probe features after wafer sawing where at least a die is probed and sorted according to different grades during a pick-and-place step performed after wafer sawing. A suction nozzle having a plurality of probes is utilized to probe the electrical terminals of the die. After picking, the suction nozzle is moved on a common moving path and the picked die is tested through the suction nozzle. The picked-and-probed die is moved and die-bonded to a die carrier loaded in a corresponding one of a plurality of die-bonding areas by moving the Suction nozzle on a chosen sorting path. Therefore, the die is probed and sorted during die-bonding processes. Higher graded dice at a same level are assembled on a same die carrier to form a higher graded semiconductor package.Type: ApplicationFiled: March 4, 2008Publication date: September 10, 2009Inventors: Li-Chih FANG, Wen-Jeng Fan, Nan-Chun Lin
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Publication number: 20090221105Abstract: In mass production of CMIS integrated circuit devices or the like, electric characteristics, such as Vth (threshold voltage) or the like, disadvantageously vary due to variations in gate length of the MISFET. This problem has become serious because of a short channel effect. In order to solve the problem, various kinds of feed-forward techniques have been studied in which a subsequent variation factor process is regulated to be reversed with respect to variations in a previous variation factor process so as to cause these variation factors to cancel each other out. Since the feed-back technique has an effect of the cancellation process over the entire system, the technique can be relatively easily applied to a product with a single type of MISFE, but is difficult to be applied to a product equipped with a plurality of types of MISFETs.Type: ApplicationFiled: February 26, 2009Publication date: September 3, 2009Inventors: Masanobu Hishiki, Yaichiro Miura, Hiroshi Kawashima, Katsuhiro Mitsuda
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Publication number: 20090221103Abstract: In the fabrication of a semiconductor integrated circuit device, a 2D-3D inspection technique for solder printed on a substrate is provided which permits easy preparation of data and easy visual confirmation of a defective portion. In a substrate inspecting step, first, a 3D inspection is performed, followed by execution of 2D inspection, whereby a 2D picked-up image of the portion of a pad determined to be defective can be displayed on a larger scale simultaneously with the end of inspection, thereby providing an environment for efficient visual confirmation of the defect. Further, by subjecting a raw substrate to measurement at the time of preparing inspection data, a relation between an original height measurement reference generated automatically by the inspection system and the height of a pad upper surface is checked, whereby it is possible to measure the height and volume of printed solder based on the pad upper surface.Type: ApplicationFiled: May 11, 2009Publication date: September 3, 2009Inventor: Norio Watanabe
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Patent number: 7582884Abstract: When a space, sandwiched by large patterns having a predetermined size or more, is exposed using a charged particle beam, the space sandwiched by the large patterns is exposed using a common block mask having the space and edge portions of the large patterns on both sides of the space, and portions other than the edge portions of the large patterns on both sides are exposed by a variable rectangular beam or by using another block mask.Type: GrantFiled: April 13, 2005Date of Patent: September 1, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Yasushi Takahashi
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Publication number: 20090215204Abstract: A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed.Type: ApplicationFiled: May 6, 2009Publication date: August 27, 2009Inventors: Hideharu KOBASHI, Hiroshi Maki, Masayuki Mochizuki, Yoshiaki Makita
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Publication number: 20090197355Abstract: A method for manufacturing a semiconductor device that controls the influence of a thickness of a stopper film even if there is a change in the thickness of the stopper film by measuring the thickness prior to etching to a predetermined thickness.Type: ApplicationFiled: February 3, 2009Publication date: August 6, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Masanori Terahara
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Publication number: 20090197359Abstract: A method for evaluating a shape change of a semiconductor wafer is provided. The method comprises acquiring unconstrained shape data of shape data of the semiconductor wafer being placed on a reference surface in a unconstrained state; acquiring constrained shape data of shape data of the semiconductor wafer being constrained along the reference surface in a constrained state; and comparing the unconstrained shape data and the constrained shape data. A method for manufacturing the semiconductor wafer utilizing a result of the evaluation of the wafer is also provided.Type: ApplicationFiled: January 29, 2009Publication date: August 6, 2009Inventors: Kazuhiro Iriguchi, Toshiyuki Isami, Kouhei Kawano
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Publication number: 20090194865Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.Type: ApplicationFiled: September 24, 2008Publication date: August 6, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
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Publication number: 20090191651Abstract: A positioning apparatus comprises a detector which detects the mark and outputs a mark signal and a controller. The controller includes a calculating unit which calculates position data of the mark based on the mark signal, a processing unit which calculates a parameter representing a displacement of the object, based on the mark signal and the position data of the mark, and a positioning controller which controls the positioning of the object, based on the position information of the object corrected by using the parameter calculated by said processing unit. The processing unit calculates a feature value, calculates a degree of influence that the feature value exerts on a displacement of the mark, corrects the calculated position data of the mark based on the calculated degree of influence, and statistically calculates the corrected position data of the mark, thereby calculating a parameter representing a displacement of the object.Type: ApplicationFiled: January 22, 2009Publication date: July 30, 2009Applicant: CANON KABUSHIKI KAISHAInventor: Shinichi Egashira
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Publication number: 20090186425Abstract: A semiconductor substrate (1) is secured by suction to a rear face (1b) of a supporting face (11a) of a substrate supporting table (11). In this event, the thickness of the semiconductor substrate (1) is made fixed by planarization on the rear face (1b), and the rear face (1b) is forcibly brought into a state free from undulation by the suction to the supporting face (11a), so that the rear face (1b) becomes a reference face for planarization of a front face (1a). In this state, a tool (10) is used to cut surface layers of Au projections (2) and a resist mask (12) on the front face (1a), thereby planarizing the Au projections (2) and the resist mask (12) so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.Type: ApplicationFiled: March 30, 2009Publication date: July 23, 2009Applicant: FUJITSU LIMITEDInventors: Masataka MIZUKOSHI, Yoshikatsu ISHIZUKI, Kanae NAKAGAWA, Keishiro OKAMOTO, Kazuo TESHIROGI, Taiji SAKAI
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Publication number: 20090186427Abstract: A system and method of characterizing a parameter of an ultra thin film, such as a gate oxide layer. A system is disclosed that includes a structure having a pseudo substrate positioned below an ultra thin film, wherein the pseudo substrate includes an optical mirror for enhancing an optical response; and a system for characterizing the ultra thin film by applying a light source to the ultra thin film and analyzing the optical response.Type: ApplicationFiled: January 17, 2008Publication date: July 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shahin Zangooie, Lin Zhou, Sean D. Burns
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Publication number: 20090186429Abstract: A computer implemented method for correcting a mask pattern includes: predicting a displacement of a device pattern by using a mask pattern to form the device pattern and a variation of a process condition; determinating an optical proximity correction value so that the displacement falls within a displacement tolerance of the device pattern; and correcting the mask pattern using the optical proximity correction value.Type: ApplicationFiled: February 11, 2009Publication date: July 23, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Toshiya Kotani, Satoshi Tanaka, Soichi Inoue
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Publication number: 20090186428Abstract: An optical critical dimension measuring method, applicable in measuring a pattern, that includes a plurality of polysilicon layers, of a device, is provided. The method includes obtaining a real curve corresponding to the to-be-measured device. Then, determining whether an ion implantation process has been performed on the polysilicon layers, a different module is selected. A correlation process is performed according to the selected module to generate a theoretical curve that correlates with the real curve to obtain a plurality of parameters corresponding to the theoretical curve.Type: ApplicationFiled: January 22, 2008Publication date: July 23, 2009Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Chi Huang, Wen-Yi Teng
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Publication number: 20090179307Abstract: An integrated circuit system that includes: providing a substrate and a material layer; measuring a parameter of the material layer; and correlating the thickness of an anti-reflective layer to the measured parameter of the material layer for critical dimension control.Type: ApplicationFiled: January 15, 2008Publication date: July 16, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Wenzhan Zhou, Jasper Goh, Hui Peng Koh, Jung Yu Hsieh, Meisheng Zhou
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Publication number: 20090181477Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.Type: ApplicationFiled: March 24, 2009Publication date: July 16, 2009Applicant: Synopsys, Inc.Inventors: Tsu-Jae King, Victor Moroz
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Publication number: 20090174042Abstract: An over-molded leadframe (e.g., a Quad Flat No-lead (QFN)) package capable of operating at frequencies in the range of about five gigahertz (GHz) to about 300 GHz and a method of making the over-molded leadframe package are disclosed. The over-molded leadframe package includes a capacitance lead configured to substantially reduce and/or offset the inductance created by one or more wirebonds used to connect an integrated circuit (IC) chip on the package to an input/output (I/O) lead. The IC chip is connected to the capacitance lead via one or more wirebonds, and the capacitance lead is then connected to the I/O lead via at least a second wirebond. Thus, inductance created by the one or more wirebonds on the package is substantially reduced and/or offset by the capacitance lead prior to a signal being output by the package and/or received by the IC chip.Type: ApplicationFiled: February 9, 2009Publication date: July 9, 2009Applicant: VIASAT, INC.Inventors: Richard S. Torkington, Michael R. Lyons, Kenneth V. Buer
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Publication number: 20090170222Abstract: A method for semiconductor processing is provided, wherein a semiconductor wafer having undergone polishing is provided. The semiconductor wafer has an active region positioned between one or more moat regions, wherein the one or more moat regions have an oxide disposed therein. A top surface of the active region is recessed from a top surface of the moat region, therein defining a step having a step height associated therewith. A step height is measured, and a photoresist is formed over the semiconductor wafer. A modeled step height is further determined, wherein the modeled step height is based on the measured step height and a desired critical dimension of the photoresist. A dosage of energy is determined for patterning the photoresist, wherein the determination of the dosage of energy is based, at least in part, on the modeled step height. The photoresist is then patterned using the determined dosage of energy.Type: ApplicationFiled: November 25, 2008Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventors: Brian Douglas Reid, James David Bernstein, Hongyu Yue, Howie Hui Yang, Mark Boehm
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Publication number: 20090160027Abstract: Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.Type: ApplicationFiled: December 19, 2007Publication date: June 25, 2009Inventors: O Seo Park, Wai-Kin Li
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Publication number: 20090159937Abstract: Dimensions of structures in integrated circuits are shrinking with each new fabrication technology generation. Maintaining control of profiles of structures in transistors and interconnects is becoming more important to sustaining profitable integrated circuit production facilities. Measuring profiles of structures with many elements in integrated circuits, such as MOS transistor gates with recessed regions for Si—Ge epitaxial layers, is not cost effective for the commonly used metrology techniques: SEM, TEM and AFM. Scatterometry is technically unfeasible due to the number of elements and optical constants. The instant invention is a simplified scatterometry structure which reproduces the profiles of a structure to be profiled in a simpler structure that is compatible with conventional scatterometric techniques. A method of fabricating a transistor and an integrated circuit using the inventive simplified scatterometry structure are also disclosed.Type: ApplicationFiled: March 14, 2008Publication date: June 25, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Vladimir Alexeevich Ukraintsev, Craig Lawrence Hall
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Patent number: 7550311Abstract: Provided is near-field optical probe including: a cantilever arm support portion that is formed of a lower silicon layer of a silicon-on-insulator (SOI) substrate, the cantilever arm support portion having a through hole formed therein at a side of the lower silicon layer; and a cantilever arm forming of a junction oxidation layer pattern and an upper silicon layer pattern on the SOI substrate that are supported on an upper surface of the lower silicon layer and each have a smaller hole than the through hole, a silicon oxidation layer pattern having a tip including an aperture at a vertical end, corresponding with the hole on the upper silicon layer pattern, and an optical transmission prevention layer that is formed on the silicon oxidation layer pattern and does not cover the aperture.Type: GrantFiled: December 5, 2006Date of Patent: June 23, 2009Assignee: Electronics and Telecommunications Research InstituteInventors: Eunkyoung Kim, Sung Q Lee, Kang Ho Park
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Publication number: 20090155935Abstract: Systems and methods for scribing a semiconductor wafer with reduced or no damage or debris to or on individual integrated circuits caused by the scribing process. The semiconductor wafer is scribed from a back side thereof. In one embodiment, the back side of the wafer is scribed following a back side grinding process but prior to removal of back side grinding tape. Thus, debris generated from the scribing process is prevented from being deposited on a top surface of the wafer. To determine the location of dicing lanes or streets relative to the back side of the wafer, the top side of the wafer is illuminated with a light configured to pass through the grinding tape and the wafer. The light is detected from the back side of the wafer, and the streets are mapped relative to the back side. The back side of the wafer is then cut with a saw or laser.Type: ApplicationFiled: February 20, 2009Publication date: June 18, 2009Applicant: ELECTRO SCIENTIFIC INDUSTRIES, INC.Inventors: Richard S. Harris, Ho W. Lo
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Publication number: 20090148964Abstract: A method for determining conditions for forming a dielectric SiOCH film, includes: (i) forming a dielectric SiOCH film on a substrate under conditions; (ii) evaluating the conditions using a ratio of Si—CH3 bonding strength to Si—O bonding strength of the film as formed in step (i); (iii) if the ratio is 2.50 % or higher, confirming the conditions, and if the ratio is less than 2.50 %, changing the conditions by changing at least one of the susceptor temperature, the distance between upper and lower electrodes, the RF power, and the curing time; and (iv) repeating steps (i) to (iii) until the ratio is 2.50 % or higher.Type: ApplicationFiled: December 7, 2007Publication date: June 11, 2009Applicant: ASM JAPAN K.K.Inventors: Naoto Tsuji, Kiyohiro Matsushita, Manabu Kato, Noboru Takamure
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Patent number: 7544520Abstract: A method for applying a heat insulation layer (11, 12, 13) or a metallic protective layer to a thermally stressed component (200) having a basic material (10) in order to eliminate local damage (14) or an untreated place in the coating, includes, in a first step, pretreating the local damage (14) or untreated place, and, in a second step, applying layers (17, 18) necessary for eliminating the local damage (14) or untreated place. A markedly improved lifetime of the processed component can be achieved in that, within the first step, the edge regions (15) of the layers (11, 12, 13) ending at the local damage (14) or untreated place are processed so that they form uniformly sloped and terrace-shaped edge regions (16). Furthermore, a precharacterization of the entire coated region of the operationally stressed component or critical places by FSECT makes it possible to reduce the risk in terms of otherwise overlooked layer regions, the remaining lifetime of which would not persist for the following operating time.Type: GrantFiled: October 27, 2006Date of Patent: June 9, 2009Assignee: ALSTOM Technology Ltd.Inventors: Thomas Duda, Stefan Kiliani, Alexander Stankowski, Frigyes Szücs
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Publication number: 20090140247Abstract: The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating film and a second insulating film having a first concave portion above the light shielding film in the first region and an interconnect hole having a via hole and a second concave portion in the second region in the second insulating film on the first insulating film, wherein an area of the light shielding film is overlapping an area of the first plurality of concave portions.Type: ApplicationFiled: November 26, 2008Publication date: June 4, 2009Applicant: NEC Electronics CorporationInventor: Hidetaka NAMBU
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Publication number: 20090140390Abstract: A GaAs semiconductor substrate includes a main surface (10m) having an inclined angle of 6° to 16° with respect to a (100) plane (10a), and a concentration of chlorine atoms on the main surface (10m) is not more than 1×1013 cm?2. Further, a method of manufacturing a GaAs semiconductor substrate includes a polishing step of polishing a GaAs semiconductor wafer, a first cleaning step of cleaning the polished GaAs semiconductor wafer, an inspection step of inspecting a thickness and a main surface flatness of the GaAs semiconductor wafer subjected to the first cleaning, and a second cleaning step of cleaning the inspected GaAs semiconductor wafer with one of an acid other than hydrochloric acid and an alkali.Type: ApplicationFiled: December 2, 2008Publication date: June 4, 2009Applicant: Sumitomo Electric Industries, Ltd.Inventor: Takayuki NISHIURA
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Publication number: 20090140246Abstract: By forming a large metal pad and removing any excess material thereof, a pronounced recessed surface topography may be obtained, which may also affect the further formation of a metallization layer of a semiconductor device, thereby increasing the probability of maintaining metal residues above the recessed surface topography. Consequently, by providing test metal lines in the area of the recessed surface topography, the performance of a respective CMP process may be estimated with increased efficiency.Type: ApplicationFiled: July 1, 2008Publication date: June 4, 2009Inventors: Michael Grillberger, Matthias Lehr
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Patent number: 7537941Abstract: Embodiments of the invention provide a method, structure, service, etc. for variable overlap of dummy shapes for improved rapid thermal anneal uniformity. A method of providing uniform temperatures across a limited region of a wafer during a rapid thermal anneal process comprises determining a first reflectivity in a first portion of the limited region by measuring a density of first structures in the first portion. Next, the method determines a second reflectivity in a second portion of the limited region by measuring a density of second structures in the second portion. Specifically, the first structures comprise diffusion fill shapes and polysilicon conductor fill shapes (non-active dummy structures); and, the second structures comprise active circuit structures.Type: GrantFiled: June 7, 2006Date of Patent: May 26, 2009Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Howard S. Landis, Edward J. Nowak
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Patent number: 7538443Abstract: A system and method for identifying misalignments in an overlapping region of a stitched circuit in an integrated circuit fabrication process. The method comprises: creating a first circuit using a reference mask, wherein first circuit includes a first part of an offset dependent resistor structure in the overlapping region; creating a second circuit using a secondary mask, wherein the second circuit includes a second part of the offset dependent resistor structure in the overlapping region, wherein the offset dependent resistor structure includes a plurality of nubs that interconnect the first part and the second part of theis offset dependent resistor structure; measuring a resistance across the offset dependent resistor structure; and determining an amount of misalignment based on the measured resistance.Type: GrantFiled: June 25, 2004Date of Patent: May 26, 2009Assignee: NXP B.V.Inventor: Joseph M. Amato
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Publication number: 20090130782Abstract: A method is provided for manufacturing a semiconductor device that includes a multilayer wiring structure in which insulating layers and wiring layers each with a plurality of conductor lines are alternately stacked on each other. The method includes steps of forming a first wiring layer on a first insulating layer, detecting a defect in the first wiring layer on the first insulating layer, and determining whether or not the defect is to be irradiated with a focused ion beam, according to a detection result. If it is determined that the defect is to be irradiated, the defect is irradiated with a focused ion beam and then a second insulating layer is formed on the first wiring layer disposed on the first insulating layer. If it is determined that the defect is not to be irradiated with a focused ion beam, the second insulating layer is formed on the first wiring layer disposed on the first insulating layer without irradiating the defect.Type: ApplicationFiled: November 7, 2008Publication date: May 21, 2009Applicant: CANON KABUSHIKI KAISHAInventors: Masatsugu Itahashi, Kouhei Hashimoto, Nobuhiko Sato, Seiichi Tamura, Hiroshi Yuzurihara
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Publication number: 20090124027Abstract: A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.Type: ApplicationFiled: January 13, 2009Publication date: May 14, 2009Inventors: Sebastian Schmidt, Thomas Schafbauer, Hang Yip Liu, Yayi Wei