Abstract: A manufacturing method of a semiconductor device is provided to improve the reliability of electrical coupling of the semiconductor device. The manufacturing method includes the steps of (a) laminating a main conductive film (base film) and a stopper insulating film (film to be measured) above the main conductive film, over a main surface of a semiconductor substrate, (b) forming an opening in the stopper film, (c) applying an electron beam (excitation beam) to the opening to emit characteristic X-rays, and (d) detecting the characteristic X-rays to determine the presence or absence, or thickness of the stopper insulating film at the bottom of the opening based on detection result of the characteristic X-rays. In the step (d), the presence or absence, or thickness of the stopper film is determined by a ratio of element components contained in the characteristic X-rays.

Abstract: A photovoltaic device is made using a method and a system disclosed herein. The method may comprise: providing a web of photovoltaic material; providing a web of interconnect material; cutting the web of photovoltaic material into a plurality of photovoltaic cells; cutting the web of interconnect material into a plurality of interconnects; providing a respective one of the plurality of interconnects between adjacent photovoltaic cells to electrically connect a first string of photovoltaic cells in series; and laminating the first string of photovoltaic cells which are electrically connected in series between a top laminating sheet and a bottom laminating sheet. The system may comprise: a first conveyor, an optical inspection apparatus, a removal apparatus, a sorter, a second conveyor, and an assembly apparatus configured to place an interconnect between adjacent photovoltaic cells to electrically connect a first string of photovoltaic cells in series.

Abstract: A set of optical rule checker (ORC) markers are identified in a simulated lithographic pattern generated for a set of data preparation parameters and lithographic processing conditions. Each ORC marker identifies a feature in the simulated lithographic pattern that violates rules of the ORC. A centerline is defined in each ORC marker, and a minimum dimension region is generated around each centerline with a minimum width that complies with the rules of the ORC. A failure region is defined around each ORC marker by removing regions that overlap with the ORC marker from the minimum dimension region. The areas of all failure regions are added to define a figure of demerit, which characterizes the simulated lithographic pattern. The figure of demerit can be evaluated for multiple simulated lithographic patterns or iteratively decreased by modifying the set of data preparation parameters and lithographic processing conditions.

Abstract: Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer over the blocking layer; and inspecting optically at least one wavelength at least one inspection area, the blocking layer extending substantially throughout the inspection area. An inspection method including adhering an optical absorbing layer to a semiconductor process wafer, where the absorbing layer is configured to substantially absorb a range of wavelengths of light; applying at least one layer over the absorbing layer; and inspecting optically at least one wavelength at least one inspection area of the process wafer. A manufacturing method including ascertaining if a defect is present within a photoresist layer, and changing a semiconductor manufacturing process to prevent the defect, if the defect is present.

Abstract: A method of evaluating damage of a compound semiconductor member, comprising: a step of performing spectroscopic ellipsometry measurement on a surface of the compound semiconductor member; and a step of evaluating damage on the surface of the compound semiconductor member, using a spectrum in a wavelength band containing a wavelength corresponding to a bandgap of the compound semiconductor member, in a spectrum of an optical constant obtained by the spectroscopic ellipsometry measurement.

Abstract: A computer implemented method of monitoring a polishing process includes, for each sweep of a plurality of sweeps of an optical sensor across a substrate undergoing polishing, obtaining a plurality of current spectra, each current spectrum of the plurality of current spectra being a spectrum resulting from reflection of white light from the substrate, for each sweep of the plurality of sweeps, determining a difference between each current spectrum and each reference spectrum of a plurality of reference spectra to generate a plurality of differences, for each sweep of the plurality of sweeps, determining a smallest difference of the plurality of differences, thus generating a sequence of smallest difference, and determining a polishing endpoint based on the sequence of smallest differences.

Abstract: A method of initiating molecular bonding, comprising bringing one face of a first wafer to face one face of a second wafer and initiating a point of contact between the two facing faces. The point of contact is initiated by application to one of the two wafers, for example, using a bearing element of a tool, of a mechanical pressure in the range from 0.1 MPa to 33.3 MPa.

Abstract: An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged.

Abstract: A method of inspecting a semiconductor substrate having a back surface and including at least one piece of metal embedded in the substrate comprises directing measuring light towards the back surface of the substrate and detecting a portion of the measuring light received back from the substrate. The method also includes determining a distance between the piece of metal and the back surface based upon the detected measuring light received back from the substrate.

Abstract: A method for process control is disclosed. The method includes performing an etching process on a semiconductor substrate forming a structure and a test structure having a pattern and a releasing mechanism coupled to the pattern; and monitoring the pattern of the test structure to determine whether the etching process is complete.

Abstract: A method of manufacturing a surface-emitting laser element having a light-emitting mesa structure with an emitting area including a high-reflectance portion and a low-reflectance portion includes forming a layered body that includes a lower reflecting mirror, a cavity structure, and an upper reflecting mirror on a substrate; forming a first area on an upper surface of the layered body; forming a second area having the same size as the first area on the upper surface of the layered body; forming a light-emitting mesa structure and a monitoring-mesa structure by etching the first area and the second area, respectively; forming a confinement structure including a current passage area surrounded by an oxide in the light-emitting mesa structure and the monitoring-mesa structure; and measuring the size of the current passage area of the monitoring-mesa structure.

Abstract: The disclosure relates to a method of aligning a set of patterns on a substrate, which includes depositing on the substrate's surface a set of silicon nanoparticles, which includes a set of ligand molecules including a set of carbon atoms. The method involves forming a first set of regions where the nanoparticles are deposited, while the remaining portions of the substrate surface define a second set of regions. The method also includes densifying the set of nanoparticles into a thin film to form a set of silicon-organic zones on the substrate's surface, wherein the first and the second set of regions have respectively first and second reflectivity values, such that the ratio of the second reflectivity value to the first reflectivity value is greater than about 1.1.

Abstract: A method for aligning a wafer stack includes providing a wafer stack including a top wafer with a top mark and a bottom wafer with a bottom mark in particular the top mark and the bottom mark capable of corresponding to each other; adjusting a relative position between the top wafer and the bottom wafer so that the top mark and the bottom mark are in contact with each other; applying an electrical signal on the top mark to obtain an electrical reading and optimizing the electrical reading to substantially align the wafer stack.

Abstract: A method of distinguishing a set of highly doped regions from a set of lightly doped regions on a silicon substrate is disclosed. The method includes providing the silicon substrate, the silicon substrate configured with the set of lightly doped regions and the set of highly doped regions. The method further includes illuminating the silicon substrate with an electromagnetic radiation source, the electromagnetic radiation source transmitting a wavelength of light above about 1100 nm. The method also includes measuring a wavelength absorption of the set of lightly doped regions and the set of heavily doped regions with a sensor, wherein for any wavelength above about 1100 nm, the percentage absorption of the wavelength in the lightly doped regions is substantially less than the percentage absorption of the wavelength in the heavily doped regions.

Abstract: According to one embodiment, a droplet dispensing control method includes detecting an amount of positional deviation between a stage on which a substrate is mounted and a template as a template positional deviation amount and detecting an amount of positional deviation between a movement direction of the stage and a nozzle array direction as a nozzle positional deviation amount. The method further includes calculating a stage movement direction correction value and an ejection timing correction value of the imprint material as correction values for eliminating the positional deviation of the landing position of the imprint material. The method further includes controlling the movement direction of the stage using the stage movement direction correction value and controlling the ejection timing of the imprint material using the ejection timing correction value.

Abstract: A semiconductor device manufacture method has the steps of: (a) forming a semiconductor device structure in a chip and alignment marks, respectively in a semiconductor wafer; (b) forming a workpiece layer above the semiconductor wafer; (c) exposing the alignment marks; (d) coating an electron beam resist film on the workpiece layer; (e) scanning the alignment marks with an electron beam to obtain plural position information on the alignment marks and obtaining differences between the plural position information; (f) removing abnormal values of position information in accordance with the difference between the plural position information; and (g) performing an electron beam exposure in accordance with plural position information of the alignment marks with the abnormal value being removed. An alignment mark detection precision can be improved in electron beam exposure.

Abstract: Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants.

Abstract: A system and method for uniform deposition of material layers on wafers in a rotating disk chemical vapor deposition reaction system is provided, wherein one or more substrates are rotated on a carrier about an axis while maintaining surfaces of the one or more substrates substantially perpendicular to the axis of rotation and facing in an upstream direction along the axis of rotation. During rotating a first gas is discharged in the downstream direction towards the one or more substrates from a first set of gas inlets. A second gas is discharged in the downstream direction towards the one or more substrates from at least one movable gas injector, and the at least one movable gas inlet is moved with a component of motion in a radial direction towards or away from the axis of rotation.

Abstract: When bump electrodes 26 of a semiconductor light emitting element 2 and electrode portions 21 of a mounting board 3 are joined to each other, power is supplied to the electrode portions 21 of the mounting board 3 to allow the semiconductor light emitting element 2 to emit light, the optical properties of the semiconductor light emitting element 2 having emitted light are detected, and the detected value of optical properties is processed to obtain the joining state of the bump electrodes 26 of the semiconductor light emitting element 2 and the electrode portions 21 of the mounting board 3, so that the completion of joining is determined. Thus, the semiconductor light emitting element can be satisfactorily joined to the electrode portions on the mounting board via the metal electrodes formed on the semiconductor light emitting element.

Abstract: A semiconductor device that is resin-sealed in a wafer level after a rewiring layer forming process and a metal post forming process forming a metal post are performed on a semiconductor substrate of the semiconductor device includes devices formed on the semiconductor substrate. Further all of the devices are disposed in respective positions other than positions overlapping a peripheral border of the metal post when viewed from a top of the semiconductor substrate.

Abstract: A chip on film (COF) package and a method for manufacturing same are provided. The COF package comprises a base film, a semiconductor chip mounted on the base film, a signal-inputting portion mounted on the base film, a first passive element mounted on the base film and comprising first and second terminals and a first signal line formed on the base film and connecting the first passive element to the semiconductor chip, wherein the first signal line comprises a connection pad connected to the first terminal of the first passive element and a first test line connected to the signal-inputting portion.

Abstract: The present invention provides devices capable of testing the electrical performance of thin-film transistor backplane arrays and methods for their use.

Abstract: Provided is an apparatus for laser scribing. The laser scribing apparatus may include: a first laser emitter to emit a laser for a thickness measurement while moving towards a first axial direction of a substrate where a plurality of light emitting devices is formed; a laser receiver to receive a reflected laser when the laser emitted from the first laser emitter is reflected from the substrate; a thickness measurement unit to measure a thickness of the substrate based on a strength of the leaser received by the laser receiver; and a second laser emitter to generate a scribing line on the substrate by emitting a laser towards a first axial direction and a second axial direction of the substrate while adjusting a laser emission location based on the measured thickness.

Abstract: A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.

Abstract: A chemical mechanical polishing method is provided. The chemical mechanical polishing method includes steps of providing a plurality of semiconductor elements to be polished, obtaining a respective dimension of the each semiconductor element to be polished, and polishing the each semiconductor element according to the respective dimension thereof.

Abstract: A semiconductor device may be designed in the following manner. A stacked layer of a silicon oxide film and an organic film is provided over a substrate, deuterated water is contained in the organic film, and then a conductive film is formed in contact with the organic film. Next, an inert conductive material that does not easily generate a deuterium ion or a deuterium molecule is selected by measuring the amount of deuterium that exists in the silicon oxide film.

Abstract: According to one embodiment, a template for manufacturing a memory cell array comprising a relievable area and a redundant area replaceable with the relievable area is to be inspected. First, based on a defect position of a defect-detected template and position information on a relievable area, a decision is made as to whether the detected defect is positioned within the relievable area. A decision is made as to whether the number of defect-detected relievable areas exceeds the preset permissible number. When the detected defect is positioned outside the relievable area or when the number of defect-detected relievable areas exceeds the permissible number, a notification that the template has failed the inspection is output.

Abstract: In order to solve the above problem, provided is an electronic component having an authentication pattern formed on an exposed surface, in which the authentication pattern includes a base section including a resin and colored particles having a hue that can be identified in the base section, and the colored particles are dispersed so as to form dotted pattern in the base section.

Abstract: A metrology system for analyzing a semiconductor device on a substrate can include a metrology sensor.

Abstract: A laminated body, comprising: a supporting body having a concave-convex surface; and a semiconductor layer laminated on a surface of the supporting body, wherein a part of the supporting body includes a layer thickness measurement portion for optically measuring a layer thickness of the semiconductor layer, and the layer thickness measurement portion includes a reduced surface roughness region whose surface roughness is smaller than that of the concave-convex surface.

Abstract: An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Abstract: Embodiments of the invention generally provide apparatus and methods of screen printing a pattern on a substrate. In one embodiment, a patterned layer is printed onto a surface of a substrate along with a plurality of alignment marks. The locations of the alignment marks are measured with respect to a feature of the substrate to determine the actual location of the patterned layer. The actual location is compared with the expected location to determine the positional error of the patterned layer placement on the substrate. This information is used to adjust the placement of a patterned layer onto subsequently processed substrates.

Abstract: Provided are a light-emitting tube and lamp that can maintain a high lamp efficiency even if the lamp power fluctuate. The light-emitting tube (3) comprises a heremetically sealed glass tube (19), and electrodes (17, 18) are disposed at both ends (13, 15) of said glass tube. The glass tube (19) has a bulging part (37) in a center area that roughly corresponds to the center of the interelectrode region between the filament coils (25, 26) at the electrodes (17, 18). When the light-emitting tube is lit at a rated lamp power, the lowest-temperature point is in an end region outside of the interelectrode region, and when lit at a prescribed lamp power below the rated lamp power, said lowest-temperature point is in the bulging part (37). The lamp comprises the abovementioned light-emitting tube (3) and a socket that electrically connects to the electrodes (17, 18) inside the light-emitting tube (3).

Abstract: A method and apparatus for dispensing a volume of die attach adhesive onto a surface can include an optical system which images the dispensed volume of die attach adhesive. A two-dimensional area covered by the die attach adhesive and a die attach dispense pressure can be used as a comparison with a reference value to determine whether the volume of die attach adhesive dispensed is sufficient. The reference value can take into account viscosity changes of the die attach adhesive, so that the volume of die attach adhesive dispensed during production can be determined. The volume dispensed can be automatically adjusted in situ during production using a computer system.

Abstract: Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.

Abstract: A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion.

Abstract: By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

Abstract: There is provided a high-performance compound semiconductor epitaxial wafer that has an improved linearity of the voltage-current characteristic, a producing method thereof, and a judging method thereof. Provided is a semiconductor wafer including a compound semiconductor that produces a two-dimensional carrier gas, a carrier supply semiconductor that supplies a carrier to the compound semiconductor, and a mobility lowering semiconductor that is disposed between the compound semiconductor and the carrier supply semiconductor and that has a mobility lowering factor that makes the mobility of the carrier in the mobility lowering semiconductor lower than the mobility of the carrier in the compound semiconductor.

Abstract: Manufacturing semiconductor heterostructures by way of molecular beam epitaxy, including placing a substrate into a first vacuum chamber, heating the substrate to a first temperature, depositing from at least one molecular beam a first epitaxial layer of a first material containing a binary, ternary or quaternary compound of elements of main group III and V, cooling the substrate to a second temperature, interrupting the molecular beam by elements of main group III and V, heating the substrate to a third temperature and depositing from at least one molecular beam a second epitaxial layer of a second material containing a binary, ternary, or quaternary compound of elements of main group III and V and that is deposited from at least one molecular beam; and semiconductor components produced thereby.

Abstract: A metrology system for gauging and spatially mapping a semiconductor material on a substrate can be used in controlling deposition and thermal activation processes.

Abstract: This method of manufacturing a silicon wafer has a step of preparing a wafer, in which a surface of the silicon wafer is surface-treated, a step of setting stress, in which the stress S (MPa) subjected on the wafer is set, a step of inspecting, in which a defect on a surface of the wafer is inspected, and a step of determining, in which the wafer is evaluated if the wafer satisfies a criterion. In this method, it is possible to manufacture a wafer with cracking resistance even if it is subjected to a millisecond annealing by the FLA annealing treatment.

Abstract: Projection systems and methods with mechanically decoupled metrology plates according to embodiments of the present invention can be used to characterize and compensate for misalignment and aberration in production images due to thermal and mechanical effects. Sensors on the metrology plate measure the position of the metrology plate relative to the image and to the substrate during exposure of the substrate to the production image. Data from the sensors are used to adjust the projection optics and/or substrate dynamically to correct or compensate for alignment errors and aberration-induced errors. Compared to prior art systems and methods, the projection systems and methods described herein offer greater design flexibility and relaxed constraints on mechanical stability and thermally induced expansion. In addition, decoupled metrology plates can be used to align two or more objectives simultaneously and independently.

Abstract: A method of forming an epitaxial layer to increase flatness of an epitaxial silicon wafer is provided. In particular, a method of controlling the epitaxial layer thickness in a peripheral part of the wafer is provided. An apparatus for manufacturing an epitaxial wafer by growing an epitaxial layer with reaction of a semiconductor wafer and a source gas in a reaction furnace comprising: a pocket in which the semiconductor wafer is placed; a susceptor fixing the semiconductor; orientation-dependent control means dependent on a crystal orientation of the semiconductor wafer and/or orientation-independent control means independent from the crystal orientation of the semiconductor wafer, wherein the apparatus may improve flatness in a peripheral part of the epitaxial layer.

Abstract: A semiconductor device and a method of manufacturing are provided. In some embodiments, a backside annealing process such that a first heat source is placed along a backside of the substrate. In other embodiments, the first heat source is used in combination with an anti-reflection dielectric (ARD) layer is deposited over the substrate. In yet other embodiments, a second heat source is placed along a front side of the substrate in addition to the first heat source placed on the backside of the substrate. In yet other embodiments, a heat shield may be placed between the substrate and the second heat source on the front side of the substrate. In yet further embodiments, a single heat source may be used on the front side of the substrate in combination with the ARD layer. A reflectivity scan may be performed to determine which anneal stage (RTA or MSA or both) to place thermal leveling solution.

Abstract: A flexible, high density decal and the use thereof methods of forming detachable electrical interconnections between a flexible chip carrier and a printed wiring board. The flexible decal has fine-pitch pads on a first surface and pads of a pitch wider than the fine pitch on a second surface, the fine-pitch pads on the first surface designed to electrically connect to a semiconductor device, and the wider-pitch pads on the second surface designed to electrically connect to a printed wiring board or the like. The pads on the first surface are conductively wired to the pads on the second surface through one or more insulating levels in the flexible decal.

Abstract: Projection systems and methods with mechanically decoupled metrology plates according to embodiments of the present invention can be used to characterize and compensate for misalignment and aberration in production images due to thermal and mechanical effects. Sensors on the metrology plate measure the position of the metrology plate relative to the image and to the substrate during exposure of the substrate to the production image. Data from the sensors are used to adjust the projection optics and/or substrate dynamically to correct or compensate for alignment errors and aberration-induced errors. Compared to prior art systems and methods, the projection systems and methods described herein offer greater design flexibility and relaxed constraints on mechanical stability and thermally induced expansion. In addition, decoupled metrology plates can be used to align two or more objectives simultaneously and independently.

Abstract: A method and apparatus (20) for testing the mounting of an integrated circuit (16) on a printed circuit board (12) using a ball grid array comprises measuring the change in height, or drop, of the integrated circuit (16) relative to the printed circuit board (12) following soldering of the ball grid array and comparing the measured drop with a predetermined range. The integrated circuit is deemed to have been successfully mounted to the printed circuit board if the change in height falls within the predetermined range.

Abstract: A structure and methods for using an integrated circuit structure comprise a substrate and circuitry connected to the substrate. The substrate includes a heat sensitive material that changes color when heated. The heat sensitive material has one of a plurality of colors depending upon a temperature to which the substrate was exposed.

Abstract: A method to determine the cleanness of a semiconductor substrate and the quantity/density of pin holes that may exist within a patterned antireflective coating (ARC) is provided. Electroplating is employed to monitor the changes in the porosity of the ARC caused by the pin holes during solar cell manufacturing. In particular, electroplating a metal or metal alloy to form a metallic grid on an exposed front side surface of a substrate also fills the pin holes. The quantity/density of metallic filled pin holes (and hence the number of pin holes) in the patterned ARC can then be determined.

Abstract: Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.