Abstract: A process for manufacturing a silicon-on-insulator substrate comprising a single-crystal silicon substrate in which an oxide layer has been locally buried includes forming a step on the silicon substrate so that a region corresponding to the oxide layer has a greater surface height than other regions; then implanting oxygen ions in the silicon substrate so as to form the oxide layer.

Abstract: A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel region of the access device of one vertical memory cell and a semiconductor substrate of the SOI wafer. The body contact provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by an ion implantation process that modifies the stoichiometry of a region of the buried dielectric layer so that the modified region becomes electrically conductive with a relatively high resistance.

Abstract: In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.

Abstract: A semiconductor substrate is manufactured in which a plurality of single crystal semiconductor layers is fixed to a base substrate having low heat resistance such as a glass substrate with a buffer layer interposed therebetween. A plurality of single crystal semiconductor substrates is prepared, each of which includes a buffer layer and a damaged region which is formed by adding hydrogen ions to each semiconductor substrate and contains a large amount of hydrogen. One or more of these single crystal semiconductor substrates is fixed to a base substrate and irradiated with an electromagnetic wave having a frequency of 300 MHz to 300 GHz, thereby being divided along the damaged region. Fixture of single crystal semiconductor substrates and electromagnetic wave irradiation are repeated to manufacture a semiconductor substrate where a required number of single crystal semiconductor substrates are fixed onto the base substrate.

Abstract: A SIMOX wafer is produced by implanting an oxygen ions into a surface of a Si substrate and then conducting a high-temperature annealing, in which an atmosphere in at least an end stage of the high-temperature annealing treatment is an Ar or N2 atmosphere containing an oxygen of more than 3 volume % but not more than 10 volume %.

Abstract: To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form a buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.

Abstract: This method for manufacturing a SIMOX wafer, includes: implanting oxygen ions in a silicon wafer; cleaning said silicon wafer into which said oxygen ions are implanted; and forming a buried oxide film within an interior of said silicon wafer by subjecting said cleaned silicon wafer to a heat treatment, wherein said method further includes immersing said silicon wafer in an aqueous solution of hydrofluoric acid and etching a SiO2 film formed on a surface of said silicon wafer, which is conducted after said implanting of oxygen ions in said silicon wafer, but prior to said cleaning of said silicon wafer, and an etching rate for said SiO2 film by said aqueous solution of hydrofluoric acid during said etching treatment is within a range from 150 to 3,000 (?/minute).

Abstract: An apparatus and a method for forming the apparatus include a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a coefficient of thermal expansion substantially equal to that of the semiconductor layer. The semiconductor layer can also be formed having a thickness such that it does not yield due to temperature-induced strain at device processing temperatures. A silicon layer bonded to a silicon oxycarbide glass substrate provides a silicon on insulator wafer in which circuitry for electronic devices is fabricated.

Abstract: The present invention provides a method of producing an SOI wafer, comprising at least steps of forming an oxygen ion-implanted layer by implanting oxygen ions into a silicon wafer from one main surface thereof, subjecting the silicon wafer to oxide film-forming heat treatment to convert the oxygen ion-implanted layer into a buried oxide film, and thereby producing an SOI wafer having an SOI layer on the buried oxide film, wherein when the buried oxide film is formed in the silicon wafer, the buried oxide film is formed so that a thickness thereof is thicker than a thickness of the buried oxide film which the SOI wafer to be produced has, and thereafter the silicon wafer in which the thicker buried oxide film is formed is subjected to a heat treatment to reduce the thickness of the buried oxide film.

Abstract: This method for manufacturing a SIMOX wafer includes: heating a silicon wafer to 300° C. or more and implanting oxygen ions so as to form a high oxygen concentration layer within the silicon wafer; subjecting the silicon wafer to a cooling to less than 300° C. and an implanting of oxygen ions so as to form an amorphous layer; and subjecting the silicon wafer to a heat-treating in a mixed gas atmosphere containing oxygen so as to form a buried oxide layer. In the forming of the buried oxide layer, a starting temperature is less than 1350° C. and a maximum temperature is 1350° C. or more. This SIMOX wafer is manufactured by the above method and includes a BOX layer and a SOI layer on the BOX layer. The BOX layer has a thickness of 1300 ? or more and a breakdown voltage of 7 MV/cm or more, and the surface of the SOI layer and the interface between the SOI layer and the BOX layer have a roughness over a 10-?m square area of 4 ? rms or less.

Abstract: The invention encompasses a method of forming a semiconductor-on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is formed within the insulative mass. The material comprises one or more of nitrogen argon, fluorine, bromine, chlorine, iodine and germanium.

Abstract: A process for treating a structure to prepare it for electronics or optoelectronics applications. The structure includes a bulk substrate, an oxide layer, and a semiconductor layer, and the process includes providing a masking to define on the semiconductor layer a desired pattern, and applying a thermal treatment for removing a controlled thickness of oxide in the regions of the oxide layer corresponding to the desired pattern to assist in preparing the structure.

Abstract: A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.

Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.

Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.

Abstract: Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.

Abstract: A method for manufacturing a SIMOX wafer includes: heating a silicon wafer, implanting oxygen ions so as to form a high oxygen concentration layer; implanting oxygen ions into the silicon wafer obtained by the forming of the high oxygen concentration layer to form an amorphous layer; and heat-treating the silicon wafer to form a buried oxide layer, wherein in the forming of the amorphous layer, the implantation of oxygen ions is carried out after preheating the silicon wafer to a temperature lower than the heating temperature of the forming of the high oxygen concentration layer. Alternatively, the method for manufacturing a SIMOX wafer includes: in the formation of the high oxygen concentration layer, implanting oxygen ions while heating a silicon wafer at a temperature of 300° C. or more; and in the formation of the amorphous layer, implanting oxygen ions after preheating the silicon wafer to a temperature of less than 300° C.

Abstract: The invention encompasses a method of forming a semiconductor on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is formed within the insulative mass. The material comprises one or more of nitrogen argon, fluorine, bromine, chlorine, iodine and germanium.

Abstract: Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

Abstract: A method (100) of forming a silicon-on-insulator (SOI) wafer includes forming one or more channels in a top surface of a first wafer (104), and forming an insulator layer on a second wafer (106). The second wafer is treated (108) to generate a structural weakness therein, and the first and second wafers together (110) are then bonded together so that the channels face the insulator layer. A portion of the second wafer is then removed (112) from the bonded first and second wafers at a location corresponding to the structure weakness.

Abstract: A method for manufacturing a SOI wafer includes a step of forming a SOI wafer including a silicon support, an insulating layer containing oxide, and a superficial silicon layer arranged in that order and also includes a step of introducing hydrogen into the interface between the insulating layer and the superficial silicon layer. The SOI wafer is heat-treated in an atmosphere containing hydrogen or water in the hydrogen-introducing step. A method for manufacturing a SOI wafer includes a step of forming a SOI wafer including a silicon support, an insulating layer containing oxide, and a superficial silicon layer arranged in that order; a step of introducing hydrogen into the interface between the insulating layer and the superficial silicon layer by forming a film on an oxide layer present on the SOI wafer using a reaction to generate hydrogen; and a step of removing the film.

Abstract: A method for forming a high density dielectric film by chemical vapor deposition. The method comprises: (a) a substrate is provided in a processing chamber; (b) a first gas is introduced into the processing chamber with a first pressure and adsorbed on the substrate, wherein the first gas comprises silicon-containing or carbon-containing gas; (c) the first gas is stopped, and the first pressure is lowered to a second pressure; (d) a second gas is introduced into the processing chamber with a third pressure, and forced to react with the first gas absorbed on the substrate and remained in the processing chamber, wherein the second gas comprises oxidizer or reduction agent; (e) the steps (b)˜(d) are repeated until a high density dielectric film is formed on the substrate.

Abstract: A method is provided for fabricating thin membrane structures in localized surface regions of a single crystal substrate. In the method, ion implantation masks are patterned on the surface of the single crystal substrate with openings that define the localized surface regions. Foreign ions are implanted through the openings into the single crystal substrate to modify the chemical and/or structural properties of subsurface layers at predetermined depths underneath super layers of material. These subsurface layers are removed by selective etching. The removal of the subsurface layers leaves the super layers of material intact as membrane structures on top of openings or channels corresponding to the space of the removed subsurface layers. At least one portion or end of a membrane structure remains attached to the single crystal substrate.

Abstract: An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

Abstract: It is an object of the present invention to provide a semiconductor laser device with high-yielding in which a clack generated in an epitaxial growth layer is restrained and to the manufacturing method thereof, the semiconductor laser device includes a GaN substrate 1, an n-type GaN layer 2, an n-type AlGaN cladding layer 3, a n-type GaN guide layer 4, an InGaN multiple quantum well active layer 5, an undoped-GaN guide layer 6, a p-type AlGaN electron overflow suppression layer 7, a p-type GaN guide layer 8, a SiO2 blocking layer 9, an Ni/ITO cladding layer electrode 10 as a transparent electrode, a Ti/Au pad electrode 11, and a Ti/Al/Ni/Au electrode 12. The SiO2 blocking layer 9 is formed above the InGaN multiple quantum well active layer 5 so as to have an opening. The Ni/ITO cladding layer electrode 10 is formed inside the opening, and which is transparent for the light from the InGaN multiple quantum well active layer, and serves as a cladding layer.

Abstract: A system and method for inhibiting radiation hardness of Silicon on Insulator (SOI) integrated circuits is described. An electrical connection is used to connect a substrate below a buried oxide layer to the topside above the buried oxide layer. A bias is then applied to the substrate. The bias may turn on a parasitic backgate in the buried oxide layer. As a result, the integrated circuit may not meet certain hardness criteria and, thus, not be subject to certain export restrictions imposed by the International Traffic in Arms Regulations.

Abstract: A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

Abstract: A SOI (silicon on insulator) single crystalline chip structure is provided. The SOI chip structure has a first silicon layer for at least one SOI device to be placed thereon, at least one buried oxide area with a predetermined depth placed at a predetermined position of the first silicon layer in order to enable the first silicon layer to have at least two different silicon layer thicknesses. The buried oxide area is filled with a silicon oxide material serving as an insulating area, and a second silicon layer is located below the first silicon layer and the buried oxide area.

Abstract: Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer. The oxygen implant step forms an isolated region near the oxygen implants. A backside implant step selectively dopes the isolated region for forming a backgate for an SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices.

Abstract: According to one embodiment, a semiconductor device is provided. The semiconductor device includes an oxide layer. The semiconductor device also includes a silicon layer disposed outwardly from the oxide layer and having at least one region comprising a dopant. The semiconductor device also includes a dielectric layer disposed outwardly from the silicon layer. The semiconductor device also includes a gate disposed outwardly from the dielectric layer. The semiconductor device also includes a blocking layer disposed between the oxide layer and the silicon layer. The blocking layer is operable to at least partially block a transfer of the dopant from the at least one region of the silicon layer to the oxide layer.

Abstract: The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask having at least one opening on a surface of Si-containing material, recessing the Si-containing material through the at least one opening using an etching process to provide a structure having at least one recess region and a non-recessed region, and forming a first buried insulating region in the non-recessed region and a second buried insulating region in the recessed region. In accordance with the present invention, the first buried insulating region in the non-recessed region is located above the second buried isolation region in the recessed region. A lift-off step can be employed to remove the first buried insulating region and the material that lies above to provide a substrate containing both SOI and non-SOI regions.

Abstract: In one illustrative example, a three terminal magnetic sensor includes a collector region made of a semiconductor material, a base region, and an emitter region. An insulator layer is formed between the collector region and a carrier substrate body which carries the three terminal magnetic sensor. The insulator layer serves to reduce a capacitance otherwise present between the collector region and magnetic media at a magnetic field sensing plane of the three terminal magnetic sensor. Thus, the insulator layer electrically isolates the collector region from the carrier substrate body. The structure may be formed through use of a separation by implanting oxygen (SIMOX) technique or a wafer-bonding technique, as examples.

Abstract: A method of fabricating a silicon-on-insulator (SOI) having a superficial Si-containing layer that has a reduced number of tile and divot defects is provided. The method includes the steps of: implanting oxygen ions into a surface of a Si-containing substrate, the implanted oxygen ions having a concentration sufficient to form a buried oxide region during a subsequent annealing step; and annealing the substrate containing implanted oxygen ions under conditions wherein the implanted oxygen ions form a buried oxide region which electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. Moreover, the annealing conditions employed are capable of reducing the number of tile or divot defects present in the superficial Si-containing layer so as to allow optical detection of any other defect that has a lower density than the tile or divot defect. The present invention also relates to the SOI substrate that is produced using the inventive method.