Using Silicon Implanted Buried Insulating Layers, E.g., Oxide Layers, I.e., Simox Technique (epo) Patents (Class 257/E21.563)
  • Patent number: 10475696
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: November 12, 2019
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Henry Frank Erk, Sasha Kweskin, Jeffrey L. Libbert, Mayank Bulsara
  • Patent number: 10347538
    Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: July 9, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Che-Wei Yang, Hao-Hsiung Lin, Samuel C. Pan
  • Patent number: 10170315
    Abstract: There is set forth herein a semiconductor device fabricated on a bulk wafer having a local buried oxide region underneath a channel region of a MOSFET. In one embodiment the local buried oxide region can be self-aligned to a gate, and a source/drain region can be formed in a bulk substrate. A local buried oxide region can be formed in a semiconductor device by implantation of oxygen into a bulk region of the semiconductor device followed by annealing.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yanxiang Liu, Min-hwa Chi
  • Patent number: 8895407
    Abstract: A manufacturing method of an SOI substrate which possesses a base substrate having low heat resistance and a very thin semiconductor layer having high planarity is demonstrated. The method includes: implanting hydrogen ions into a semiconductor substrate to form an ion implantation layer; bonding the semiconductor substrate and a base substrate such as a glass substrate, placing a bonding layer therebetween; heating the substrates bonded to each other to separate the semiconductor substrate from the base substrate, leaving a thin semiconductor layer over the base substrate; irradiating the surface of the thin semiconductor layer with laser light to improve the planarity and recover the crystallinity of the thin semiconductor layer; and thinning the thin semiconductor layer. This method allows the formation of an SOI substrate which has a single-crystalline semiconductor layer with a thickness of 100 nm or less over a base substrate.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Akihisa Shimomura, Tatsuya Mizoi, Eiji Higa, Yoji Nagano
  • Patent number: 8815700
    Abstract: In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: August 26, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Peter J. Hopper, William French, Kyuwoon Hwang
  • Patent number: 8772129
    Abstract: A manufacturing method of an SOI substrate which possesses a base substrate having low heat resistance and a very thin semiconductor layer having high planarity is demonstrated. The method includes: implanting hydrogen ions into a semiconductor substrate to form an ion implantation layer; bonding the semiconductor substrate and a base substrate such as a glass substrate, placing a bonding layer therebetween; heating the substrates bonded to each other to separate the semiconductor substrate from the base substrate, leaving a thin semiconductor layer over the base substrate; irradiating the surface of the thin semiconductor layer with laser light to improve the planarity and recover the crystallinity of the thin semiconductor layer; and thinning the thin semiconductor layer. This method allows the formation of an SOI substrate which has a single-crystalline semiconductor layer with a thickness of 100 nm or less over a base substrate.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Akihisa Shimomura, Tatsuya Mizoi, Eiji Higa, Yoji Nagano
  • Patent number: 8772126
    Abstract: A cavity is etched from a front surface into a semiconductor substrate. After providing an etch stop structure at the bottom of the cavity, the cavity is closed. From a back surface opposite to the front surface the semiconductor substrate is grinded at least up to an edge of the etch stop structure oriented to the back surface. Providing the etch stop structure at the bottom of an etched cavity allows for precisely adjusting a thickness of a semiconductor body of a semiconductor device.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: July 8, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Anton Mauder
  • Patent number: 8735263
    Abstract: An SOI substrate is manufactured by the following steps: a semiconductor substrate is irradiated with an ion beam in which the proportion of H2O+ to hydrogen ions (H3+) is lower than or equal to 3%, preferably lower than or equal to 0.3%, whereby an embrittled region is formed in the semiconductor substrate; a surface of the semiconductor substrate and a surface of a base substrate are disposed so as to be in contact with each other, whereby the semiconductor substrate and the base substrate are bonded; and a semiconductor layer is separated along the embrittled region from the semiconductor substrate which is bonded to the base substrate by heating the semiconductor substrate and the base substrate, so that the semiconductor layer is formed over the base substrate.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kazuya Hanaoka
  • Publication number: 20130320483
    Abstract: Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 ? are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 ?. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 ?.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 5, 2013
    Applicant: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Joel P. de Souza, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 8563396
    Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.
    Type: Grant
    Filed: January 29, 2011
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sampath Purushothaman, Roy R. Yu
  • Patent number: 8486776
    Abstract: Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Katherine L. Saenger
  • Patent number: 8330222
    Abstract: A small amount of oxygen is ion-implanted in a wafer surface layer, and then heat treatment is performed so as to form an incomplete implanted oxide film in the surface layer. Thereby, wafer cost is reduced; a pit is prevented from forming in a surface of an epitaxial film; and a slip is prevented from forming in an external peripheral portion of a wafer.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: December 11, 2012
    Assignee: Sumco Corporation
    Inventors: Yoshiro Aoki, Noashi Adachi, Akihiko Endo, Yoshihisa Nonogaki
  • Patent number: 8222124
    Abstract: This method for manufacturing a SIMOX wafer includes: forming a mask layer on one surface side of a silicon single crystal wafer, which has an opening on a region where a BOX layer is to be formed; implanting oxygen ions through the opening of the mask layer into the silicon single crystal wafer to a predetermined depth, and locally forming an oxygen implantation region; annealing the silicon single crystal wafer with the mask layer, and oxidizing the oxygen implantation region so as to form the BOX layer; and removing a coated oxide film that covers the whole silicon single crystal wafer which is formed in the annealing of the silicon single crystal wafer, wherein the mask layer has a lamination comprising an oxide film and either one or both of a polysilicon film and an amorphous silicon film.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: July 17, 2012
    Assignee: Sumco Corporation
    Inventor: Tetsuya Nakai
  • Patent number: 8193068
    Abstract: To provide an SOI substrate with an SOI layer that can be put into practical use, even when a substrate with a low allowable temperature limit such as a glass substrate is used, and to provide a semiconductor substrate formed using such an SOI substrate. In order to bond a single-crystalline semiconductor substrate to a base substrate such as a glass substrate, a silicon oxide film formed by CVD with organic silane as a source material is used as a bonding layer, for example. Accordingly, an SOL substrate with a strong bond portion can be formed even when a substrate with an allowable temperature limit of less than or equal to 700° C. such as a glass substrate is used. A semiconductor layer separated from the single-crystalline semiconductor substrate is irradiated with a laser beam so that the surface of the semiconductor layer is planarized and the crystallinity thereof is recovered.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: June 5, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Eiji Higa, Yoji Nagano, Tatsuya Mizoi, Akihisa Shimomura
  • Patent number: 8183635
    Abstract: A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: May 22, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyuki Sugii, Ryuta Tsuchiya, Shinichiro Kimura, Takashi Ishigaki, Yusuke Morita, Hiroyuki Yoshimoto
  • Patent number: 8173553
    Abstract: A small amount of oxygen is ion-implanted in a wafer surface layer, and then heat treatment is performed so as to form an incomplete implanted oxide film in the surface layer. Thereby, wafer cost is reduced; a pit is prevented from forming in a surface of an epitaxial film; and a slip is prevented from forming in an external peripheral portion of a wafer.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: May 8, 2012
    Assignee: Sumco Corporation
    Inventors: Yoshiro Aoki, Noashi Adachi, Akihiko Endo, Yoshihisa Nonogaki
  • Publication number: 20120068267
    Abstract: Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.
    Type: Application
    Filed: September 21, 2010
    Publication date: March 22, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Katherine L. Saenger
  • Patent number: 8138063
    Abstract: An object of the present invention is to provide a semiconductor device having a structure which can realize not only suppressing a punch-through current but also reusing a silicon wafer which is used for bonding, in manufacturing a semiconductor device using an SOI technique, and a manufacturing method thereof. The semiconductor device can suppress the punch-through current by forming a semiconductor film in which an impurity imparting a conductivity type opposite to that of a source region and a drain region is implanted over a substrate having an insulating surface, and forming a channel formation region using a semiconductor film of stacked layers obtained by bonding a single crystal semiconductor film to the semiconductor film by an SOI technique.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: March 20, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiromichi Godo
  • Patent number: 8043929
    Abstract: Hetero-semiconductor structures possessing an SOI structure containing a silicon-germanium mixed crystal are produced at a low cost and high productivity. The semiconductor substrates comprise a first layer formed of silicon having germanium added thereto, a second layer formed of an oxide and adjoined to the first layer, and a third layer derived from the same source as the first layer, but having an enriched content of germanium as a result of thermal oxidation and thinning of the third layer.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: October 25, 2011
    Assignee: Siltronic AG
    Inventors: Josef Brunner, Hiroyuki Deai, Atsushi Ikari, Martin Grassl, Atsuki Matsumura, Wilfried von Ammon
  • Patent number: 8034694
    Abstract: An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: October 11, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Tetsuya Kakehata, Yoichi Iikubo
  • Patent number: 8021991
    Abstract: Oxide films are deposited under conditions generating a silicon-rich oxide in which silicon nanoclusters form either during deposition or during subsequent annealing. Such deposition conditions include those producing films with optical indices (n) greater than 1.46. The method of the present invention reduces the TID radiation-induced shifts for the oxides.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: September 20, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Harold L Hughes, Bernard J Mrstik, Reed K Lawrence, Patrick J McMarr
  • Patent number: 7977167
    Abstract: A method of producing a field effect transistor arrangement. A substrate having a first crystal surface orientation is provided. A first layer is formed above a first portion of the substrate, the first layer having a second crystal surface orientation different from the first crystal surface orientation. A second layer is formed on at least a second portion of the substrate and adjacent to the first layer, the second layer having the first crystal surface orientation. A first buried oxide layer is formed between the substrate and the first layer. Micro-cavities are formed in the second layer and oxidizing the micro-cavities, thereby forming a second buried oxide layer between the substrate and the second layer. A first field effect transistor of a first conductivity type is formed in or on the first layer. A second field effect transistor of a second conductivity type is formed in or on the second layer.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: July 12, 2011
    Assignee: Infineon Technologies AG
    Inventors: Karl Hofmann, Luis-Felipe Giles
  • Patent number: 7943482
    Abstract: A design structure is provided for a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The device includes a first structure and a second structure. The first structure includes: a radiation hardened BOX layer under an active device layer; radiation hardened shallow trench isolation (STI) structures between active regions of the active device layer and above the radiation hardened BOX layer; metal interconnects in one or more interlevel dielectric layers above gates structures of the active regions. The second structure is bonded to the first structure. The second structure includes: a Si based substrate; a BOX layer on the substrate; a Si layer with active regions on the BOX; oxide filled STI structures between the active regions of the Si layer; and metal interconnects in one or more interlevel dielectric layers above gates structures. At least one metal interconnect is electrically connecting the first structure to the second structure.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: May 17, 2011
    Assignee: International Business Machines Corporation
    Inventors: John M. Aitken, Ethan H. Cannon
  • Patent number: 7943414
    Abstract: An object of an embodiment of the present invention to be disclosed is to prevent oxygen from being taken in a single crystal semiconductor layer in laser irradiation even when crystallinity of the single crystal semiconductor layer is repaired by irradiation with a laser beam; and to make substantially equal or reduce an oxygen concentration in the semiconductor layer after the laser irradiation comparing before the laser irradiation. A single crystal semiconductor layer which is provided over a base substrate by bonding is irradiated with a laser beam, whereby the crystallinity of the single crystal semiconductor layer is repaired. The laser irradiation is performed under a reducing atmosphere or an inert atmosphere.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: May 17, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Hideto Ohnuma, Junpei Momo, Shunpei Yamazaki
  • Patent number: 7935609
    Abstract: A method is provided for fabricating a semiconductor device and more particularly to a method of manufacturing a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The method includes removing a substrate from an SOI wafer and selectively removing a buried oxide layer formed as a layer between the SOI wafer and active regions of a device. The method further comprises selectively removing isolation oxide formed between the active regions, and replacing the removed buried oxide layer and the isolation oxide with radiation hardened insulators.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: May 3, 2011
    Assignee: International Business Machines Corporation
    Inventors: John M. Aitken, Ethan H. Cannon
  • Patent number: 7897444
    Abstract: A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: March 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Stephen W. Bedell, Joel P. de Souza, Keith E. Fogel, Alexander Reznicek, Devendra K. Sadana, Ghavam Shahidi
  • Patent number: 7897476
    Abstract: To provide an SOI substrate with an SOI layer that can be put into practical use, even when a substrate with a low allowable temperature limit such as a glass substrate is used, and to provide a semiconductor substrate formed using such an SOI substrate. In order to bond a single-crystalline semiconductor substrate to a base substrate such as a glass substrate, a silicon oxide film formed by CVD with organic silane as a source material is used as a bonding layer, for example. Accordingly, an SOI substrate with a strong bond portion can be formed even when a substrate with an allowable temperature limit of less than or equal to 700° C. such as a glass substrate is used. A semiconductor layer separated from the single-crystalline semiconductor substrate is irradiated with a laser beam so that the surface of the semiconductor layer is planarized and the crystallinity thereof is recovered.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: March 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Eiji Higa, Yoji Nagano, Tatsuya Mizoi, Akihisa Shimomura
  • Patent number: 7884000
    Abstract: A method for manufacturing SIMOX wafer, wherein roughness (Rms) of an SOI layer and roughness (Rms) of an interface between the SOI layer and a BOX layer can be reduced. The method includes forming a first ion-implanted layer containing highly concentrated oxygen within a wafer; forming a second ion-implanted amorphous layer; and a high temperature heat treatment, transforming the first and second ion-implanted layers into a BOX layer by holding the wafer at a temperature between 1300° C. or more and a temperature less than a silicon melting point in an atmosphere containing oxygen, wherein when a first dose amount in forming the first ion-implanted layer is set to 2×1017 to 3×1017 atoms/cm2, the first implantation energy set to 165 to 240 keV and a second dose amount in forming the second ion-implanted layer is set to 1x1014 to 1x1016 atoms/cm2.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: February 8, 2011
    Assignee: Sumco Corporation
    Inventors: Yoshiro Aoki, Riyuusuke Kasamatsu, Yukio Komatsu
  • Publication number: 20100327397
    Abstract: This method for manufacturing a SIMOX wafer includes: forming a mask layer on one surface side of a silicon single crystal wafer, which has an opening on a region where a BOX layer is to be formed; implanting oxygen ions through the opening of the mask layer into the silicon single crystal wafer to a predetermined depth, and locally forming an oxygen implantation region; annealing the silicon single crystal wafer with the mask layer, and oxidizing the oxygen implantation region so as to form the BOX layer; and removing a coated oxide film that covers the whole silicon single crystal wafer which is formed in the annealing of the silicon single crystal wafer, wherein the mask layer has a lamination comprising an oxide film and either one or both of a polysilicon film and an amorphous silicon film.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 30, 2010
    Applicant: SUMCO CORPORATION
    Inventor: Tetsuya NAKAI
  • Publication number: 20100323502
    Abstract: The present invention provides a method for manufacturing an SOI substrate including at least: an oxygen ion implantation step of ion-implanting oxygen ions from one main surface of a single-crystal silicon substrate to form an oxygen ion implanted layer; and a heat treatment step of performing a heat treatment with respect to the single-crystal silicon substrate having the oxygen ion implanted layer formed therein to change the oxygen ion implanted layer into a buried oxide film layer, wherein acceleration energy for the oxygen ion implantation is previously determined from a thickness of the buried oxide film layer to be obtained, and the oxygen ion implantation step is carried out with the determined acceleration energy to manufacture the SOI substrate. Thereby, it is possible to provide an SOI substrate manufacturing method that enables efficiently manufacturing an SOI substrate having a continuous and uniform thin buried oxide film layer.
    Type: Application
    Filed: February 19, 2008
    Publication date: December 23, 2010
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi Takeno, Tohru Ishizuka, Nobuhiko Noto
  • Publication number: 20100283118
    Abstract: A method for manufacturing a SeOI substrate that includes a thin working layer made from one or more semiconductor material(s); a support layer; and a thin buried oxide layer between the working layer and the support layer. The method includes a manufacturing step of an intermediate SeOI substrate having a buried oxide layer with a thickness greater than a thickness desired for the thin buried oxide layer; and a dissolution step of the buried oxide layer in order to form therewith the thin buried oxide layer. After the dissolution step, an oxidation step of the substrate is conducted for creating an oxidized layer on the substrate, and an oxide migration step for diffusing at least a part of the oxide layer through the working layer in order to increase the electrical interface quality of the substrate and decrease its Dit value.
    Type: Application
    Filed: February 20, 2008
    Publication date: November 11, 2010
    Applicant: S.O.I.TEC SILICON ON INSULATION TECHNOLOGIES
    Inventors: Oleg Kononchuk, George K. Celler
  • Patent number: 7820524
    Abstract: A manufacturing method of an SOI substrate which possesses a base substrate having low heat resistance and a very thin semiconductor layer having high planarity is demonstrated. The method includes: implanting hydrogen ions into a semiconductor substrate to form an ion implantation layer; bonding the semiconductor substrate and a base substrate such as a glass substrate, placing a bonding layer therebetween; heating the substrates bonded to each other to separate the semiconductor substrate from the base substrate, leaving a thin semiconductor layer over the base substrate; irradiating the surface of the thin semiconductor layer with laser light to improve the planarity and recover the crystallinity of the thin semiconductor layer; and thinning the thin semiconductor layer. This method allows the formation of an SOI substrate which has a single-crystalline semiconductor layer with a thickness of 100 nm or less over a base substrate.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: October 26, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Akihisa Shimomura, Tatsuya Mizoi, Eiji Higa, Yoji Nagano
  • Patent number: 7811878
    Abstract: To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form an buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: October 12, 2010
    Assignees: Sumco Corporation, Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Nakai, Bong-Gyun Ko, Takeshi Hamamoto, Takashi Yamada
  • Patent number: 7781302
    Abstract: Methods of fabricating a semiconductor device include forming a mask pattern on a semiconductor substrate and which exposes defined regions of the semiconductor substrate. Oxygen ions are implanted into the defined regions of the semiconductor substrate using the mask pattern as an ion implantation mask. The oxygen ion implanted regions of the semiconductor substrate are annealed at one or more temperatures in a range that is sufficiently high to form silicon oxide substantially throughout the oxygen ion implanted regions by reacting the implanted oxygen ions with silicon in the oxygen ion implanted regions, and that is sufficiently low to substantially prevent oxidation of the semiconductor substrate adjacent to the oxygen ion implanted regions.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Won Cha, Dae-Lok Bae
  • Patent number: 7745306
    Abstract: A bonded wafer is produced by a method comprising a step of implanting ions of a light element such as hydrogen, helium or the like into a wafer for active layer at a predetermined depth position to form an ion implanted layer, a step of bonding the wafer for active layer to a wafer for support substrate through an insulating film, a step of exfoliating the wafer at the ion implanted layer, a first heat treatment step of conducting a sacrificial oxidation for reducing damage on a surface of an active layer exposed through the exfoliation and a second heat treatment step of raising a bonding strength, in which the second heat treatment step is continuously conducted after the first heat treatment step without removing an oxide film formed on the surface of the active layer.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: June 29, 2010
    Assignee: Sumco Corporation
    Inventors: Hidehiko Okuda, Tatsumi Kusaba
  • Patent number: 7727867
    Abstract: A MLD-SIMOX wafer is obtained by forming a first ion-implanted layer in a silicon wafer; forming a second ion-implanted layer that is in an amorphous state; and subjecting the wafer to a high-temperature heat treatment to maintain the wafer in an atmosphere containing oxygen at a temperature that is not lower than 1300° C. but lower than a silicon melting point to change the first and the second ion-implanted layers into a BOX layer, wherein the dose amount for the first ion-implanted layer is 1.25 to 1.5×1017 atoms/cm2, the dose amount for the second ion-implanted layer is 1.0×1014 to 1×1016 atoms/cm2, the wafer is preheated to a temperature of 50° C. to 200° C. before forming the second ion-implanted layer, and the second ion-implanted layer is formed in a state where it is continuously heated to a preheating temperature.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: June 1, 2010
    Assignee: Sumco Corporation
    Inventors: Yoshiro Aoki, Bong-Gyun Ko
  • Patent number: 7727874
    Abstract: Non-polar or semi-polar (Al, Ga, In)N substrates are fabricated by re-growth of (Al, Ga, In)N crystal on (Al, Ga, In)N seed crystals, wherein the size of the seed crystal expands or is increased in the lateral and vertical directions, resulting in larger sizes of non-polar and semi-polar substrates useful for optoelectronic and microelectronic devices. One or more non-polar or semi-polar substrates may be sliced from the re-grown crystal. The lateral growth rate may be greater than the vertical growth rate. The seed crystal may be a non-polar seed crystal. The seed crystal may have crystalline edges of equivalent crystallographic orientation.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: June 1, 2010
    Assignee: Kyma Technologies, Inc.
    Inventors: Andrew David Hanser, Edward Alfred Preble, Lianghong Liu, Terry Lee Clites, Keith Richard Evans
  • Publication number: 20100120225
    Abstract: An object is to reduce occurrence of defective bonding between a base substrate and a semiconductor substrate even when a silicon nitride film or the like is used as a bonding layer. Another object is to provide a method for manufacturing an SOI substrate by which an increase in the number of steps can be suppressed.
    Type: Application
    Filed: January 25, 2010
    Publication date: May 13, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Tetsuya KAKEHATA, Kazutaka KURIKI
  • Patent number: 7691734
    Abstract: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: April 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Bradley A. Orner, Robert M. Rassel, David C. Sheridan, Steven H. Voldman
  • Patent number: 7666721
    Abstract: An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Zhijiong Luo, Haining S. Yang
  • Patent number: 7659599
    Abstract: In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: February 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Roger Allen Booth, Jr., Louis Lu-Chen Hsu, Jack A. Mandelman, William R. Tonti
  • Publication number: 20100022066
    Abstract: A method for producing a high-resistance SIMOX wafer wherein oxygen diffused inside of a wafer by the heat treatment at a high temperature in an oxidizing atmosphere can be reduced to suppress the occurrence of thermal donor. In one embodiment, a heating-rapid cooling treatment is conducted after the heat treatment at a high temperature in an oxidizing atmosphere to implant vacancies from a surface of a wafer into an interior thereof to thereby easily precipitate oxygen diffused inside the wafer during the heat treatment.
    Type: Application
    Filed: July 16, 2009
    Publication date: January 28, 2010
    Applicant: SUMCO CORPORATION
    Inventors: Yoshiro Aoki, Naoshi Adachi
  • Patent number: 7642112
    Abstract: A method of manufacturing a bonded substrate stack includes a bonding surface processing step of processing at least one of first and second substrates each containing silicon and having a bonding surface, and a bonding step of bonding the bonding surface of the first substrate and the bonding surface of the second substrate. The bonding surface processing step includes an OH group increasing step of increasing OH groups on the bonding surfaces, and a moisture content decreasing step of heating the bonding surfaces where the OH groups have been increased at a temperature falling within a range of 50° C. to 200° C. to decrease moisture contents of the bonding surfaces.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: January 5, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tadashi Atoji, Ryuji Moriwaki
  • Patent number: 7642598
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: January 5, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Publication number: 20090321874
    Abstract: A small amount of oxygen is ion-implanted in a wafer surface layer, and then heat treatment is performed so as to form an incomplete implanted oxide film in the surface layer. Thereby, wafer cost is reduced; a pit is prevented from forming in a surface of an epitaxial film; and a slip is prevented from forming in an external peripheral portion of a wafer.
    Type: Application
    Filed: June 12, 2009
    Publication date: December 31, 2009
    Applicant: SUMCO CORPORATION
    Inventors: Yoshiro AOKI, Naoshi ADACHI, Akihiko ENDO, Yoshihisa NONOGAKI
  • Publication number: 20090311834
    Abstract: Method for making a transistor with self-aligned gate and ground plane, comprising the steps of: a) forming a stack, on one face of a semi-conductor substrate, comprising an organometallic layer and a dielectric layer, b) exposing a part of the organometallic layer, a portion of the organometallic layer different to the exposed part being protected from the electron beams by a mask, the shape and the dimensions of a section, in a plane parallel to the face of the substrate, of the gate of the transistor being substantially equal to the shape and to the dimensions of a section of said organometallic portion in said plane, c) removing the exposed part, d) forming dielectric portions in empty spaces formed by the removal of said exposed part of the organometallic layer, around said organometallic portion.
    Type: Application
    Filed: June 11, 2009
    Publication date: December 17, 2009
    Applicant: COMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Claire FENOUILLET-BERANGER, Philippe CORONEL
  • Patent number: 7632735
    Abstract: A process for manufacturing a silicon-on-insulator substrate comprising a single-crystal silicon substrate in which an oxide layer has been locally buried includes forming a step on the silicon substrate so that a region corresponding to the oxide layer has a greater surface height than other regions; then implanting oxygen ions in the silicon substrate so as to form the oxide layer.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: December 15, 2009
    Assignee: Sumco Corporation
    Inventor: Tetsuya Nakai
  • Patent number: RE42097
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: February 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: RE42139
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: February 15, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: RE42241
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: March 22, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani