Using Semiconductor Or Insulator Technology, I.e., Soi Technology (epo) Patents (Class 257/E21.561)
  • Patent number: 10236659
    Abstract: A mode-locked laser on a silicon substrate and method for the production thereof by low temperature palladium bonding is disclosed.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: March 19, 2019
    Assignee: Rochester Institute of Technology
    Inventors: Stefan F. Preble, Zihao Wang, Michael L. Fanto
  • Patent number: 10049917
    Abstract: Methods of locally changing the BOX layer of a MOSFET device to a high-k layer to provide different Vts with one backside voltage and the resulting device are provided. Embodiments include providing a Si substrate having a BOX layer formed over the substrate and a SOI layer formed over the BOX layer; implanting a high current of dopants into at least one portion of the BOX layer; performing a high-temperature anneal of the BOX layer; forming first and second fully depleted silicon-on-insulator (FDSOI) transistors on the SOI layer, the first FDSOI transistors formed above either the BOX layer or the at least one portion of the BOX layer and the second FDSOI transistors formed above the at least one portion of the BOX layer; and applying a single voltage across a backside of the Si substrate.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Philipp Steinmann, Peter Javorka
  • Patent number: 10014356
    Abstract: An organic light-emitting diode display is disclosed. In one aspect, the display includes a substrate having a flexible portion configured to bend or fold, a semiconductor positioned over the substrate, and a gate insulating layer positioned over the semiconductor and having an opening. The display also includes an interlayer insulating layer positioned over the gate insulating layer, a portion of the interlayer insulating layer positioned within the opening. The display further includes a gate electrode positioned between the gate insulating layer and the interlayer insulating layer and overlapping the semiconductor in the depth dimension of the OLED display. A source electrode and a drain electrode are positioned over the interlayer insulating layer and connected to the semiconductor.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: July 3, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae An Seo, Ju Chan Park, Jin Hwan Choi, Tae Woong Kim, Bo Ik Park, Young Gug Seol
  • Patent number: 9899496
    Abstract: The present disclosure provides a device having a doped active region disposed in a substrate. The doped active region having an elongate shape and extends in a first direction. The device also includes a plurality of first metal gates disposed over the active region such that the first metal gates each extend in a second direction different from the first direction. The plurality of first metal gates includes an outer-most first metal gate having a greater dimension measured in the second direction than the rest of the first metal gates. The device further includes a plurality of second metal gates disposed over the substrate but not over the doped active region. The second metal gates contain different materials than the first metal gates. The second metal gates each extend in the second direction and form a plurality of respective N/P boundaries with the first metal gates.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: February 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sey-Ping Sun, Sung-Li Wang, Chin-Hsiang Lin, Neng-Kuo Chen, Clement Hsingjen Wann
  • Patent number: 9893200
    Abstract: It is an object to provide an oxide semiconductor which is suitable for use in a semiconductor device. Alternatively, it is another object to provide a semiconductor device using the oxide semiconductor. Provided is a semiconductor device including an In—Ga—Zn—O based oxide semiconductor layer in a channel formation region of a transistor. In the semiconductor device, the In—Ga—Zn—O based oxide semiconductor layer has a structure in which crystal grains represented by InGaO3(ZnO)m (m=1) are included in an amorphous structure represented by InGaO3(ZnO)m (m>0).
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: February 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Junichiro Sakata, Takuya Hirohashi, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga
  • Patent number: 9728441
    Abstract: A method for manufacturing a semiconductor device includes: bonding at least a part of the rear surface of a semiconductor wafer, and a supporting substrate in use of using a silane coupling agent; forming a functional structure on a front surface of the semiconductor wafer; placing a condensation point of laser light transmitted through the semiconductor wafer on a bonding interface between the semiconductor wafer and the supporting substrate, and irradiating the bonding interface with the laser light, thereby forming a fracture layer on at least a part of an outer circumferential section of the bonding interface; separating the bonding interface; and carrying out rear surface processing on the rear surface of the semiconductor wafer.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: August 8, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masaaki Tachioka, Tsunehiro Nakajima
  • Patent number: 9601513
    Abstract: Various embodiments include methods and integrated circuit structures. One method includes masking a structure with a mask to cover at least a portion of the structure under the mask, selectively implanting a material through a semiconductor layer and into a buried insulator layer forming an implant region. The implant region is substantially parallel to and below an upper surface of the structure. The method may also include masking an additional portion of the structure; etching a set of access ports though the semiconductor layer and partially through the insulator layer into the implant region; etching at least one tunnel below the upper surface of the structure in the implant region using the set of access; and depositing a conductor into the at least one tunnel and the set of access ports.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: March 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Terence B. Hook, Andreas Scholze, Lars W. Liebmann, Roger A. Quon, Andrew H. Simon
  • Patent number: 9431531
    Abstract: A semiconductor device configured to provide high heat dissipation and improve breakdown voltage comprises a substrate, a buried oxide layer over the substrate, a buried n+ region in the substrate below the buried oxide layer, and an epitaxial layer over the buried oxide layer. The epitaxial layer comprises a p-well, an n-well, and a drift region between the p-well and the n-well. The semiconductor device also comprises a source contact, a first electrode electrically connecting the source contact to the p-well, and a gate over a portion of the p-well and a portion of the drift region. The semiconductor device further comprises a drain contact, and a second electrode extending from the drain contact through the n-well and through the buried oxide layer to the buried n+ region. The second electrode electrically connects the drain contact to the n-well and to the buried n+ region.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung-Yang Lin, Hsin-Chih Chiang, Ruey-Hsin Liu, Ming-Ta Lei
  • Patent number: 9397120
    Abstract: An array substrate includes a substrate, a plurality of gate lines extending in a first direction on the substrate, a plurality of data lines including first and second data line pairs separated by cutting portions and a plurality of active patterns electrically connected to the first and second data line pairs. The data lines extend in a second direction crossing the first direction. The active patterns overlap the cutting portion and overlap a first gate line.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: July 19, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Min-Ha Hwang, Woong-Kwon Kim, In-Woo Kim, Seong-Young Lee, Kweon-Sam Hong, Dong-Hyun Yoo, Beom-Hee Han
  • Patent number: 9269571
    Abstract: It is an object to provide a highly reliable semiconductor device, a semiconductor device with low power consumption, a semiconductor device with high productivity, and a method for manufacturing such a semiconductor device. Impurities left remaining in an oxide semiconductor layer are removed without generating oxygen deficiency, and the oxide semiconductor layer is purified to have an extremely high purity. Specifically, after oxygen is added to the oxide semiconductor layer, heat treatment is performed on the oxide semiconductor layer to remove the impurities. In order to add oxygen, it is preferable to use a method in which oxygen having high energy is added by an ion implantation method, an ion doping method, or the like.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: February 23, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroki Ohara
  • Patent number: 9012994
    Abstract: A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: April 21, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Ho Jung, Young Joo Choi, Joon Geol Kim, Kang Moon Jo, Sho Yeon Kim, Byung Hwan Chu, Woo Geun Lee, Woo-Seok Jeon
  • Patent number: 8999774
    Abstract: A process fabricates a fin field-effect-transistor by implanting a dopant into an exposed portion of a semiconductor substrate within a cavity. The cavity is formed in a dielectric layer on the semiconductor substrate. The cavity exposes the portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate. A height of the cavity defines a height of the epitaxially grown semiconductor.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
  • Patent number: 8993382
    Abstract: A process fabricates a fin field-effect-transistor by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
  • Patent number: 8952454
    Abstract: An SOI wafer according to the present invention includes a support substrate and an insulating layer formed on the support substrate, a predetermined cavity pattern being formed on one of main surfaces of the support substrate on which the insulating layer is provided, further includes an active semiconductor layer formed on the insulating layer with the cavity pattern being closed, the active semiconductor layer not being formed in an outer peripheral portion of the support substrate, and further includes a plurality of superposition mark patterns formed in the outer peripheral portion on the one of the main surfaces of the support substrate for specifying a position of the cavity pattern.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: February 10, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhiro Shimizu, Junichi Yamashita, Takuichiro Shitomi
  • Patent number: 8951887
    Abstract: The invention relates to a process for fabricating a semiconductor that comprises providing a handle substrate comprising a seed substrate and a weakened sacrificial layer covering the seed substrate; joining the handle substrate with a carrier substrate; optionally treating the carrier substrate; detaching the handle substrate at the sacrificial layer to form the semiconductor structure; and removing any residue of the sacrificial layer present on the seed substrate.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: February 10, 2015
    Assignee: Soitec
    Inventors: Fabrice Letertre, Didier Landru
  • Patent number: 8927349
    Abstract: A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: January 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8921188
    Abstract: One illustrative method disclosed herein includes forming a trench within an isolated region of a bulk semiconductor substrate, forming a region of an insulating material in the trench and forming a semiconductor material within the trench and above the upper surface of the region of insulating material. A substrate disclosed herein includes an isolated substrate region in a bulk semiconductor substrate, a region of an insulating material that is positioned within a trench defined in the isolated substrate region and a semiconductor material positioned within the trench and above the upper surface of the region of insulating material.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: December 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ram Asra
  • Patent number: 8912057
    Abstract: A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: December 16, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Derya Deniz
  • Patent number: 8877618
    Abstract: The semiconductor-on-insulator substrate includes a support, an electrically insulating film, a crystalline film made from semiconductor material, and a protection layer. Germanium ions are implanted in the semiconductor material film through the protection layer so as to form an amorphized area in contact with the protection layer and a crystalline area in contact with the electrically insulating film. The semiconductor material film is annealed so as to recrystallize the amorphized area from the crystalline area.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: November 4, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Laurent Grenouillet, Maud Vinet, Yannick Le Tiec, Romain Wacquez, Olivier Faynot
  • Patent number: 8877570
    Abstract: An array substrate having a wiring of a pad region formed without an insulating film or without an insulating film and an organic film to reduce abnormal operations due to an increase in resistance caused by a contact margin at a high temperature, and a method for manufacturing the same are provided. The array substrate includes: an insulating substrate including a pad region and a thin film transistor (TFT) formation region; a first electrode layer formed in the pad region of the substrate; and a second electrode formed on the first electrode layer in an overlapping manner.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: November 4, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: JongWoo Kim, ChangHo Oh, WonHyung Yoo, SangYoon Paik, JunKi Kang, JongHoon Kim
  • Patent number: 8877604
    Abstract: A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions and their associated contacts. A high-k dielectric layer is provided between the raised source/drain regions and a gate conductor as well as between the gate conductor and a substrate, such as an ETSOI or PDSOI substrate. The structure is usable in electronic devices such as MOSFET devices.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8865534
    Abstract: In a manufacturing process of a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation through heat treatment and oxygen doping treatment are performed. A transistor including an oxide semiconductor film subjected to dehydration or dehydrogenation through heat treatment and oxygen doping treatment can be a highly reliable transistor having stable electric characteristics in which the amount of change in threshold voltage of the transistor between before and after the bias-temperature stress (BT) test can be reduced.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8829597
    Abstract: A nonvolatile memory device includes a plurality of channel connection layers formed over a substrate; a first gate electrode layer filling a space between the plurality channel connection layers; a gate dielectric layer interposed between each of the channel connection layers and the first gate electrode layer; a stacked structure formed over the plurality channel connection layers and the first gate electrode layer, the stacked structure including a plurality of interlayer dielectric layers and a plurality second gate electrode layers, which are alternately stacked; a pair of channel layers, formed through the stacked structure and connected to each channel connection layer of the plurality of channel connection layers; and a memory layer interposed between each of the channel layers and each of the second gate electrode layers.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: September 9, 2014
    Assignee: SK Hynix Inc.
    Inventor: Su-Chang Kwak
  • Patent number: 8823146
    Abstract: A semiconductor structure having a silicon substrate having a <111> crystallographic orientation, an insulating layer disposed over a first portion of the silicon substrate, a silicon layer having a <100> orientation disposed over the insulating layer, and a non-nitride column III-V semiconductor layer or column II-VI semiconductor layer having the same <111> crystallographic orientation as the silicon substrate, the non-nitride column III-V semiconductor layer or column II-VI semiconductor layer being in direct contact with a second portion of the silicon substrate. A column III-nitride is disposed on the surface of the third portion of the substrate.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: September 2, 2014
    Assignee: Raytheon Company
    Inventor: William E. Hoke
  • Patent number: 8802534
    Abstract: A bond substrate is attached with an incline toward the setting surface of a base substrate. Accordingly, an attachment starting portion can be limited. Further, the bond substrate is provided so that part of the bond substrate extends beyond a support base and the part is closest to the base substrate. Because of this, part of the bond substrate is separated from the support base with the use of an end portion of the support base as a fulcrum point because the support base is not provided below the contact portion, and attachment sequentially proceeds from a portion which gets close to the base substrate; thus, stable attachment can be performed without an air layer remaining at the interface between the bond substrate and the base substrate.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshihiro Komatsu, Tomoaki Moriwaka, Kojiro Takahashi
  • Patent number: 8772143
    Abstract: A method of forming a back gate transistor device includes forming an open isolation trench in a substrate; forming sidewall spacers in the open isolation trench; and using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench that serves as a back gate conductor, wherein the sidewall spacers prevent contamination of a channel region of the back gate transistor device by dopants.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi
  • Patent number: 8765571
    Abstract: A method and system are provided for manufacturing a base substrate that is used in manufacturing a semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: July 1, 2014
    Assignee: Soitec
    Inventors: Oleg Kononchuk, Frederic Allibert
  • Patent number: 8723296
    Abstract: A method includes forming a stress compensating stack over a substrate, where the stress compensating stack has compressive stress on the substrate. The method also includes forming one or more Group III-nitride islands over the substrate, where the one or more Group III-nitride islands have tensile stress on the substrate. The method further includes at least partially counteracting the tensile stress from the one or more Group III-nitride islands using the compressive stress from the stress compensating stack. Forming the stress compensating stack could include forming one or more oxide layers and one or more nitride layers over the substrate. The one or more oxide layers can have compressive stress, the one or more nitride layers can have tensile stress, and the oxide and nitride layers could collectively have compressive stress. Thicknesses of the oxide and nitride layers can be selected to provide the desired amount of stress compensation.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: May 13, 2014
    Assignee: National Semiconductor Corporation
    Inventor: Jamal Ramdani
  • Patent number: 8703531
    Abstract: An object is to provide a manufacturing method of an oxide semiconductor film with high crystallinity. Another object is to provide a manufacturing method of a transistor with high field effect mobility. In a manufacturing method of an oxide semiconductor film, an oxide semiconductor film is formed over a substrate in an atmosphere in which oxygen is purposely not contained, and then the oxide semiconductor film is crystallized by a heat treatment in an atmosphere containing oxygen.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: April 22, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Honda, Takatsugu Omata, Yusuke Nonaka
  • Patent number: 8669616
    Abstract: Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: March 11, 2014
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Xiaodong Yang, Yanxiang Liu, Vara Govindeswara Reddy Vakada, Jinping Liu, Min Dai
  • Publication number: 20140054698
    Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicant: STMicroelectronics, Inc.
    Inventors: Qing Liu, Nicolas Loubet, Prasanna Khare
  • Patent number: 8658508
    Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: February 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Shichi, Junichi Koezuka, Hideto Ohnuma, Shunpei Yamazaki
  • Patent number: 8652902
    Abstract: Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: February 18, 2014
    Assignee: IMEC
    Inventors: Pieter Blomme, Antonino Cacciato, Gouri Sankar Kar
  • Patent number: 8637932
    Abstract: In a semiconductor integrated circuit sandwiched between a pair of a first impact resistance layer and a second impact resistance layer, an impact diffusion layer is provided between the semiconductor integrated circuit and the second impact resistance layer. By provision of the impact resistance layer against the external stress and the impact diffusion layer for diffusing the impact, force applied to the semiconductor integrated circuit per unit area is reduced, so that the semiconductor integrated circuit is protected. The impact diffusion layer preferably has a low modulus of elasticity and high breaking modulus.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: January 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shingo Eguchi
  • Patent number: 8637383
    Abstract: Methods of fabricating semiconductor structures include forming a plurality of openings extending through a semiconductor material and at least partially through a metal material and deforming the metal material to relax a remaining portion of the semiconductor material. The metal material may be deformed by exposing the metal material to a temperature sufficient to alter (i.e., increase) its ductility. The metal material may be formed from one or more of hafnium, zirconium, yttrium, and a metallic glass. Another semiconductor material may be deposited over the remaining portions of the semiconductor material, and a portion of the metal material may be removed from between each of the remaining portions of the semiconductor material. Semiconductor structures may be formed using such methods.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: January 28, 2014
    Assignee: Soitec
    Inventor: Christiaan J. Werkhoven
  • Patent number: 8633065
    Abstract: The present invention relates to a method for manufacturing a mother substrate, the mother substrate comprising: a substrate comprising at least one display region and pre-cutting regions in a periphery of the display region, wherein the display region comprises gate scanning lines and data scanning lines, the pre-cutting regions comprise a gate-line connecting line and a data-line connecting line electrically connected to each other, and the gate-line connecting line is electrically connected to all of the gate scanning lines in the display region, and the data-line connecting line is electrically connected to all of the data scanning lines in the display region substrate.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: January 21, 2014
    Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
    Inventors: Huafeng Liu, Hongxi Xiao, Shunkang Su, Ping Wu, Hanting Ding
  • Patent number: 8633044
    Abstract: In a display region of an active matrix substrate, an interlayer insulating film made of a photosensitive organic insulating film, an insulating film different from the interlayer insulating film, and a plurality of pixel electrodes formed on a surface of the interlayer insulating film are provided. In a non-display region of the active matrix substrate, a lead line extended from the display region is formed. In a formation region for a sealing member, the interlayer insulating film is removed, the insulating film is provided to cover part of the lead line, and the sealing member is formed directly on a surface of the insulating film.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: January 21, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihito Hara, Yukinobu Nakata
  • Patent number: 8629030
    Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: January 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Shichi, Junichi Koezuka, Hideto Ohnuma, Shunpei Yamazaki
  • Patent number: 8629007
    Abstract: A method of making a gate of a field effect transistor (FET) with improved fill by a replacement gate process using a sacrificial film includes providing a substrate with a dummy gate. It further includes depositing a sacrificial layer and an encapsulating layer over the substrate, and planarizing so that the encapsulating layer, sacrificial layer and dummy gate are co-planar. The encapsulating layer and a portion of the sacrificial film are removed to leave a remaining sacrificial film. The dummy gate is removed to form and opening in the remaining sacrificial film and to expose sidewalls of the film. Spacers are formed on the sidewalls. A high dielectric constant film and metal film are deposited in the opening and planarized to form a gate. The remaining sacrificial film is removed. The method can be used on planar FETs as well non-planar FETs.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Balasubramanian S. Haran, James J. Demarest
  • Patent number: 8629501
    Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Brian J. Greene, Dureseti Chidambarrao, Gregory G. Freeman
  • Patent number: 8623712
    Abstract: A fin field-effect-transistor fabricated by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
  • Patent number: 8618554
    Abstract: The present disclosure, which is directed to ultra-thin-body-and-BOX and Double BOX fully depleted SOI devices having an epitaxial diffusion-retarding semiconductor layer that slows dopant diffusion into the SOI channel, and a method of making these devices. Dopant concentrations in the SOI channels of the devices of the present disclosure having an epitaxial diffusion-retarding semiconductor layer between the substrate and SOI channel are approximately 50 times less than the dopant concentrations measured in SOI channels of devices without the epitaxial diffusion-retarding semiconductor layer.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: December 31, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi
  • Patent number: 8617942
    Abstract: A method of producing a transistor includes providing a substrate including a first electrically conductive material layer. A resist material layer is deposited over the first electrically conductive material layer. The resist material layer is patterned to expose a portion of the first electrically conductive material layer. Some of the first electrically conductive material layer is removed to create a reentrant profile in the first electrically conductive material layer and expose a portion of the substrate. The first electrically conductive material layer and at least a portion of the substrate are conformally coated with an electrically insulating material layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: December 31, 2013
    Assignee: Eastman Kodak Company
    Inventors: Shelby F. Nelson, Lee W. Tutt
  • Patent number: 8598646
    Abstract: An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: December 3, 2013
    Assignee: Spansion LLC
    Inventors: Chun Chen, Shenqing Fang
  • Patent number: 8598013
    Abstract: To provide a method for manufacturing an SOI substrate provided with a semiconductor layer which can be used practically even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like is used. The semiconductor layer is transferred to a supporting substrate by the steps of irradiating a semiconductor wafer with ions from one surface to form a damaged layer; forming an insulating layer over one surface of the semiconductor wafer; attaching one surface of the supporting substrate to the insulating layer formed over the semiconductor wafer and performing heat treatment to bond the supporting substrate to the semiconductor wafer; and performing separation at the damaged layer into the semiconductor wafer and the supporting substrate. The damaged layer remaining partially over the semiconductor layer is removed by wet etching and a surface of the semiconductor layer is irradiated with a laser beam.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: December 3, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideto Ohnuma, Yoichi Iikubo, Yoshiaki Yamamoto, Kenichiro Makino
  • Patent number: 8587025
    Abstract: A method for forming a laterally varying n-type doping concentration is provided. The method includes providing a semiconductor wafer with a first surface, a second surface arranged opposite to the first surface and a first n-type semiconductor layer having a first maximum doping concentration, implanting protons of a first maximum energy into the first n-type semiconductor layer, and locally treating the second surface with a masked hydrogen plasma. Further, a semiconductor device is provided.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: November 19, 2013
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina
  • Patent number: 8569152
    Abstract: A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Huiming Bu, Kangguo Cheng, Balasubramanian S. Haran, Nicolas Loubet, Shom Ponoth, Stefan Schmitz, Theodorus E Standaert, Tenko Yamashita
  • Patent number: 8557668
    Abstract: Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: October 15, 2013
    Assignee: GLOBALFOUNDRIES SINGAPORE Pte. Ltd.
    Inventors: Xiaodong Yang, Yanxiang Liu, Vara Govindeswara Reddy Vakada, Jinping Liu, Min Dai
  • Patent number: 8541841
    Abstract: Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: September 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-joo Kim, Sang-moo Choi, Tae-hee Lee, Yoon-dong Park
  • Patent number: RE44531
    Abstract: A thin film transistor includes a gate, a gate insulator layer, a channel layer, a source, a drain, and an ohmic contact layer. The gate insulator layer covers the gate; the channel layer is disposed on the gate insulator layer above the gate; the source and the drain are disposed on the channel layer; the ohmic contact layer is disposed between the channel layer and the source and drain. The ohmic contact layer is constituted by a number of film layers. As mentioned above, the thin film transistor has an ohmic contact layer constituted by a number of film layers. When the thin film transistor is turned off, the current leakage thereof is lowered than that of a conventional thin film transistor.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: October 8, 2013
    Assignee: Intellectual Ventures Fund 82 LLC
    Inventors: Min-Ching Hsu, Yung-Lung Mo