Using Silicon Etch Back Technique, E.g., Besoi, Eltran (epo) Patents (Class 257/E21.569)
  • Patent number: 9331227
    Abstract: A semiconductor device may include a first subassembly and a second subassembly. The first subassembly may include a first bonding layer. The second subassembly may include a second substrate and a second bonding layer directly bonded to the first bonding layer. The first bonding layer and the second bonding layer may be lattice-mismatched to one another. At least one of the following may be selected: the first bonding layer is lattice-mismatched to the first substrate, and the second bonding layer is lattice-mismatched to the second substrate.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: May 3, 2016
    Assignee: THE BOEING COMPANY
    Inventors: Daniel C. Law, Richard R. King, Dimitri Daniel Krut, Dhananjay Bhusari
  • Patent number: 8975668
    Abstract: A structure and method of manufacture is disclosed for a backside thinned imager that incorporates a conformal, Al2O3, low thermal budget, surface passivation. This passivation approach facilitates fabrication of backside thinned, backside illuminated, silicon image sensors with thick silicon absorber layer patterned with vertical trenches that are formed by etching the exposed back surface of a backside-thinned image sensor to control photo-carrier diffusion and optical crosstalk. A method of manufacture employing conformal, Al2O3, surface passivation approach is shown to provide high quantum efficiency and low dark current while meeting the thermal budget constraints of a finished standard foundry-produced CMOS imager.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 10, 2015
    Assignee: Intevac, Inc.
    Inventors: Kenneth A. Costello, Edward Yin, Michael Wayne Pelczynski, Verle W. Aebi
  • Patent number: 8802540
    Abstract: The present invention provides a method of manufacturing a bonded wafer. The method includes ozone washing two silicon wafers to form an oxide film equal to or less than 2.2 nm in thickness on each surface of the two silicon wafers, and bonding the two silicon wafers through the oxide films formed to obtain a bonded wafer.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: August 12, 2014
    Assignee: Sumco Corporation
    Inventors: Nobuyuki Morimoto, Akihiko Endo
  • Patent number: 8791017
    Abstract: Disclosed herein are various methods of forming conductive structures, such as conductive lines and via, on an integrated circuit device using a spacer erosion technique. In one example, the method includes forming a patterned hard mask layer above a layer of insulating material, the patterned hard mask having a hard mask opening, forming an erodible spacer in the hard mask opening to thereby define a spacer opening and performing at least one etching process through the spacer opening on the layer of insulating material to define a trench therein for a conductive structure, wherein the erodible spacer is substantially eroded away during the at least one etching process.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: July 29, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Gunter Grasshoff
  • Patent number: 8685836
    Abstract: A method for forming a silicon layer according to inventive concept comprises: preparing an SOI substrate; applying an etchant or vapor of the etchant to the SOI substrate; and irradiating a light to the SOI substrate.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: April 1, 2014
    Assignee: Industry-Academic Corporation Foundation, Yonsei University
    Inventors: Taeyoon Lee, Ja Hoon Koo, Sang Wook Lee, Ka Young Lee
  • Patent number: 8679946
    Abstract: A process for manufacturing a stacked structure comprising at least one thin layer bonded to a target substrate, in which a thin layer is formed by introduction gaseous species into an initial substrate, to form a weakened layer separating a film from the rest of the initial substrate, a first contact face of the thin layer is bonded to a face of an intermediate substrate by molecular adhesion, and the initial substrate is fractured at the weakened layer so as to expose a free face of the thin layer. The intermediate substrate is then removed in order to obtain the stacked structure.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 25, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Hubert Moriceau, Bernard Aspar, Eric Jalaguier, Fabrice Letertre
  • Patent number: 8551862
    Abstract: To provide a method of manufacturing a laminated wafer by which a strong coupling is achieved between wafers made of different materials having a large difference in thermal expansion coefficient without lowering a maximum heat treatment temperature as well as in which cracks or chips of the wafer does not occur. A method of manufacturing a laminated wafer 7 by forming a silicon film layer on a surface 4 of an insulating substrate 3 comprising the steps in the following order of: applying a surface activation treatment to both a surface 2 of a silicon wafer 1 or a silicon wafer 1 to which an oxide film is layered and a surface 4 of the insulating substrate 3 followed by laminating in an atmosphere of temperature exceeding 50° C. and lower than 300° C., applying a heat treatment to a laminated wafer 5 at a temperature of 200° C. to 350° C., and thinning the silicon wafer 1 by a combination of grinding, etching and polishing to form a silicon film layer.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: October 8, 2013
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Makoto Kawai, Kouichi Tanaka, Yuji Tobisaka, Yoshihiro Nojima
  • Patent number: 8513092
    Abstract: A method for producing a stacked structure having an ultra thin buried oxide (UTBOX) layer therein by forming an electrical insulator layer on a donor substrate, introducing elements into the donor substrate through the insulator layer, forming an electrical insulator layer, on a second substrate, and bonding the two substrates together to form the stack, with the two insulator layers limiting the diffusion of water and forming the UTBOX layer between the two substrates at a thickness of less than 50 nm, wherein the donor oxide layer has, during bonding, a thickness at least equal to that of the bonding oxide layer.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: August 20, 2013
    Assignee: Soitec
    Inventor: Didier Landru
  • Patent number: 8486814
    Abstract: A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jennifer C. Clark, Emily R. Kinser, Ian D. Melville, Candace A. Sullivan
  • Patent number: 8481409
    Abstract: The invention relates to a process for manufacturing a stacked structure comprising at least one thin layer bonding to a target substrate, comprising the following steps: a) formation of a thin layer starting from an initial substrate, the thin layer having a free face called the first contact face, b) putting the first contact face into bonding contact with a face of an intermediate support, the structure obtained being compatible with later thinning of the initial substrate, c) thinning of the said initial substrate to expose a free face of the thin layer called the second contact face and opposite the first contact face, d) putting a face of the target substrate into bonding contact with at least part of the second contact face, the structure obtained being compatible with later removal of all or some of the intermediate support, e) removal of at least part of the intermediate support in order to obtain the said stacked structure.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: July 9, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Hubert Moriceau, Bernard Aspar, Eric Jalaguier, Fabrice Letertre
  • Patent number: 8476146
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a first layer on a first side of a first silicon wafer. The first silicon wafer has a second side opposite the first side. The first layer has a coefficient-of-thermal-expansion (CTE) that is lower than that of silicon. The method includes bonding the first wafer to a second silicon wafer in a manner so that the first layer is disposed in between the first and second silicon wafers. The method includes removing a portion of the first silicon wafer from the second side. The method includes forming a second layer over the second side of the first silicon wafer. The second layer has a CTE higher than that of silicon.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: July 2, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang
  • Patent number: 8394660
    Abstract: Devices having features deposited on two sides of a device substrate and methods for making the same. The devices are useful, for example, as the components in a macroelectronic system. In a preferred embodiment, the devices are photosensors having a plurality of electrodes patterned on a first side of the device and an electromagnetic interference filter patterned on a second side of the device. The method facilitates the fabrication of two-sided devices through the use of an immobilizing layer deposited on top of devices patterned on a first side of a device substrate; flipping the device substrate; processing the second side of the device substrate to produce patterned features on the second side of the device substrate; and releasing the devices having patterned elements on two sides of each device.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: March 12, 2013
    Assignee: University of Washington its Center for Commercialization
    Inventors: Samuel Kim, Babak Amirparviz
  • Patent number: 8394703
    Abstract: When the single crystal semiconductor layer is melted, the outward diffusion of oxygen is promoted. Specifically, an SOI substrate is formed in such a manner that an SOI structure having a bonding layer including oxygen provided over a base substrate and a single crystal semiconductor layer provided over the bonding layer including oxygen is formed, and part of the single crystal semiconductor layer is melted by irradiation with a laser beam in a state that the base substrate is heated at a temperature of higher than or equal to 500° C. and lower than a melting point of the base substrate.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: March 12, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Junpei Momo, Shunpei Yamazaki
  • Patent number: 8357586
    Abstract: Provided is a method for manufacturing an SOI wafer, which is capable of: efficiently removing an ion-implanted defect layer existing in an ion implanted layer in the vicinity of a peeled surface peeled by an ion implantation peeling method; ensuring the in-plane uniformity of a substrate; and also achieving cost reduction and higher throughput. The method for manufacturing an SOI wafer includes at least the steps of: bonding a silicon wafer with or without an oxide film onto a handle wafer to prepare a bonded substrate, wherein the silicon wafer has an ion implanted layer formed by implanting hydrogen ions and/or rare gas ions into the silicon wafer; peeling the silicon wafer along the ion implanted layer, thereby transferring the silicon wafer onto the handle wafer to produce a post-peeling SOI wafer; immersing the post-peeling SOI wafer in an aqueous ammonia-hydrogen peroxide solution; and performing a heat treatment at a temperature of 900° C.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: January 22, 2013
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Kouichi Tanaka, Makoto Kawai, Yuji Tobisaka, Hiroshi Tamura
  • Patent number: 8298915
    Abstract: Method for forming a semi-conducting structure includes the formation of at least one part of a circuit or a component, in or on a superficial layer of a substrate, the substrate including a buried layer underneath the superficial layer, and an underlying layer serving as first support, a transfer of said substrate onto a handle substrate, and then an elimination of the first support, the formation of an electrically conducting or ground plane forming layer, on at least one part of said buried layer, the formation, on said electrically conducting or ground plane forming layer, of a bonding layer, a transfer of the structure obtained onto a second support and an elimination of said handle substrate.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: October 30, 2012
    Assignee: S.O.I. Tec Silicon on Insulator Technologies
    Inventor: Bernard Aspar
  • Patent number: 8278189
    Abstract: The present invention provides a method of thinning a wafer. First, a wafer is provided. The wafer includes an active surface, a back surface and a side surface. The active surface is disposed opposite to the back surface. The side surface is disposed between the active surface and the back surface and encompasses the peripheral of the wafer. Next, a protective structure is formed on the wafer to at least completely cover the side surface. Last, a thinning process is performed upon the wafer from the back surface.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: October 2, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Cheng-Yu Hsieh
  • Patent number: 8193076
    Abstract: The present disclosure relates to methods and apparatuses template. The method involves forming a mechanically weak layer conformally on a semiconductor template. Then forming a thin for releasing a thin semiconductor substrate from a reusable semiconductor substrate conformally on the mechanically weak layer. The thin semiconductor substrate, the mechanically weak layer and the template forming a wafer. Then defining the border of the thin-film semiconductor substrate to be released by exposing the peripheral of the mechanically weak layer. Then releasing the thin-film semiconductor substrate by applying a controlled air flow parallel to said mechanically weak layer wherein the controlled air flow separates the thin semiconductor substrate and template according to lifting forces.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: June 5, 2012
    Assignee: Solexel, Inc.
    Inventors: Mehrdad M. Moslehi, David Xuan-Qi Wang, Sam Tone Tor, Karl-Josef Kramer
  • Patent number: 8003461
    Abstract: A method of fabricating an efuse structure, a resistor structure and a transistor structure. First, a work function metal layer, a polysilicon layer and a first hard mask layer are formed to cover a transistor region, a resistor region and an e-fuse region on a substrate. Then, the work function metal layer on the resistor region and the efuse region is removed by using a first photomask. Later, a gate, a resistor, an efuse are formed in the transistor region, the resistor region and the efuse region respectively. After that, a dielectric layer aligning with the top surface of the gate is formed. Later, the polysilicon layer in the gate is removed by taking a second hard mask as a mask to form a recess. Finally, a metal layer fills up the recess.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: August 23, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Che-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen, Shao-Hua Hsu
  • Patent number: 7939428
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving substrate and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: May 10, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative
  • Patent number: 7915079
    Abstract: A layered chip package includes a main body, and wiring disposed on at least one side surface of the main body. The main body includes a plurality of layer portions stacked. In a method of manufacturing the layered chip package, a plurality of structures are initially formed. Each structure includes at least one main-body-forming portion that is to be the main body and that has a pre-wiring surface. Next, the plurality of structures are surrounded with a jig and thereby aligned so that their pre-wiring surfaces face upward. The jig has a top surface that is lower in level than the pre-wiring surfaces. Next, a resin layer covering the jig and the structures is formed using a resin film. Next, the resin layer is polished until the pre-wiring surfaces are exposed. Next, the wiring is formed on the pre-wiring surfaces simultaneously. Next, the main-body-forming portions are separated from each other.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: March 29, 2011
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
  • Patent number: 7910455
    Abstract: The present invention relates to a method for producing an SOI wafer, having at least a step of a bonding heat treatment for increasing bonding strength by heat-treating a bonded wafer obtained by bonding a base wafer and a bond wafer, in which argon is ion-implanted from a surface of either the base wafer or the bond wafer at a dosage of 1×1015 atoms/cm2 or more at least before the bonding step, the surface ion-implanted with argon is used as a bonding surface in the bonding step, and an increase rate of temperature to a treatment temperature of the bonding heat treatment is 5° C./minute or higher. Thus the present invention provides a method for producing an SOI wafer facilitating the efficient production of an SOI wafer having in the neighborhood of a buried insulator layer thereof a polycrystalline silicon layer uniform in thickness introduced and having high gettering ability toward metal contaminations in the SOI layer by a simple and low-cost method.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: March 22, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kazuhiko Yoshida, Masao Matsumine, Hiroshi Takeno
  • Publication number: 20100311212
    Abstract: In a liquid crystal display device, a first substrate includes electrical wirings and a semiconductor integrated circuit which has TFTs and is connected electrically to the electrical wirings, and a second substrate includes a transparent conductive film on a surface thereof. A surface of the first substrate that the electrical wirings are formed is opposite to the transparent conductive film on the second substrate. the semiconductor integrated circuit has substantially the same length as one side of a display screen (i.e., a matrix circuit) of the display device and is obtained by peeling it from another substrate and then forming it on the first substrate. Also, in a liquid crystal display device, a first substrate includes a matrix circuit and a peripheral driver circuit, and a second substrate is opposite to the first substrate, includes a matrix circuit and a peripheral driver circuit and has at least a size corresponding to the matrix circuit and the peripheral driver circuit.
    Type: Application
    Filed: July 28, 2010
    Publication date: December 9, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Setsuo Nakajima, Yasuyuki Arai
  • Publication number: 20100311222
    Abstract: When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor elements, are transposed to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. Further, etching is performed on the single crystal semiconductor layers formed over the base substrate, and the shapes of the SOI layers are controlled precisely by being processed and modified.
    Type: Application
    Filed: August 18, 2010
    Publication date: December 9, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Ikuko KAWAMATA, Yasuyuki ARAI
  • Patent number: 7839001
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: November 23, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Giséle Rayssac, legal representative
  • Publication number: 20100244182
    Abstract: To provide a method of manufacturing a laminated wafer by which a strong coupling is achieved between wafers made of different materials having a large difference in thermal expansion coefficient without lowering a maximum heat treatment temperature as well as in which cracks or chips of the wafer does not occur. A method of manufacturing a laminated wafer 7 by forming a silicon film layer on a surface 4 of an insulating substrate 3 comprising the steps in the following order of: applying a surface activation treatment to both a surface 2 of a silicon wafer 1 or a silicon wafer 1 to which an oxide film is layered and a surface 4 of the insulating substrate 3 followed by laminating in an atmosphere of temperature exceeding 50° C. and lower than 300° C., applying a heat treatment to a laminated wafer 5 at a temperature of 200° C. to 350° C., and thinning the silicon wafer 1 by a combination of grinding, etching and polishing to form a silicon film layer.
    Type: Application
    Filed: January 11, 2010
    Publication date: September 30, 2010
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Makoto Kawai, Kouichi Tanaka, Yuji Tobisaka, Yoshihiro Nojima
  • Patent number: 7786587
    Abstract: A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20, and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20. The through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12, and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: August 31, 2010
    Assignee: Spansion LLC
    Inventors: Masataka Hoshino, Ryoto Fukuyama, Koji Taya
  • Patent number: 7767494
    Abstract: A manufacturing method for a layered chip package including a stack of a plurality of layer portions includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: August 3, 2010
    Assignees: Headway Technologies, Inc., TDK Corporation
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
  • Patent number: 7691724
    Abstract: A method for manufacturing an SOI substrate, including the steps of implanting hydrogen ions from a main surface of a single-crystal silicon substrate having an interstitial oxygen concentration which is equal to or below 1×1018 cm?3; performing an activation treatment with respect to the main surface of at least one of a transparent insulative substrate and the silicon substrate; bonding the main surface of the transparent insulative substrate to the main surface of the silicon substrate at a room temperature; performing a heat treatment with respect to the bonded substrate at a temperature falling within the range of 350° C. to 550° C. and having a cooling rate after the heat treatment that is equal to or below 5° C./minute; and mechanically delaminating a silicon thin film from the silicon substrate to form a silicon film on the main surface of the transparent insulative substrate.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: April 6, 2010
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Makoto Kawai, Yoshihiro Kubota, Atsuo Ito, Koichi Tanaka, Yuuji Tobisaka, Shoji Akiyama
  • Publication number: 20100068868
    Abstract: A wafer temporary bonding method using silicon direct bonding (SDB) may include preparing a carrier wafer and a device wafer, adjusting roughness of a surface of the carrier wafer, and combining the carrier wafer and the device wafer using the SDB. Because the method uses SDB, instead of an adhesive layer, for a temporary bonding process, a module or process to generate and remove an adhesive is unnecessary. Also, a defect in a subsequent process, for example, a back-grinding process, due to irregularity of the adhesive may be prevented.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 18, 2010
    Inventors: Jung-ho Kim, Dae-lok Bae, Jong-wook Lee, Seung-woo Choi, Pil-kyu Kang
  • Patent number: 7666781
    Abstract: Interconnect structures including liner layers that are non-planar with at least the adjacent insulating layer and at least one capping layer on conductive features embedded in the insulating layer. The interconnect structure includes an insulating layer of a dielectric material having a top surface and a bottom surface between the top surface and a substrate. An opening, such as a trench, has sidewalls extending from the top surface of the insulating layer toward the bottom surface and is at least partially filled by a conductive feature. A capping layer is disposed on at least a top surface of the conductive feature. A conductive liner layer is disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer has sidewall portions projecting above the top surface of the insulating layer adjacent to the sidewalls of the opening.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Louis Lu-Chen Hsu, Jack Allan Mandelman, William Robert Tonti, Chih-Chao Yang
  • Patent number: 7615468
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: November 10, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative
  • Patent number: 7595259
    Abstract: A compound semiconductor substrate manufacturing method suitable for manufacturing a compound semiconductor element having high electrical characteristics. The compound semiconductor substrate manufacturing method is a method for manufacturing a compound semiconductor substrate having pn junction, including an epitaxial growing process, a selective growing process and other discretionary processes after the epitaxial growing process. The highest temperatures in the selective growing process and other discretionary processes after the epitaxial growing process are lower than that in the epitaxial growing process prior to the selective growing process.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: September 29, 2009
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kenji Kohiro, Kazumasa Ueda, Masahiko Hata
  • Patent number: 7531429
    Abstract: Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon layer. The porous silicon layer and temporary support are then removed and packaging is completed. Embodiments of the invention provide reliable, low cost methods and apparatuses for producing reduced-thickness IC device wafers to substantially increase thermal conductivity between the device layer of an IC device and a heat sink. In alternative embodiments, the layered silicon substrate includes an insulator layer on a layer of porous silicon and a silicon layer on the insulator layer.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Peter Tolchinsky, Irwin Yablok, Chuan Hu, Richard D. Emery
  • Patent number: 7498234
    Abstract: The invention relates to a method of producing a thin layer of semiconductor material including: a step of implanting ions through a flat face (2) of a semiconductor wafer in order to create a layer of microcavities, the ion dose being within a specific range in order to avoid the formation of blisters on the flat face, a thermal treatment step in order to achieve coalescence of the microcavities possibly, a step of creating at least one electronic component (5) in the thin layer (6), a separation step of separating the thin layer (6) from the rest (7) of the wafer.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: March 3, 2009
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Bernard Aspar, Michel Bruel, Thierry Poumeyrol
  • Patent number: 7476576
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: January 13, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: 7473592
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: January 6, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: 7465647
    Abstract: With non-contact and contact IC chips becoming common, it is necessary to mass-produce enormous amount of IC chips, which are utilizable for human beings, animals and plants, commercial products, banknotes, and the like, at low cost. For example, it is necessary to manufacture IC chips to be applied to commercial products, banknotes, and the like at a cost of 1 to several yen per IC chip, preferably, at a cost less than 1 yen, and it is desired to realize a structure of an IC chip that can be mass-produced at low cost and a manufacturing process of the IC chip.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: December 16, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Yohei Kanno
  • Patent number: 7452786
    Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. A feature of the invention is to use a metal film and a reactant having the metal film as a separation layer. An etching rate of the metal film or the reactant having metal is high, and a physical means in addition to a chemical means of etching the metal film or the reactant having metal can be used in the invention. Thus, the IDF chip can be manufactured more simply and easily in a short time.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: November 18, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Dozen, Tomoko Tamura, Takuya Tsurume, Koji Dairiki
  • Patent number: 7436075
    Abstract: The ion beam irradiation apparatus has a vacuum chamber 10, an ion source 2, a substrate driving mechanism 30, rotation shafts 14, arms 12, and a motor. The ion source 2 is disposed inside the vacuum chamber 10, and emits an ion beam 4 which is larger in width than a substrate 6, to the substrate 6. The substrate driving mechanism 30 reciprocally drives the substrate 6 in the vacuum chamber 10. The center axes 14a of the rotation shafts 14 are located in a place separated from the ion source 2 toward the substrate, and substantially parallel to the surface of the substrate. The arms 12 are disposed inside the vacuum chamber 10, and support the ion source 2 through the rotation shafts 14. The motor is disposed outside the vacuum chamber 10, and reciprocally rotates the rotation shaft 14.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: October 14, 2008
    Assignee: Nissin Ion Equipment Co., Ltd.
    Inventor: Yasunori Ando
  • Patent number: 7354863
    Abstract: An etch solution that comprises tetramethylammonium hydroxide (“TMAH”) and at least one organic solvent. The etch solution may be substantially free of water. The etch solution is formulated to selectively etch a silicon layer relative to other layers on an integrated circuit. The TMAH may be present in an amount ranging from approximately 1% by weight to approximately 10% by weight. The at least one organic solvent may be selected from the group consisting of isopropanol, butanol, hexanol, phenol, glycol, glycerol, ethylene glycol, propylene glycol, glycerin, and mixtures thereof. A method of selectively etching a silicon layer and a method of removing a heat-affected zone (“HAZ”) on an integrated circuit are also disclosed.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: April 8, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Kevin J. Torek
  • Patent number: 7279751
    Abstract: It is an object of the present invention to provide a semiconductor laser device with high-yielding in which a clack generated in an epitaxial growth layer is restrained and to the manufacturing method thereof, the semiconductor laser device includes a GaN substrate 1, an n-type GaN layer 2, an n-type AlGaN cladding layer 3, a n-type GaN guide layer 4, an InGaN multiple quantum well active layer 5, an undoped-GaN guide layer 6, a p-type AlGaN electron overflow suppression layer 7, a p-type GaN guide layer 8, a SiO2 blocking layer 9, an Ni/ITO cladding layer electrode 10 as a transparent electrode, a Ti/Au pad electrode 11, and a Ti/Al/Ni/Au electrode 12. The SiO2 blocking layer 9 is formed above the InGaN multiple quantum well active layer 5 so as to have an opening. The Ni/ITO cladding layer electrode 10 is formed inside the opening, and which is transparent for the light from the InGaN multiple quantum well active layer, and serves as a cladding layer.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: October 9, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuzo Ueda, Masaaki Yuri
  • Patent number: 7273797
    Abstract: The invention encompasses a method of forming a semiconductor-on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is formed within the insulative mass. The material comprises one or more of nitrogen argon, fluorine, bromine, chlorine, iodine and germanium.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 7271076
    Abstract: A method of manufacturing a thin film integrated circuit device according to the present invention includes steps of forming a peel-off layer over a thermally oxidized silicon substrate, forming a plurality of thin film integrated circuit devices over the peel-off layer with a base film interposed therebetween, forming a groove between the plurality of thin film integrated circuit devices, and separating the plurality of thin film integrated circuit devices by introducing one of a gas and a liquid including halogen fluoride into the groove to remove the peel-off layer.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: September 18, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Yohei Kanno
  • Patent number: 7256104
    Abstract: An SOI substrate which has a thick SOI layer is first prepared. Then, the SOI layer is thinned to a target film thickness using as a unit a predetermined thickness not more than that of one lattice. This thinning is performed by repeating a unit thinning step which includes an oxidation step of oxidizing the surface of the SOI layer by the predetermined thickness not more than that of one lattice and a removal step of selectively removing silicon oxide formed by the oxidation. The SOI layer of the SOI substrate is chemically etched by supplying a chemical solution to the SOI layer, and the film thickness of the etched SOI layer is measured. When the measured film thickness of the SOI layer has a predetermined value, a process of chemically etching the SOI layer ends.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: August 14, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masataka Ito, Kenji Yamagata, Yasuo Kakizaki, Kazuhito Takanashi, Hiroshi Miyabayashi, Ryuji Moriwaki, Takashi Tsuboi
  • Patent number: 7235478
    Abstract: A polymer spacer material may increase the dimensions of the patterned photoresist that is used as a mask to etch the layers below the photoresist, which in turn translates into smaller dimensions etched into the underlying materials. This allows for the formation of integrated circuits having smaller features, smaller overall size, and greater density of features. In particular, the use of a polymer spacer material allows for the formation of contacts within flash memory cells having decreased dimensions so that higher density flash memory cells may be created without causing shorts between contacts or shorts due to misalignment of the contacts. Additionally, the use of the polymer spacer material extends the use of photolithography technologies that are used to form the patterns into the photoresists.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: June 26, 2007
    Assignee: Intel Corporation
    Inventors: Quain Geng, Jeff Junhao Xu
  • Patent number: 7229892
    Abstract: A method of manufacturing a semiconductor device, includes preparing a semiconductor substrate, bonding a first semiconductor layer onto a part of the semiconductor substrate with a first insulating layer interposed therebetween, forming a second insulating layer on a side of the first semiconductor layer, epitaxially growing a second semiconductor layer in a region on the semiconductor substrate other than a region formed with the first insulating layer, forming a first semiconductor element in the first semiconductor layer on the first insulating layer, and forming a second semiconductor element in the second semiconductor layer on the second insulating layer.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: June 12, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Usuda, Shinichi Takagi
  • Patent number: RE42097
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: February 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: RE42241
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: March 22, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani