Using Bonding Technique (epo) Patents (Class 257/E21.567)
  • Patent number: 10446729
    Abstract: A display device is provided. The display device includes a substrate and a first metal line and a second metal line disposed on the substrate. The display device includes a first pad and a second pad disposed on the substrate and electrically connected to the first metal line and the second metal line respectively. The display device further includes an electronic device disposed on the first pad and the second pad. The electronic device includes a first connecting post and a second connecting post, wherein a distance between the first connecting post and the second connecting post is in a range from 1 um to 200 um. A portion of the first connecting post is embedded in the first pad and a portion of the second connecting post is embedded in the second pad.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 15, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Jia-Yuan Chen, Tsung-Han Tsai, Kuan-Feng Lee, Yuan-Lin Wu
  • Patent number: 10446754
    Abstract: A flexible organic light-emitting diode display and a method of manufacturing the same are disclosed. In one aspect, the display includes a substrate formed of a first material including a metal and an OLED formed over the substrate.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ki Hyun Kim, Sun Ho Kim, Jeong Ho Kim, Hyun Woo Koo, Tae Woong Kim, Yeon Gon Mo
  • Patent number: 10297784
    Abstract: A folding type display apparatus, which includes a first flexible substrate including a laminate of an inorganic film and an organic film; a sheet-shaped display section formed over the first flexible substrate and having flexibility, the sheet-shaped display section including a plurality of organic electro luminescence (EL) elements and a plurality of switching elements; and a second flexible substrate including a laminate of an inorganic film and an organic film and formed over the sheet-shaped display section, wherein the first and second flexible substrates include a plurality of the laminates respectively, and the inorganic films and the organic films are alternately laminated in the plurality of laminates.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 21, 2019
    Assignee: TIANMA JAPAN, LTD.
    Inventor: Yojiro Matsueda
  • Patent number: 10128145
    Abstract: Integrated circuits and manufacturing methods are presented for creating diffusion resistors (101, 103) in which the diffusion resistor well is spaced from oppositely doped wells to mitigate diffusion resistor well depletion under high biasing so as to provide reduced voltage coefficient of resistivity and increased breakdown voltage for high-voltage applications.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: November 13, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kamel Benaissa, Amitava Chatterjee
  • Patent number: 10096724
    Abstract: A chip for radiation measurements, the chip comprising a first substrate comprising a first sensor and a second sensor. The chip moreover comprises a second substrate comprising a first cavity and a second cavity both with oblique walls. An internal layer is present on the inside of the second cavity. The second substrate is sealed to the first substrate with the cavities on the inside such that the first cavity is above the first sensor and the second cavity is above the second sensor.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 9, 2018
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventors: Carl Van Buggenhout, Appolonius Jacobus Van Der Wiel, Luc Buydens
  • Patent number: 9929190
    Abstract: It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: March 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yumiko Ohno
  • Patent number: 9914640
    Abstract: A method for manufacturing a micromechanical component including a substrate and a cap, which is connected to the substrate and, together with the substrate, encloses a first cavity, a first pressure prevailing and a first gas mixture having a first chemical composition being enclosed in the first cavity, includes in a first task, an access opening connecting the first cavity to surroundings of the component is formed in the substrate or cap, in a second task, the first pressure and/or the first chemical composition is adjusted in the first cavity, in a third task, the access opening is sealed by introducing energy or heat into an absorbing part of the substrate or cap with a laser, the introduction of the energy or heat occurring by adjusting the extension of the absorbing part and adjusting the absorption strength in the absorbing part to minimize stresses occurring in the substrate or cap.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: March 13, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventors: Mawuli Ametowobla, Philip Kappe
  • Patent number: 9892911
    Abstract: An epitaxial structure includes a substrate, a first epitaxial layer and a second epitaxial layer. The substrate has a surface, and the first epitaxial layer is disposed over the substrate and defines a plurality of slanting air voids tapering away from the substrate and an opening over each of the slanting air voids. The second epitaxial layer is disposed on the first epitaxial layer and collectively defines the slanting air voids in a shape of trapezoid with the first epitaxial layer.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: February 13, 2018
    Assignee: Lextar Electronics Corporation
    Inventors: Jun-Rong Chen, Hsiu-Mei Chou, Jhao-Cheng Ye
  • Patent number: 9685627
    Abstract: A novel functional panel is provided. The functional panel includes a first substrate, a second substrate, a first layer, a second layer, a sealing portion, and a first adhesive layer. The sealing portion is between the first layer and the second layer. The first adhesive layer is between the first layer and the first substrate. The second substrate is in contact with the second layer. When a surface of the first layer which faces the first substrate is referred to as a first surface and a surface of the second layer which is in contact with the second substrate is referred to as a second surface, the functional panel has a plurality of regions having different distances between the first surface and the second surface.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 20, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akihiro Chida
  • Patent number: 9520533
    Abstract: A UV light emitting device and a method for fabricating the same are disclosed. The method includes forming a first super-lattice layer including AlxGa(1-x)N on a substrate, forming a sacrificial layer including AlzGa(1-z)N on the first super-lattice layer, partially removing the sacrificial layer, forming an epitaxial layer on the sacrificial layer, and separating the substrate from the epitaxial layer, wherein the sacrificial layer includes voids, the substrate is separated from the epitaxial layer at the sacrificial layer, and forming an epitaxial layer includes forming an n-type semiconductor layer including n-type AluGa(1-u)N (0<u?z?x<1). With this structure, the light emitting device can emit UV light and be separated from the substrate.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: December 13, 2016
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Chang Suk Han, Hwa Mok Kim, Mi So Ko, A Ram Cha Lee, Dae Woong Suh
  • Patent number: 9496128
    Abstract: Method for a controlled spalling utilizing vaporizable release layers. For example, a method comprises providing a base substrate, depositing a stressor layer and a vaporizable release layer on the base substrate, forming a flexible support layer on at least one of the stressor layer and the vaporizable release layer, spalling an upper portion of the base substrate, securing the spalled upper portion of the base substrate to a handle substrate, and vaporizing the vaporizable release layer.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: November 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Katherine L. Saenger
  • Patent number: 9404946
    Abstract: An electronic apparatus includes a first voltage detection circuit which detects when a voltage, becomes higher than a first level after the voltage starts to be supplied to a peripheral circuit, and detects when the voltage becomes lower than a second level after a supply of the voltage to the peripheral circuit starts to be interrupted, and a second voltage detection circuit which detects when the voltage becomes lower than a reference level while the peripheral circuit operates. The second level is lower than the reference level.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: August 2, 2016
    Assignee: SK Hynix Inc.
    Inventor: Hyun Chul Lee
  • Patent number: 9372211
    Abstract: An electronic apparatus includes a first voltage detection circuit which detects when a voltage, becomes higher than a first level after the voltage starts to be supplied to a peripheral circuit, and detects when the voltage becomes lower than a second level after a supply of the voltage to the peripheral circuit starts to be interrupted, and a second voltage detection circuit which detects when the voltage becomes lower than a reference level while the peripheral circuit operates. The second level is lower than the reference level.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: June 21, 2016
    Assignee: SK Hynix Inc.
    Inventor: Hyun Chul Lee
  • Patent number: 9368376
    Abstract: A mechanical debonding method and system are provided. A mechanical debonding method, used to debond temporary bonding wafers formed by bonding a device wafer and a carrier wafer by an adhesive, includes: obtaining the height position of the adhesive through a thickness measurement apparatus; moving a cutting apparatus to a position between the device wafer and the carrier wafer based on the height position of the adhesive, then removing the adhesive at the edge of the temporary bonding wafers by the cutting apparatus; removing the carrier wafer from the temporary bonding wafers; cleaning the adhesive left on the surface of the device wafer.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: June 14, 2016
    Assignee: National Center for Advanced Packaging Co., Ltd.
    Inventors: Daquan Yu, Feng Jiang
  • Patent number: 9041147
    Abstract: According to a semiconductor substrate (40), a space (A) between a plurality of Si thin film (16), which are provide apart from one another on the insulating substrate (30), is (I) larger than a difference between elongation of part of the insulating substrate which part corresponds to the space (A) and elongation of each of Si wafers (10) when a change is made from room temperature to 600° C. and (II) smaller than 5 mm. This causes an increase in a region of each of a plurality of semiconductor thin films which region has a uniform thickness, and therefore prevents transferred semiconductor layers and the insulating substrate from being fractured or chipped.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: May 26, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Mitani
  • Patent number: 9034727
    Abstract: The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: May 19, 2015
    Assignee: SOITEC
    Inventors: Mariam Sadaka, Radu Ionut
  • Patent number: 9018730
    Abstract: A galvanic-isolated coupling of circuit portions is accomplished on the basis of a stacked chip configuration. The semiconductor chips thus can be fabricated on the basis of any appropriate process technology, thereby incorporating one or more coupling elements, such as primary or secondary coils of a micro transformer, wherein the final characteristics of the micro transformer are adjusted during the wafer bond process.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Crocifisso Marco Antonio Renna, Antonino Scuderi, Carlo Magro, Nunzio Spina, Egidio Ragonese, Barbaro Marano, Giuseppe Palmisano
  • Patent number: 8993370
    Abstract: In one embodiment, a method includes depositing a photoactive layer onto a first substrate, depositing a contact layer onto the photoactive layer, attaching a second substrate onto the contact layer, and removing the first substrate from the photoactive layer, contact layer, and second substrate.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: March 31, 2015
    Assignee: Zetta Research and Development LLC—AQT Series
    Inventors: Mariana Rodica Munteanu, Amith Kumar Murali, Kirk Hayes, Brian Josef Bartholomeusz
  • Patent number: 8980671
    Abstract: A manufacturing method of a semiconductor device according to embodiments includes forming a photodiode layer, which is an active region including a photodiode, on a main surface of a first substrate, forming a wiring layer, which includes a wire and a dielectric layer covering the wire, on the photodiode layer, and forming a dielectric film on the wiring layer. The manufacturing method of the semiconductor device according to the embodiments further includes bonding a second substrate to the dielectric film of the first substrate so that a crystal orientation of the photodiode layer matches a crystal orientation of the second substrate.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Hongo, Kazumasa Tanida, Akihiro Hori, Kenji Takahashi, Hideo Numata
  • Patent number: 8963293
    Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph
  • Patent number: 8956904
    Abstract: A method of forming a MEMS device provides first and second wafers, where at least one of the first and second wafers has a two-dimensional array of MEMS devices. The method deposits a layer of first germanium onto the first wafer, and a layer of aluminum-germanium alloy onto the second wafer. To deposit the alloy, the method deposits a layer of aluminum onto the second wafer and then a layer of second germanium to the second wafer. Specifically, the layer of second germanium is deposited on the layer of aluminum. Next, the method brings the first wafer into contact with the second wafer so that the first germanium in the aluminum-germanium alloy contacts the second germanium. The wafers then are heated when the first and second germanium are in contact, and cooled to form a plurality of conductive hermetic seal rings about the plurality of the MEMS devices.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: February 17, 2015
    Assignee: Analog Devices, Inc.
    Inventors: John R. Martin, Timothy J. Frey, Christine H. Tsau, Michael W. Judy
  • Patent number: 8956891
    Abstract: A highly reliable light-emitting device and a manufacturing method thereof are provided. A light-emitting element and a terminal electrode are formed over an element formation substrate; a first substrate having an opening is formed over the light-emitting element and the terminal electrode with a bonding layer provided therebetween; an embedded layer is formed in the opening; a transfer substrate is formed over the first substrate and the embedded layer; the element formation substrate is separated; a second substrate is formed under the light-emitting element and the terminal electrode; and the transfer substrate and the embedded layer are removed. In addition, an anisotropic conductive connection layer is formed in the opening, and an electrode is formed over the anisotropic conductive connection layer. The terminal electrode and the electrode are electrically connected to each other through the anisotropic conductive connection layer.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akihiro Chida
  • Patent number: 8951887
    Abstract: The invention relates to a process for fabricating a semiconductor that comprises providing a handle substrate comprising a seed substrate and a weakened sacrificial layer covering the seed substrate; joining the handle substrate with a carrier substrate; optionally treating the carrier substrate; detaching the handle substrate at the sacrificial layer to form the semiconductor structure; and removing any residue of the sacrificial layer present on the seed substrate.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: February 10, 2015
    Assignee: Soitec
    Inventors: Fabrice Letertre, Didier Landru
  • Patent number: 8941152
    Abstract: A method of forming a semiconductor device comprises forming a base wafer comprising a first chip package portion, a second chip package portion, and a third chip package portion. The method also comprises forming a capping wafer comprising a plurality of isolation trenches, each of the plurality of isolation trenches being configured to substantially align with one of the first chip package portion, the second chip package portion or the third chip package portion. The method further comprises eutectic bonding the capping wafer and the base wafer to form a wafer package. The method additionally comprises dicing the wafer package into a first chip package, a second chip package, and a third chip package. The method also comprises placing the first chip package, the second chip package, and the third chip package onto a substrate.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-wen Cheng, Jung-Huei Peng, Shang-Ying Tsai, Hung-Chia Tsai, Yi-Chuan Teng
  • Patent number: 8927320
    Abstract: A method of bonding by molecular bonding between at least one lower wafer and an upper wafer comprises positioning the upper wafer on the lower wafer. In accordance with the invention, a contact force is applied to a peripheral side of at least one of the two wafers in order to initiate a bonding wave between the two wafers.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: January 6, 2015
    Assignee: Soitec
    Inventors: Chrystelle Lagahe Blanchard, Marcel Broekaart, Arnaud Castex
  • Patent number: 8906775
    Abstract: A method for fabricating a semiconductor device includes forming a first semiconductor wafer, in which a circuit part and a first bonding layer are stacked, on a first semiconductor substrate, forming a second semiconductor wafer, which includes structures and an insulating layer for gap-filling between the structures, on a second semiconductor substrate, the structures including a pillar and bit lines stacked therein, bonding the first semiconductor wafer with the second semiconductor wafer so that the first bonding layer faces the insulating layer, and separating the second semiconductor substrate from the bonded second semiconductor wafer.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventors: Heung-Jae Cho, Eui-Seong Hwang, Tae-Yoon Kim, Kyu-Hyung Yoon
  • Patent number: 8853054
    Abstract: A method is provided for preparing multilayer semiconductor structures, such as silicon-on-insulator wafers, having reduced warp and bow. Reduced warp multilayer semiconductor structures are prepared by forming a dielectric structure on the exterior surfaces of a bonded pair of a semiconductor device substrate and a semiconductor handle substrate having an intervening dielectric layer therein. Forming a dielectric layer on the exterior surfaces of the bonded pair offsets stresses that may occur within the bulk of the semiconductor handle substrate due to thermal mismatch between the semiconductor material and the intervening dielectric layer as the structure cools from process temperatures to room temperatures.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: October 7, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Guoqiang Zhang, Jeffrey L. Libbert
  • Patent number: 8836033
    Abstract: Embodiments of a method and apparatus for removing metallic nanotubes without transferring CNTs from one substrate to another substrate provide two methods of transferring a thin layer of crystalline ST-cut quartz wafer to the surface of a carrier silicon wafer for subsequent CNT growth, without resorting to CNT transfer. In other words, embodiments of a method and apparatus allow CNTs to be grown on the same substrate that metallic nanotube removal is performed, therefore eliminating the costly and messy step of transferring CNTs from one substrate to another. This is achieved through a residual thin layer of crystalline ST-cut quartz layer on a silicon wafer. The ST-cut quartz wafer promotes aligned growth of CNTs, while the underlying silicon wafer allows backgate burnout.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: September 16, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Silai Krishnaswamy, Joseph Payne, Jeffrey Hartman
  • Patent number: 8829507
    Abstract: The disclosure relates generally to sealed electronic devices. More particularly, the invention relates to electronic devices employing organic devices having a seal. Packages having organic electronic devices are presented, and a number of sealing mechanisms are provided for hermetically sealing the package to protect the organic electronic device from environmental elements.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: September 9, 2014
    Assignee: General Electric Company
    Inventors: Jie Jerry Liu, Kevin Henry Janora, Xiaolei Shi, Rian Zhao, Jeffrey Michael Youmans, Srinivas Pravad Sista
  • Patent number: 8828845
    Abstract: Provided is a method of fabricating an oxide thin film device using laser lift-off and an oxide thin film device fabricated by the same. The method includes: forming an oxide thin film on a growth substrate; bonding a temporary substrate on the oxide thin film; irradiating laser onto the growth substrate to separate the oxide thin film on which the temporary substrate has been bonded from the growth substrate; bonding a device substrate on the oxide thin film on which the temporary substrate has been bonded; and forming an upper electrode film on the oxide thin film. Therefore, it is possible to overcome problems caused by a defective layer by transferring an oxide thin film transferred on a polymer-based temporary substrate onto a device substrate, without using an interface on which a defective layer formed due to oxygen diffusion upon laser lift-off is formed.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: September 9, 2014
    Assignee: Korea Institute of Science and Technology
    Inventors: Chong Yun Kang, Seok Jin Yoon, Young Ho Do, Ji Won Choi, Seung Hyub Baek, Hyun Cheol Song, Jin Sang Kim
  • Patent number: 8822307
    Abstract: According to one embodiment, a semiconductor manufacturing apparatus is provided. The semiconductor manufacturing apparatus includes a stage, a substrate supporter, first and second pushers, and a controller. The stage is configured to support outer periphery portions of the first semiconductor substrate from below. The substrate supporter is configured to hold the back of the second semiconductor substrate. The first and second pushers are configured to bring the first and second semiconductor substrates in contact. The controller is configured to form the bonding initiation point between the first and second semiconductor substrates.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yamaguchi, Kazumasa Tanida, Hideo Numata, Satoshi Hongo, Kenji Takahashi
  • Patent number: 8796056
    Abstract: A method for fabricating a display panel includes the following steps. A surface of a first substrate is adhered to a first supporting substrate with a first adhesive layer. First devices are formed on the other surface of the first substrate. The other surface of the first substrate is adhered to a second supporting substrate with a second adhesive layer. The first adhesive layer and supporting substrate are separated from the first substrate. Second devices are formed on the surface of the first substrate. A second substrate is adhered to a third supporting substrate with a third adhesive layer. The first substrate and the second substrate are assembled, and a display medium layer is interposed between the first substrate and the second substrate. The second adhesive layer and supporting substrate are separated from the first substrate, and the third adhesive layer and supporting substrate are separated from the second substrate.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 5, 2014
    Assignee: AU Optronics Corp.
    Inventor: Chi-Ho Chang
  • Patent number: 8796850
    Abstract: By forming a metal layer 14 on at least one of a connecting electrode 12 of a first substrate 10 and a connecting electrode 17 of a second substrate 15, placing the first substrate 10 and the second substrate 15 together in order that the connecting electrode 12 and the connecting electrode 17 face opposite to each other via the metal layer 14, increasing temperature up to anodic bonding temperature, and applying DC voltage between the first substrate 10 and the second substrate 15 while maintaining that temperature, the first substrate 10 and the second substrate 15 are anodically bonded, and at the same time by melting the metal layer 14, the connecting electrode 12 and the connecting electrode 17 are electrically connected. The method achieves anodic bonding of substrates with high yield and at the same time establishes wiring connection, effective for packaging.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: August 5, 2014
    Assignee: Tohoku University
    Inventors: Shuji Tanaka, Masayoshi Esashi, Sakae Matsuzaki, Mamoru Mori
  • Patent number: 8785292
    Abstract: An anodic bonding apparatus includes a first electrode and a second electrode. The first electrode has a first surface, and the second electrode has a second surface facing the first surface. The first surface includes a first central area; a first substrate placing area for placing a laminated substrate; and a first peripheral area surrounding the first substrate placing area. The second surface includes a second central area corresponding to the first central area; a second substrate placing area surrounding the second central area; and a second peripheral area corresponding to the first peripheral area and surrounding the second substrate placing area. Further, the second electrode includes a curved portion curved toward the first electrode, so that a distance between the first central area and the second central area becomes smaller than a distance between the first peripheral area and the second peripheral area.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: July 22, 2014
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Shinichi Sueyoshi
  • Patent number: 8772128
    Abstract: A single crystal semiconductor substrate is irradiated with ions that are generated by exciting a hydrogen gas and are accelerated with an ion doping apparatus, thereby forming a damaged region that contains a large amount of hydrogen. After the single crystal semiconductor substrate and a supporting substrate are bonded, the single crystal semiconductor substrate is heated to be separated along the damaged region. While a single crystal semiconductor layer separated from the single crystal semiconductor substrate is heated, this single crystal semiconductor layer is irradiated with a laser beam. The single crystal semiconductor layer undergoes re-single-crystallization by being melted through laser beam irradiation, thereby recovering its crystallinity and planarizing the surface of the single crystal semiconductor layer.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junpei Momo, Fumito Isaka, Eiji Higa, Masaki Koyama, Akihisa Shimomura
  • Patent number: 8765576
    Abstract: A method of manufacturing a laminated substrate is provided. The method includes: forming an oxide film on at least a surface of a first substrate having a hardness of equal to or more than 150 GPa in Young's modulus, and then smoothing the oxide film; implanting hydrogen ions or rare gas ions, or mixed gas ions thereof from a surface of a second substrate to form an ion-implanted layer inside the substrate, laminating the first substrate and the second substrate through at least the oxide film, and then detaching the second substrate in the ion-implanted layer to form a laminated substrate; heat-treating the laminated substrate and diffusing outwardly the oxide film.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: July 1, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Atsuo Ito, Yoshihiro Kubota, Koichi Tanaka, Makoto Kawai, Yuuji Tobisaka
  • Patent number: 8753910
    Abstract: A method of manufacturing a vertical structure light emitting diode device, the method including: sequentially forming a first conductivity type III-V group compound semiconductor layer, an active layer, and a second conductivity type III-V group compound semiconductor layer on a substrate for growth; bonding a conductive substrate to the second conductivity type III-V group compound semiconductor layer; removing the substrate for growth from the first conductivity type III-V group compound semiconductor layer; and forming an electrode on an exposed portion of the first conductive III-V group compound semiconductor layer due to the removing the substrate for growth, wherein the bonding a conductive substrate comprises partially heating a metal bonding layer by applying microwaves to a bonding interface while bringing the metal bonding layer into contact with the bonding interface.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: June 17, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myong Soo Cho, Ki Yeol Park, Sang Yeob Song, Si Hyuk Lee, Pun Jae Choi
  • Patent number: 8745860
    Abstract: A method for manufacturing a printed wiring board includes forming on a support board a first resin insulation layer, forming a second resin insulation layer on the first resin insulation layer, forming in the second resin insulation layer an opening portion in which an electronic component having an electrode is mounted, accommodating the electronic component in the opening portion of the second resin insulation layer such that the electrode of the electronic component faces an opposite side of the first resin insulation layer, forming on the first surface of the second resin insulation layer and the electronic component an interlayer resin insulation layer, and forming in the interlayer resin insulation layer a via conductor reaching to the electrode of the electronic component.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: June 10, 2014
    Assignee: Ibiden Co., Ltd.
    Inventor: Tsuyoshi Inui
  • Patent number: 8748289
    Abstract: A method for manufacturing a semiconductor device makes it possible to efficiently polish with a polishing tape a peripheral portion of a silicon substrate under polishing conditions particularly suited for a deposited film and for silicon underlying the deposited film. The method includes pressing a first polishing tape against a peripheral portion of a device substrate having a deposited film on a silicon surface while rotating the device substrate at a first rotational speed, thereby removing the deposited film lying in the peripheral portion of the device substrate and exposing the underlying silicon. A second polishing tape is pressed against the exposed silicon lying in the peripheral portion of the device substrate while rotating the device substrate at a second rotational speed, thereby polishing the silicon to a predetermined depth.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: June 10, 2014
    Assignee: Ebara Corporation
    Inventors: Masayuki Nakanishi, Tetsuji Togawa, Kenya Ito, Masaya Seki, Kenji Iwade, Takeo Kubota
  • Patent number: 8748294
    Abstract: There is provided an SOS substrate with reduced stress. The SOS substrate is a silicon-on-sapphire (SOS) substrate comprising a sapphire substrate and a monocrystalline silicon film on or above the sapphire substrate. The stress of the silicon film of the SOS substrate as measured by a Raman shift method is 2.5×108 Pa or less across an entire in-plane area of the SOS substrate.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: June 10, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Shoji Akiyama
  • Patent number: 8741739
    Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph
  • Patent number: 8735205
    Abstract: A method of fabricating a microelectronic unit can include providing a semiconductor element having front and rear surfaces, a plurality of conductive pads each having a top surface exposed at the front surface and a bottom surface remote from the top surface, and a first opening extending from the rear surface towards the front surface. The method can also include forming at least one second opening extending from the first opening towards the bottom surface of a respective one of the pads. The method can also include forming a conductive via, a conductive interconnect, and a contact, the conductive via in registration with and in contact with the conductive pad and extending within the second opening, the contact exposed at an exterior of the microelectronic unit, the conductive interconnect electrically connecting the conductive via with the contact and extending away from the via at least partly within the first opening.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: May 27, 2014
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Kenneth Allen Honer, David B. Tuckerman, Vage Oganesian
  • Patent number: 8735263
    Abstract: An SOI substrate is manufactured by the following steps: a semiconductor substrate is irradiated with an ion beam in which the proportion of H2O+ to hydrogen ions (H3+) is lower than or equal to 3%, preferably lower than or equal to 0.3%, whereby an embrittled region is formed in the semiconductor substrate; a surface of the semiconductor substrate and a surface of a base substrate are disposed so as to be in contact with each other, whereby the semiconductor substrate and the base substrate are bonded; and a semiconductor layer is separated along the embrittled region from the semiconductor substrate which is bonded to the base substrate by heating the semiconductor substrate and the base substrate, so that the semiconductor layer is formed over the base substrate.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kazuya Hanaoka
  • Patent number: 8735261
    Abstract: A method and a system are described herein for applying etchant to edges of a plurality of wafers. The system includes a sump configured for holding etchant, a roller having an outer surface in fluid communication with the sump and configured to have etchant thereon, a wafer cassette configured to retain wafers positioned therein so that edges of the wafers are in contact with the roller. The cassette permits axial rotation of the wafers about an axis. A method of applying etchant to the edge of the wafer includes placing the wafer edge in contact with the roller and rotating the roller about a longitudinal axis of the roller. At least a portion of the roller contact an etchant contained in a sump during rotation so that etchant is applied to the wafer edge.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: May 27, 2014
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Robert W. Standley
  • Patent number: 8716108
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a circuit substrate having an active side opposite to an inactive portion; attaching a nonconductive cover to the active side; forming a separation-gap partially cutting into the nonconductive cover and the circuit substrate to a kerf depth; attaching a back-grinding tape to the nonconductive cover; removing a portion of the inactive portion; and exposing the nonconductive cover by removing the back-grinding tape.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: May 6, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Hun Teak Lee, DaeWook Yang, Yeongbeom Ko
  • Patent number: 8716105
    Abstract: Methods of bonding together semiconductor structures include annealing metal of a feature on a semiconductor structure prior to directly bonding the feature to a metal feature of another semiconductor structure to form a bonded metal structure, and annealing the bonded metal structure after the bonding process. The thermal budget of the first annealing process may be at least as high as a thermal budget of a later annealing process. Additional methods involve forming a void in a metal feature, and annealing the metal feature to expand the metal of the feature into the void. Bonded semiconductor structures and intermediate structures are formed using such methods.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: May 6, 2014
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu, Didier Landru
  • Publication number: 20140117510
    Abstract: A system and method for bonding semiconductor devices is provided. An embodiment comprises halting the flow of a eutectic bonding material by providing additional material of one of the reactants in a grid pattern, such that, as the eutectic material flows into the additional material, the additional material will change the composition of the flowing eutectic material and solidify the material, thereby stopping the flow. Other embodiments provide for additional layouts to put the additional material into the path of the flowing eutectic material.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuei-Sung Chang, Nien-Tsung Tsai, Ting-Hau Wu, Yi Heng Tsai
  • Patent number: 8709912
    Abstract: Even when a substrate for treatment is joined with a supporting substrate having an outer shape larger than that of the substrate for treatment, with a photothermal conversion layer and an adhesive layer interposed, and the surface of the substrate for treatment on the side opposite this joined surface is treated, the occurrence of a defective external appearance on the treatment surface of the substrate for treatment is prevented. An adhesive layer 4 is formed on one surface of a substrate for treatment 3, a photothermal conversion layer 2 is formed on one surface of a supporting substrate 1 having a surface with an outer shape larger than that of the surface of the substrate for treatment, and the substrate for treatment 3 is bonded onto the surface of the photothermal conversion layer 2 with the adhesive layer 4 interposed, to obtain a layered member.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: April 29, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yuichi Urano, Kenichi Kazama
  • Patent number: 8709911
    Abstract: The present invention is a method for producing an SOI substrate including the steps of: preparing a bond wafer and a base wafer which are composed of single crystal silicon wafers; forming an oxide film on a surface of at least one of the bond wafer and the base wafer so that a thickness of a buried oxide film after bonding becomes 3 ?m or more; bonding the bond wafer and the base wafer via the oxide film; performing a low-temperature heat treatment at a temperature of 400° C. or more and 1000° C. or less to the bonded substrate; thinning the bond wafer to be an SOI layer; and increasing bonding strength by performing a high-temperature heat treatment at a temperature exceeding 1000° C. Thus, a method for producing an SOI substrate by which generation of slip dislocations is suppressed and an SOI substrate having a high-quality SOI layer can be obtained, for producing a SOI layer in which the thickness of a buried oxide film is thick as 3 ?m or more by a bonding method, etc. are provided.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: April 29, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Masao Matsumine
  • Publication number: 20140091439
    Abstract: One embodiment for forming a shaped substrate for an electronic device can form a shaped perimeter to define the substrate shape on the surface of a substrate. The shaped perimeter can extend at least part way into the substrate. A subsequent thinning process can remove substrate material and expose the shaped perimeter effectively forming shaped dies from the substrate.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: APPLE INC.
    Inventors: Shawn X. ARNOLD, Matthew E. LAST