By Selective Deposition Of Conductive Material In Vias, E.g., Selective Chemical Vapor Deposition On Semiconductor Material, Plating (epo) Patents (Class 257/E21.586)
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Publication number: 20130320480Abstract: A semiconductor device comprises an integrated circuit (IC) die having a top side and a back side. The circuit substrate includes a heat source circuit, a heat sensitive circuit, a package substrate coupled to the top side of the circuit substrate, and a plurality of thermally conductive through-silicon vias (TSVs) formed from the back side of the circuit substrate to near but not through the top side of the circuit substrate.Type: ApplicationFiled: May 31, 2012Publication date: December 5, 2013Inventors: Michael B. Mcshane, Kevin J. Hess, Perry H. Pelley, Tab A. Stephens
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Patent number: 8598031Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.Type: GrantFiled: September 28, 2009Date of Patent: December 3, 2013Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Fan Zhang, Xiaomei Bu, Jane Hui, Tae Jong Lee, Liang Choo Hsia
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Patent number: 8586431Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, forming doped portions of the substrate layer in the first planar area, removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer, and etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure.Type: GrantFiled: April 26, 2013Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Emily R. Kinser, Richard Wise, Hakeem Yusuff
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Publication number: 20130299993Abstract: The present invention provides a method for fabricating an interconnection of a semiconductor device, which includes the following processes. First, an isolation layer is formed on a substrate. Then, at least a first trenches extending along a first direction is formed in the isolation layer. The first trench is then filled up with a first conductive material followed by forming a patterned mask layer on the substrate, wherein the patterned mask exposes parts of the isolation layer and part of the first conductive material. Finally, at least a second trench extending along a second direction is formed in the isolation layer, wherein the at least one second trenches intersects and overlaps portions of the at least one first trenches.Type: ApplicationFiled: May 11, 2012Publication date: November 14, 2013Inventor: Hsin-Yu Chen
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Patent number: 8580684Abstract: In sophisticated semiconductor devices, contact elements in the contact level may be formed by patterning the contact openings and filling the contact openings with the metal of the first metallization layer in a common deposition sequence. To this end, in some illustrative embodiments, a sacrificial fill material may be provided in contact openings prior to depositing the dielectric material of the first metallization layer.Type: GrantFiled: November 4, 2010Date of Patent: November 12, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Robert Seidel, Kai Frohberg, Carsten Peters
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Patent number: 8580687Abstract: One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a workpiece; forming a dielectric barrier layer over the workpiece; forming an opening through the dielectric barrier layer; forming a seed layer over the dielectric barrier layer and within the dielectric barrier layer opening; and electroplating a first fill layer on the seed layer.Type: GrantFiled: September 30, 2010Date of Patent: November 12, 2013Assignee: Infineon Technologies AGInventors: Gerald Dallmann, Dirk Meinhold, Alfred Vater
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Publication number: 20130292841Abstract: The present disclosure provides an interconnect structure for a semiconductor device. The interconnect structure includes a first metal layer that contains a first metal line. The interconnect structure includes a dielectric layer located over the first metal layer. The dielectric layer contains a first sub-via electrically coupled to the first metal line and a second sub-via electrically coupled to the first sub-via. The second sub-via is different from the first sub-via. The interconnect structure includes a second metal layer located over the dielectric layer. The second metal layer contains a second metal line electrically coupled to the second sub-via. No other metal layer is located between the first metal layer and the second metal layer.Type: ApplicationFiled: May 4, 2012Publication date: November 7, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Ming Lai, Wen-Chun Huang, Ru-Gun Liu, Pi-Tsung Chen
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Patent number: 8575028Abstract: Methods, apparatus, and systems for depositing copper and other metals are provided. In some implementations, a wafer substrate is provided to an apparatus. The wafer substrate has a surface with field regions and a feature. A copper layer is plated onto the surface of the wafer substrate. The copper layer is annealed to redistribute copper from regions of the wafer substrate to the feature. Implementations of the disclosed methods, apparatus, and systems allow for void-free bottom-up fill of features in a wafer substrate.Type: GrantFiled: May 16, 2011Date of Patent: November 5, 2013Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Huanfeng Zhu
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Publication number: 20130288474Abstract: Methods for fabricating dual damascene interconnect structures are provided herein. In some embodiments, a method for fabricating a dual damascene interconnect structure may include etching a via into a substrate through a first photoresist layer; patterning a second photoresist layer atop the substrate to define a trench pattern, wherein the via is aligned within the trench pattern, and wherein a portion of undeveloped photoresist remains in the via after patterning; and etching the trench into the substrate to form a dual damascene pattern in the substrate.Type: ApplicationFiled: April 27, 2012Publication date: October 31, 2013Applicant: APPLIED MATERIALS, INC.Inventors: ROHIT MISHRA, JAYAGATAN R. VIJAYEN, KHALID M. SIRAJUDDIN, BRAD EATON, MADHAVA RAO YALAMANCHILI
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Patent number: 8569154Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, etching to the exposed first planar area to form a cavity having a first depth in the structure, removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer, forming a doped portion in the sacrificial substrate layer, and etching the cavity to increase the depth of the cavity to expose a first conductor in the structure and to increase the planar area and depth of a portion of the cavity to expose a second conductor in the structure.Type: GrantFiled: March 16, 2012Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Emily R. Kinser, Richard Wise, Hakeem Yusuff
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Publication number: 20130277810Abstract: Semiconductor devices are formed with through silicon vias extending into the semiconductor substrate from a backside surface for improved heat dissipation. Embodiments include forming a cavity in a backside surface of a substrate, the substrate including a gate stack on a frontside surface, and filling the cavity with a thermally conductive material.Type: ApplicationFiled: April 23, 2012Publication date: October 24, 2013Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Juan Boon Tan, Yeow Kheng Lim, Shao Ning Yuan, Soh Yun Siah
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Publication number: 20130277842Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.Type: ApplicationFiled: April 20, 2012Publication date: October 24, 2013Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., RENESAS ELECTRONICS CORPORATION, STMICROELECTRONICS, INC.Inventors: Frieder Hainrich Baumann, Chao-Kun Hu, Andrew H. Simon, Tibor Bolom, Koichi Motoyama, Chengyu Charles Niu
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Publication number: 20130270711Abstract: An apparatus and method are provided for integrating TSVs into devices prior to device contacts processing. The apparatus includes a semiconducting layer; one or more CMOS devices mounted on a top surface of the semiconducting layer; one or more TSVs integrated into the semiconducting layer of the device wafer; at least one metal layer applied over the TSVs; and one or more bond pads mounted onto a top layer of the at least one metal layer, wherein the at least one metal layer is arranged to enable placement of the one or more bond pads at a specified location for bonding to a second device wafer. The method includes obtaining a wafer of semiconducting material, performing front end of line processing on the wafer; providing one or more TSVs in the wafer; performing middle of line processing on the wafer; and performing back end of line processing on the wafer.Type: ApplicationFiled: April 12, 2012Publication date: October 17, 2013Applicant: The Research Foundation Of State University Of New YorkInventors: Jeremiah HEBDING, Megha RAO, Colin McDONOUGH, Matthew SMALLEY, Douglas Duane COOLBAUGH, Joseph PICCIRILLO, JR., Stephen G. BENNETT, Michael LIEHR, Daniel PASCUAL
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Publication number: 20130270713Abstract: A dual damascene structure having a through silicon via and a manufacturing method thereof are provided. The method includes forming a first, a second, and a third dielectric layers a on a substrate having a conductive structure. A trench is formed in the third dielectric layer. A hard mask layer is formed on the third dielectric layer and a surface of the trench. A first opening having a tapered sidewall is formed in the hard mask layer. A second opening is formed in the second and the third dielectric layers. The substrate exposed by the second opening and the first opening is etched to form a through hole so as to form a dual damascene opening. A liner layer is formed on a surface of the dual damascene opening and the conductive structure is exposed. The dual damascene opening is filled with a conductive material.Type: ApplicationFiled: July 11, 2012Publication date: October 17, 2013Applicant: Industrial Technology Research InstituteInventors: Sue-Chen Liao, Tzu-Kun Ku, Cha-Hsin Lin, Pei-Jer Tzeng, Chi-Hon Ho
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Publication number: 20130234336Abstract: Processes for forming integrated circuits and integrated circuits formed thereby are provided in which a first dielectric layer including a first dielectric material is formed on an underlying substrate. A first etch mask having at least two patterned recesses is patterned over the first dielectric layer. At least one first-level via is etched in the first dielectric layer through one patterned recess in the first etch mask with a first etchant, and the first-level via is filled with electrically-conductive material. A second dielectric layer including a second dielectric material is formed over the first dielectric layer. A second etch mask having patterned recesses corresponding to the patterned recesses of the first etch mask is patterned over the second dielectric layer. Second-level vias are etched in the second dielectric layer through the patterned recesses in the second etch mask with a second etchant and exposed to the first etchant.Type: ApplicationFiled: March 12, 2012Publication date: September 12, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Ralf Richter, Hans-Jürgen Thees
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Patent number: 8531033Abstract: A contact plug structure formed on a contact hole of an insulating layer of a semiconductor device includes a metal silicide layer formed on a bottom part of the contact hole of the insulating layer, a manganese oxide layer formed on the metal silicide layer in the contact hole, and a buried copper formed on the manganese oxide layer which substantially fills the contact hole.Type: GrantFiled: September 7, 2010Date of Patent: September 10, 2013Assignee: Advanced Interconnect Materials, LLCInventors: Junichi Koike, Akihiro Shibatomi, Kouji Neishi
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Publication number: 20130224948Abstract: A method for fabricating an integrated circuit includes providing a semiconductor wafer comprising a hole etched therein, depositing a first layer comprising tungsten onto the semiconductor wafer and into the hole therein, thereby filling the hole with the first layer, and etching the first layer from the semiconductor wafer, wherein etching the first layer results in the formation of a divot above the first layer within the hole. The method may further include depositing a second layer comprising tungsten onto the semiconductor wafer and into the divot formed above the first layer within the hole and polishing the second layer from the semiconductor wafer, wherein polishing the second layer does not remove the second layer deposited into the divot.Type: ApplicationFiled: February 28, 2012Publication date: August 29, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Ralf Richter, Jana Rössler
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Publication number: 20130221535Abstract: A diffusion barrier layer, a metal interconnect arrangement and a method of manufacturing the same are disclosed. In one embodiment, the metal interconnect arrangement may comprise a conductive plug/interconnect wire for electrical connection, and a diffusion barrier layer provided on at least a portion of a surface of the conductive plug/interconnect wire. The diffusion barrier layer may comprise insulating amorphous carbon.Type: ApplicationFiled: February 29, 2012Publication date: August 29, 2013Inventors: Xiaolong Ma, Huaxiang Yin, Lichuan Zhao
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Publication number: 20130214411Abstract: Provided is a method of manufacturing a metal interconnect of a semiconductor device including: forming a interconnect hole by patterning an interlayer insulating film formed on a substrate; performing a nitriding treatment on a surface of the interlayer insulating film by injecting a gas including nitrogen into a deposition apparatus in which the substrate is disposed; forming a diffusion preventing film by injecting the gas including nitrogen and a metal source gas into the deposition apparatus together; filling the interconnect hole with a metal; and removing the metal formed on a part other than the interconnect hole by a chemical mechanical polishing (CMP) process. Accordingly, the mechanical strength of the interlayer insulating film is increased, thereby preventing scratches or defects that are generated during the chemical mechanical polishing process.Type: ApplicationFiled: October 24, 2012Publication date: August 22, 2013Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGYInventor: Korea Institute of Science and Technology
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Patent number: 8513124Abstract: Disclosed are methods of depositing a copper seed layer to be used for subsequent electroplating a bulk-layer of copper thereon. A copper seed layer may be deposited with different processes, including CVD, PVD, and electroplating. With electroplating methods for depositing a copper seed layer, disclosed are methods for depositing a copper alloy seed layer, methods for depositing a copper seed layer on the semi-noble metal layer with a non-corrosive electrolyte, methods of treating the semi-noble metal layer that the copper seed layer is deposited on, and methods for promoting a more uniform copper seed layer deposition across a semiconductor wafer.Type: GrantFiled: May 21, 2010Date of Patent: August 20, 2013Assignee: Novellus Systems, Inc.Inventors: Thomas A. Ponnuswamy, John H. Sukamto, Jonathan D. Reid, Steven T. Mayer
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Publication number: 20130207264Abstract: A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.Type: ApplicationFiled: February 9, 2012Publication date: August 15, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Publication number: 20130200441Abstract: An integrated circuit having a mis-alignment tolerant electrical contact is formed by providing a semiconductor containing substrate over which is a first FET gate laterally bounded by a first dielectric region, replacing an upper portion of the first FET gate with a second dielectric region, applying a mask having an opening extending partly over an adjacent source or drain contact region of the substrate and over a part of the second dielectric region above the first FET gate, forming an opening through the first dielectric region extending to the contact region and the part of the second dielectric region, and filling the opening with a conductor making electrical connection with the contact region but electrically insulated from the first FET gate by the second dielectric region. A further FET gate may also be provided having an electrical contact thereto formed separately from the source-drain contact.Type: ApplicationFiled: February 2, 2012Publication date: August 8, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: André P. Labonté, Richard S. Wise, Ying Li, Brett H. Engel
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Patent number: 8501620Abstract: Top-down methods of increasing reflectivity of tungsten films to form films having high reflectivity, low resistivity and low roughness are provided. The methods involve bulk deposition of tungsten followed by a removing a top portion of the deposited tungsten. In particular embodiments, removing a top portion of the deposited tungsten involve exposing it to a fluorine-containing plasma. The methods produce low resistivity tungsten bulk layers having lower roughness and higher reflectivity. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. Applications include forming tungsten bit lines.Type: GrantFiled: March 5, 2012Date of Patent: August 6, 2013Assignee: Novellus Systems, Inc.Inventors: Anand Chandrashekar, Raashina Humayun
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Publication number: 20130193575Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To improve the copper plating, a seed layer formed in the through-wafer vias can be modified to increase water affinity, rinsed to remove contaminants, and activated to facilitate copper deposition. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.Type: ApplicationFiled: January 27, 2012Publication date: August 1, 2013Applicant: SKYWORKS SOLUTIONS, INC.Inventor: Hong Shen
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Publication number: 20130189839Abstract: A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region.Type: ApplicationFiled: September 13, 2012Publication date: July 25, 2013Applicants: GLOBALFOUNDRIES Inc., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. GUILLORN, Christian LAVOIE, Ghavam G. SHAHIDI, Bin YANG, Zhen ZHANG
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Publication number: 20130187274Abstract: A method of forming a semiconductor device includes forming a first conductive layer over the substrate. A dielectric layer, having a first opening, is formed over the first conductive layer. A seed layer is deposited over the first dielectric layer and in the first opening. A layer is formed of conductive nanotubes from the seed layer over the first dielectric layer and over the first opening. A second dielectric is formed over the layer of conductive nanotubes. An opening is formed in the second dielectric layer over the first opening. Conductive material is deposited in the second opening.Type: ApplicationFiled: January 25, 2012Publication date: July 25, 2013Inventor: Douglas M. Reber
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Patent number: 8492252Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, forming doped portions of the substrate layer in the first planar area, removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer, and etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure.Type: GrantFiled: March 16, 2012Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Emily R. Kinser, Richard Wise, Hakeem Yusuff
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Patent number: 8492260Abstract: A semiconductor substrate can be patterned to define a trench and a feature. In an embodiment, the trench can be formed such that after filling the trench with a material, a bottom portion of the filled trench may be exposed during a substrate thinning operation. In another embodiment, the trench can be filled with a thermal oxide. The feature can have a shape that reduces the likelihood that a distance between the feature and a wall of the trench will be changed during subsequent processing. A structure can be at least partly formed within the trench, wherein the structure can have a relatively large area by taking advantage of the depth of the trench. The structure can be useful for making electronic components, such as passive components and through-substrate vias. The process sequence to define the trenches and form the structures can be tailored for many different process flows.Type: GrantFiled: August 30, 2010Date of Patent: July 23, 2013Assignee: Semionductor Components Industries, LLCInventors: John Michael Parsey, Jr., Gordon M. Grivna
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Publication number: 20130183825Abstract: A method for manufacturing a damascene structure includes providing a substrate having a dielectric layer formed thereon, forming at least a trench in the dielectric layer, forming at least a via hole and a dummy via hole in the dielectric layer, forming a first conductive layer filling up the trench, the via hole and the dummy via hole on the substrate, and performing a chemical mechanical polishing process to form a damascene structure and simultaneously to remove the dummy via hole.Type: ApplicationFiled: January 18, 2012Publication date: July 18, 2013Inventors: En-Chiuan Liou, Chih-Wei Yang, Chih-Sen Huang, Chan-Yuan Hu, Ssu-I Fu
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Patent number: 8486832Abstract: A trench is formed in an interlayer dielectric formed on a substrate, then a barrier seed film is formed to cover the interlayer dielectric and the inner walls of the trench, and copper is embedded in the trench by electrolytic plating using the barrier seed film as an electrode. The barrier seed film is a single-layer film made of an oxide or nitride of a refractory metal and contains a low-resistance metal other than copper.Type: GrantFiled: September 10, 2007Date of Patent: July 16, 2013Assignee: Panasonic CorporationInventors: Yasunori Morinaga, Hideo Nakagawa
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Patent number: 8486827Abstract: A device of filling metal in a through-via-hole formed in a semiconductor wafer and a method of filling metal in a through-via-hole using the same are disclosed. A device of filling metal in a through-via-hole formed in a semiconductor wafer includes a jig base comprising a jig configured to fix the wafer having the through-via-hole formed therein; a upper chamber 120 installed on the jig base; a lower chamber installed under the jig base; a heater installed in the upper chamber, the heater configured to apply heat to filling metal placed on the wafer to melt the filling metal; and a vacuum pump configured to generate pressure difference between the upper chamber and the lower chamber by the pressure of the lower chamber reduced by discharging air of the lower chamber 130 outside, only to fill the melted filling metal in the through-via-hole.Type: GrantFiled: December 30, 2009Date of Patent: July 16, 2013Assignee: Korea Institute of Industrial TechnologyInventors: Se Hoon Yoo, Chang Woo Lee, Jun Ki Kim, Jeong Han Kim, Cheol Hee Kim, Young Ki Ko, Yue Seon Shin
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Patent number: 8471236Abstract: A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.Type: GrantFiled: July 16, 2012Date of Patent: June 25, 2013Assignees: International Business Machines Corporation, Macronix International Co., Ltd.Inventors: Matthew J. Breitwisch, Eric A. Joseph, Chung H. Lam, Hsiang-Lan Lung, Alejandro G. Schrott
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Publication number: 20130154055Abstract: A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.Type: ApplicationFiled: September 14, 2012Publication date: June 20, 2013Applicant: SK HYNIX INC.Inventors: Sun Mi PARK, Sang Hyun OH, Sang Bum LEE
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Patent number: 8466052Abstract: A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method.Type: GrantFiled: February 11, 2010Date of Patent: June 18, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-min Baek, Hee-sook Park, Seong-hwee Cheong, Gil-heyun Choi, Byung-hak Lee, Tae-ho Cha, Jae-hwa Park, Su-kyoung Kim
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Publication number: 20130147051Abstract: A method is for forming a decoy via and a functional via. The method includes forming the functional via between a metal portion of a first interconnect layer and a portion of a second interconnect layer. The method further includes forming the decoy via in a protection region between the metal portion of the first interconnect layer and a metal portion of the third interconnect level.Type: ApplicationFiled: December 7, 2011Publication date: June 13, 2013Inventors: MEHUL D. SHROFF, Douglas M. Reber, Edward O. Travis
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Publication number: 20130149863Abstract: A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes.Type: ApplicationFiled: April 6, 2012Publication date: June 13, 2013Inventor: Jae-Seon YU
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Patent number: 8461046Abstract: A process for producing an upper metallization level and a via level connecting this upper metallization level to a lower metallization level includes: producing an insulating region on the lower metallization level; producing a hard mask on the insulating region (4, 5) defining the position of the via and metallic line of the upper metallization level; etching the insulating region through the hard mask so as to form a cavity; cleaning the cavity (which forms an undercut at the interface between the hard mask and the insulating region); and completely filling the cavity. The step of completely filling includes at least partially filling the cavity with copper and plugging the undercut. The undercut is plugged by sputtering a plugging material and forming an overlying doped copper layer.Type: GrantFiled: July 20, 2011Date of Patent: June 11, 2013Assignee: STMicroelectronics (Crolles 2) SASInventor: Patrick Vannier
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Publication number: 20130134600Abstract: The present invention relates to a semiconductor device and method for manufacturing the same. The semiconductor device includes a substrate, a dielectric layer, a metal layer, an interconnection metal and an insulation circular layer. The substrate has at least one through hole. The dielectric layer is disposed adjacent to the substrate. The metal layer is disposed adjacent to the dielectric layer. The interconnection metal is disposed in the at least one through hole. An insulation circular layer surrounds the interconnection metal, wherein the insulation layer has an upper surface and the upper surface contacts the dielectric layer. Whereby, the metal layer can be electrically connected to another surface of the substrate through the interconnection metal.Type: ApplicationFiled: November 28, 2011Publication date: May 30, 2013Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chih-Jing Hsu, Ying-Te Ou
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Patent number: 8450197Abstract: Contact elements in the contact level of a semiconductor device may be formed on the basis of a selective deposition technique, such as electroless plating, wherein an efficient planarization of the contact level is achieved without subjecting the contact elements to undue mechanical stress. In some illustrative embodiments, an overfilling of the contact openings may be reliably avoided and the planarization of the surface topography is accomplished on the basis of a non-critical polishing process. In other cases, electrochemical etch techniques are applied in combination with a conductive sacrificial current distribution layer in order to remove any excess material of the contact elements without inducing undue mechanical stress.Type: GrantFiled: December 8, 2010Date of Patent: May 28, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Axel Preusse, Norbert Schroeder, Uwe Stoeckgen
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Patent number: 8450210Abstract: Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for wetting, initiation, seed layer repair, fill, overburden, reclaim, and rinse.Type: GrantFiled: August 25, 2011Date of Patent: May 28, 2013Assignee: Novellus Systems, Inc.Inventors: Evan E. Patton, Theodore Cacouris, Eliot Broadbent, Steven T. Mayer
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Patent number: 8445380Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer.Type: GrantFiled: May 25, 2012Date of Patent: May 21, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
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Publication number: 20130119543Abstract: Stacked wafer connections are enhanced by forming a though silicon via including a first via portion formed in an upper portion of a via hole and a second via portion in a lower portion of the via hole. Embodiments include forming a via hole in a first surface of a substrate; partially filling the via hole with a dielectric material; filling the remainder of the via hole with a first conductive material; removing a portion of a second surface of the substrate to expose the dielectric material; removing the dielectric material from the via hole; and filling a the via hole with a second conductive material electrically conductively connected to the first conductive material.Type: ApplicationFiled: November 16, 2011Publication date: May 16, 2013Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Hong YU, Huang LIU, Alex SEE
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Publication number: 20130115771Abstract: One or more embodiments may include a method of making a semiconductor structure, comprising: forming a first opening partially through a semiconductor substrate; forming a first dielectric layer over a sidewall surface of the first opening; and forming a second opening partially through a semiconductor substrate, the second opening being below the first opening.Type: ApplicationFiled: November 3, 2011Publication date: May 9, 2013Inventor: Manfred Engelhardt
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Patent number: 8435894Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.Type: GrantFiled: January 17, 2012Date of Patent: May 7, 2013Assignee: Novellus Systems, Inc.Inventors: Anand Chandrashekar, Raashina Humayun, Michal Danek, Aaron R. Fellis, Sean Chang
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Publication number: 20130109175Abstract: The present disclosure relates to a method of fabricating semiconductor devices. In the method provided by the present invention, by filling with diblock copolymer a recess of an interlayer dielectric layer naturally formed between two gate lines and then performing a self-assembly process of the diblock copolymer, a small-sized contact hole precisely aligned with an doped area can be formed, and thus misalignment between the contact hole and the doped area can be eliminated or alleviated.Type: ApplicationFiled: December 15, 2011Publication date: May 2, 2013Applicant: Semiconductor Manufacturing International (Beijing) CorporationInventors: HAIYANG ZHANG, Dongjiang Wang
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Publication number: 20130105987Abstract: A laminate interconnect structure includes a core material and at least one additional layer adjacent the core material, a first electrically conductive via formed in the core material, and a second electrically conductive via formed in the core material, coaxial with the first electrically conductive via and separated from the first electrically conductive via by a non-conductive material.Type: ApplicationFiled: November 2, 2011Publication date: May 2, 2013Applicant: Avago Technologies Enterprise IP (Singapore) Pte. Ltd.Inventors: Adam Gallegos, Mark Hinton, Nurwati Suwendi Devnani, John Connor
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Publication number: 20130109176Abstract: According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.Type: ApplicationFiled: October 22, 2012Publication date: May 2, 2013Applicant: Newport Fab, LLC dba Jazz SemiconductorInventor: Newport Fab, LLC dba Jazz Semiconductor
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Publication number: 20130105968Abstract: Generally, the subject matter disclosed herein relates to interconnect structures used for making electrical connections between semiconductor chips in a stacked or 3D chip configuration, and methods for forming the same. One illustrative method disclosed herein includes forming a conductive via element in a semiconductor substrate, wherein the conductive via element is formed from a front side of the semiconductor substrate so as to initially extend a partial distance through the semiconductor substrate. The illustrative method also includes forming a via opening in a back side of the semiconductor substrate to expose a surface of the conductive via element, and filling the via opening with a layer of conductive contact material.Type: ApplicationFiled: November 2, 2011Publication date: May 2, 2013Inventors: Yue Kang Lu, Shaoning Yuan, Yeow Kheng Lim, Juan Boon Tan
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Publication number: 20130099383Abstract: An electrical device includes a semiconductor chip. The semiconductor chip includes a routing line. An insulating layer is arranged over the semiconductor chip. A solder deposit is arranged over the insulating layer. A via extends through an opening of the insulating layer to electrically connect the routing line to the solder deposit. A front edge line portion of the via facing the routing line is substantially straight, has a concave curvature or has a convex curvature of a diameter greater than a maximum lateral dimension of the via.Type: ApplicationFiled: October 21, 2011Publication date: April 25, 2013Applicant: Infineon Technologies AGInventors: Georg Meyer-Berg, Christian Birzer
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Publication number: 20130099349Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate, a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate, a conductive layer on the opening, the conductive layer being connected to the LSI, and a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening.Type: ApplicationFiled: August 24, 2012Publication date: April 25, 2013Inventor: Akiko Nomachi