Abstract: A semiconductor device and a method for manufacturing the same are disclosed. When forming a profile of the lower electrode, a second lower electrode hole (i.e., a bunker region) located at the lowermost part of the lower electrode is buried with an Ultra Low Temperature Oxide (ULTO) material without damaging the lower electrode material. As a result, when a dielectric film is deposited in a subsequent process, the above-mentioned semiconductor device prevents the occurrence of a capacitor leakage current caused by defective gapfilling of the dielectric film located at the lowermost part of the lower electrode.

Abstract: A method for manufacturing an interposer equipped with a plurality of through-hole electrodes comprises a laser light converging step of converging a laser light at a sheet-like object to be processed made of silicon so as to form a modified region in the object; an etching step of anisotropically etching the object after the laser light converging step so as to advance etching selectively along the modified region and form a plurality of through holes in the object, each through hole being tilted with respect to a thickness direction of the object and having a rectangular cross section; an insulating film forming step of forming an insulating film on an inner wall of each through hole after the etching step; and a through-hole electrode forming step of inserting a conductor into the through holes so as to form the through-hole electrodes after the insulating film forming step; wherein the plurality of through holes are arranged such that the through holes aligning in the tilted direction are staggered in a d

Abstract: An anchored conductive damascene buried in a multi-density dielectric layer and method for forming the same, the anchored conductive damascene including a dielectric layer with an opening extending through a thickness of the dielectric layer; wherein the dielectric layer comprises at least one relatively higher density portion and a relatively lower density portion, the relatively lower density portion forming a contiguous major portion of the dielectric layer; and, wherein the opening in the relatively lower density portion has a lateral dimension relatively larger compared to the relatively higher density portion to form anchoring steps

Abstract: Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.

Abstract: A method is provided for forming at least one TSV interconnect structure surrounded by at least one isolating trench-like structure having at least one airgap. The method comprises at least the steps of providing a substrate having a first main surface and producing simultaneous at least one a TSV hole and a trench-like structure surrounding the TSV hole and separated by remaining substrate material. The method also comprises thereafter depositing a dielectric liner in order to smoothen the sidewalls of the etched TSV hole and to pinch-off the opening of the trench-like structure at the first main surface of the substrate in order to create at least one airgap in said trench-like structure and depositing a conductive material in said TSV hole in order to create a TSV interconnect. A corresponding substrate is also provided.

Abstract: In methods of manufacturing a semiconductor device, a substrate having a first surface and a second surface opposite to the first surface is prepared. A sacrificial layer pattern is formed in a region of the substrate that a through electrode will be formed. The sacrificial layer pattern extends from the first surface of the substrate in a thickness direction of the substrate. An upper wiring layer is formed on the first surface of the substrate. The upper wiring layer includes a wiring on the sacrificial layer pattern. The second surface of the substrate is partially removed to expose the sacrificial layer pattern. The sacrificial layer pattern is removed from the second surface of the substrate to form an opening that exposes the wiring. A through electrode is formed in the opening to be electrically connected to the wiring.

Abstract: A bonding structure of a semiconductor package includes: a first conductive member configured to transmit an electrical signal; and a bonding pad configured to be electrically coupled to a surface of the first conductive member and comprising a plurality of sub bonding pads.

Abstract: A method of fabricating a semiconductor device, a process of fabricating a through substrate via and a substrate with through vias are provided. The substrate with through vias includes a semiconductor substrate having a back surface and a via penetrating the back surface, a metal layer, a first insulating layer and a second insulating layer. The first insulating layer is formed on the back surface of the substrate and has an opening connected to the through via. The second insulating layer is formed on the first insulating layer and has a portion extending into the opening and the via to form a trench insulating layer. The bottom of the trench insulating layer is etched back to form a footing portion at the corner of the via. The footing portion has a height less than a total height of the first and second insulating layers.

Abstract: The present invention discloses an integrated circuit (IC) comprising a bond pad (160); a substrate stack carrying a first layer (130) comprising conductive regions (135); and an interconnect layer (140) over the first layer (130) comprising a dielectric material portion (400) between the bond pad (160) and the substrate stack, said portion comprising a plurality of air-filled trenches (345) defining at least one pillar (340) of the dielectric material (400), at least said air-filled trenches (345) being capped by a porous capping layer (440). The interconnect layer (140), which typically is one of the uppermost interconnect layers of the IC, has an improved resilience to pressure exerted on the bond pad (160). The present invention further teaches a method for manufacturing such an IC.

Abstract: Provided are a method for manufacturing a semiconductor package and a semiconductor package manufactured using the method. The method includes providing a substrate having a first region and a second region having a higher step difference than the first region, i.e., having a difference in height, forming a mask pattern having a first opening exposing a portion of the first region and a second opening exposing a portion of the second region on the substrate, forming first and second bump material films filling the first and second openings, respectively, and forming the first and second bumps by performing a reflow process on the first and second bump material films, wherein the first opening has a lower portion having the same width with the second opening and a top portion having a width greater than the second opening.

Abstract: A method is disclosed for depositing multiple seed layers for metallic interconnects over a substrate, the substrate includes a patterned insulating layer which comprises an opening surrounded by a field, said opening has sidewalls and top corners, and the method including: depositing a continuous seed layer over the sidewalls, using a first set of deposition parameters; and depositing another seed layer over the substrate, including inside the at least one opening and over a portion of said field, using a second set of deposition parameters, wherein: the second set of deposition parameters includes one deposition parameter which is different from any parameters in the first set, or whose value is different in the first and second sets; the continuous seed layer has a thickness in a range from about 20 ? to not more than 250 ? over the field; and the combined seed layers leave sufficient room for electroplating inside the opening.

Abstract: A semiconductor device with vertical current flow includes a body having a substrate made of semiconductor material. At least one electrical contact on a first face of the body. A metallization structure is formed on a second face of the body, opposite to the first face. The metallization structure is provided with metal vias, which project from the second face within the substrate so as to form a high-conductivity path in parallel with portions of said substrate.

Abstract: A semiconductor device with vertical current flow includes a body having a substrate made of semiconductor material. At least one electrical contact on a first face of the body. A metallization structure is formed on a second face of the body, opposite to the first face. The metallization structure is provided with metal vias, which project from the second face within the substrate so as to form a high-conductivity path in parallel with portions of said substrate.

Abstract: In a semiconductor device having a through-hole electrode and a manufacturing method thereof, a dummy groove hole portion for forming insulating portion insulating wirings from each other is provided, to surround a rewiring layer including a through-hole electrode on a back surface of a semiconductor substrate. This allows the wirings to be insulated from each other just by removing the metal layer existing at a bottom portion of the dummy groove hole portion. Thus, a reduction in the processing time can be realized.

Abstract: In a method of manufacturing a semiconductor device, a first etching mask and a second etching mask are formed sequentially on a metal gate structure on a substrate and a first insulating interlayer covering a sidewall of the metal gate structure respectively. An opening is formed to expose a top surface of the substrate by removing a portion of the first insulating interlayer not overlapped with the first etching mask or the second etching mask. A metal silicide pattern is formed on the exposed top surface of the substrate. A plug on the metal silicide pattern is formed to fill a remaining portion of the opening. Further, a planarization layer may be used as the second etching mask.

Abstract: Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a conductive material in an interconnect opening within an interlayer dielectric material that is disposed on a substrate, forming a low density dielectric material on a surface of the dielectric layer and on a surface of the conductive material, and forming a high density dielectric barrier layer on the low density dielectric layer.

Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.

Abstract: A base conductive member is formed on a surface and in a hole section of a substrate, and a resist is formed on a part of the base conductive member in which a conductive layer is not to be formed. The conductive layer is formed on a part except for the part in which the resist has been formed, and a mask metal is formed on the conductive layer. Then, the resist is removed, and the base conductive member is etched using the mask metal as a mask to form the conductive layer into a predetermined shape.

Abstract: Bond pads on an integrated circuit are provided with planarizing dielectric structures to permit the electroplating of metal posts having planar top surfaces. The metal posts contact at least three sides of the planarizing dielectric structures. The planarizing dielectric structures can be used on integrated circuits having bond pads of different sizes to electroplate metal posts having the same height.

Abstract: A method of forming a semiconductor device includes the following processes. A first interlayer insulating film is formed over a cell transistor and a peripheral transistor. A cell contact hole is formed in the first interlayer insulating film, the cell contact hole reaching the cell transistor. A lower contact plug is formed at a bottom of the cell contact hole. A peripheral contact hole is formed in the first interlayer insulating film, the peripheral contact hole reaching the peripheral transistor. A first peripheral contact plug is simultaneously formed in the peripheral contact hole and an upper contact plug in the cell contact hole, the upper contact plug being disposed on the lower contact plug.

Abstract: Provided is a vertical electrode structure using a trench and a method of manufacturing the vertical electrode structure. The method of forming a vertical electrode structure using a trench includes steps of: forming the trench on a predetermined region of a semiconductor substrate; and forming electrode layers in predetermined regions of inner and outer portions of the trench. In this manner, the electrode deposition in the vertical direction is established by using the trench, so that it is possible to form a deposited electrode having a size of several hundred nm or less by a short processing time and a low processing cost.

Abstract: A process of forming an integrated circuit using a dual damascene interconnect process by etching a via hole in an ILD and filling the via hole with a sacrificial via fill material. A trench etch hard mask layer is formed over the ILD. An inorganic hard mask layer is formed over the trench etch hard mask layer. The inorganic hard mask layer is etched to form an etch mask for the trench etch hard mask layer, which is subsequently etched to form an etch mask for the trench etch process. The sacrificial via fill material etches at a comparable rate to the ILD layer. The trench etch hard mask layer is removed and the sacrificial via fill material is removed from the via hole.

Abstract: The method comprises affixing a thin sheet of crystal (8) onto metal (6) of same type as the sheet but amorphous or of small grain size, deposited in trenches of a substrate (1) to form interconnect lines for example. Annealing progressively imposes the crystalline structure of the sheet onto the lines. When the crystal (8) is removed, highly conductive crystalline lines are obtained since the grains thereof have been greatly enlarged.

Abstract: One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.

Abstract: A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period.

Abstract: In a method of forming a contact plug of a semiconductor device, a nitride layer is prevented from being broken by forming a passivation layer over the nitride layer when contact holes are formed by etching an insulating layer between select lines formed over a semiconductor substrate. In an etch process of forming the contact plug, the passivation layer formed on sidewalls of the select lines is formed twice to protect the sidewalls of the select lines. Accordingly, the sidewalls of the select lines can be prevented from being damaged. Consequently, a process margin necessary to form a contact plug can be increased and, therefore, a smaller contact plug can be formed.

Abstract: Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

Abstract: According to one embodiment, an exposure method is disclosed. The method can include applying light to a photomask by an illumination. The method can include converging diffracted beams emitted from the photomask by a lens. In addition, the method can include imaging a plurality of point images on an exposure surface. On the photomask, a light transmitting region is formed at a lattice point represented by nonorthogonal unit cell vectors, and in the illumination, a light emitting region is set so that three or more of the diffracted beams pass through positions equidistant from center of a pupil of the lens.

Abstract: An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.

Abstract: In a method of manufacturing a semiconductor device according to an embodiment, an etching stopper, an oxide film and a mask material are formed. A trench pattern is formed in the mask material. The oxide film is etched to form the trench pattern therein by using the mask material having the trench pattern formed therein as a mask. The etching stopper is etched until the etching stopper is penetrated to form the trench pattern therein, by using the oxide film having the trench pattern formed therein as a mask. A Cu film is formed to be filled in the trench pattern formed in the etching stopper and the oxide film and to cover the top surface of the oxide film. CMP is performed on the Cu film and the oxide film until the top surface of the etching stopper serving as a stopper is exposed.

Abstract: A semiconductor package includes: a semiconductor substrate; an inner insulator layer formed on the substrate; at least one internal wiring extending from a front side of the substrate along one of lateral sides of the substrate to a rear side of the substrate; a first outer insulator layer disposed at the front side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole; and a second outer insulator layer disposed at the rear side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole which exposes a portion of the internal wiring.

Abstract: A method for forming an interconnect structure includes forming a mandrel above a base layer, forming spacers on the mandrel, forming recesses in the base layer using the spacers as an etch template, and forming a conductive material in the recesses.

Abstract: Top-down methods of increasing reflectivity of tungsten films to form films having high reflectivity, low resistivity and low roughness are provided. The methods involve bulk deposition of tungsten followed by a removing a top portion of the deposited tungsten. In particular embodiments, removing a top portion of the deposited tungsten involve exposing it to a fluorine-containing plasma. The methods produce low resistivity tungsten bulk layers having lower roughness and higher reflectivity. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. Applications include forming tungsten bit lines.

Abstract: In sophisticated semiconductor devices, a contact structure may be formed on the basis of a void positioned between closely spaced transistor elements wherein disadvantageous metal migration along the void may be suppressed by sealing the voids after etching a contact opening and prior to filling in the contact metal. Consequently, significant yield losses may be avoided in well-established dual stress liner approaches while, at the same time, superior device performance may be achieved.

Abstract: A semiconductor substrate can be patterned to define a trench and a feature. In an embodiment, the trench can be formed such that after filling the trench with a material, a bottom portion of the filled trench may be exposed during a substrate thinning operation. In another embodiment, the trench can be filled with a thermal oxide. The feature can have a shape that reduces the likelihood that a distance between the feature and a wall of the trench will be changed during subsequent processing. A structure can be at least partly formed within the trench, wherein the structure can have a relatively large area by taking advantage of the depth of the trench. The structure can be useful for making electronic components, such as passive components and through-substrate vias. The process sequence to define the trenches and form the structures can be tailored for many different process flows.

Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.

Abstract: A semiconductor device includes an interlayer film formed over a semiconductor substrate. A groove is formed in the interlayer film. A wiring formed in the groove is a copper alloy including copper and a metal element. An oxide layer of the metal element is formed over the surface of the wiring. The oxide layer is formed in a first region along a grain boundary of a copper crystal and a second region surrounded by the grain boundary, over the surface of the wiring. The oxide layer formed in the first region has a thickness greater than that of the oxide layer formed in the second region.

Abstract: A method for making a semiconductor device including at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided in interconnection layers underlying and overlying the one interconnection layer.

Abstract: Methods of filling high aspect ratio features provided on partially manufactured semiconductor substrates with tungsten-containing materials are provided. In certain embodiments, the methods include partial filling a high aspect ratio feature with a layer of tungsten-containing materials and selective removal of the partially filled materials from the feature cavity. Substrates processed using these methods have improved step coverage of the tungsten-containing materials filled into the high aspect ratio features and reduced seam sizes.

Abstract: Methods of controlling deposition of metal on field regions of a substrate in an electroplating process are provided. In one aspect, a dielectric layer is deposited under plasma on the field region of a patterned substrate, leaving a conductive surface exposed in the openings. Electroplating on the field region is reduced or eliminated, resulting in void-free features and minimal excess plating. In another aspect, a resistive layer, which may be a metal, is used in place of the dielectric. In a further aspect, the surface of the conductive field region is modified to change its chemical potential relative to the sidewalls and bottoms of the openings.

Abstract: A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level including conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and (d) annealing the structure.

Abstract: Method of manufacturing a semiconductor device, which achieves a reduction in manufacturing cost and prevents, a damage on the interconnect layer by an influence of the etchant solution, since the support substrate can be easily stripped from the interconnect layer. The method of manufacturing a semiconductor device includes: forming an interconnect film, by forming a seed metal layer on a support substrate and a protective film contacting with an end of an interface between the support substrate and the seed metal layer, and by growing a plated material from a surface of the seed metal layer; mounting a semiconductor chip on the interconnect film; removing at least a portion of the protective film to form a region where the support substrate and the seed metal layer are exposed; and stripping the support substrate from the region as a starting point to remove thereof from the seed metal layer.

Abstract: A device of filling metal in a through-via-hole formed in a semiconductor wafer and a method of filling metal in a through-via-hole using the same are disclosed. A device of filling metal in a through-via-hole formed in a semiconductor wafer includes a jig base comprising a jig configured to fix the wafer having the through-via-hole formed therein; a upper chamber 120 installed on the jig base; a lower chamber installed under the jig base; a heater installed in the upper chamber, the heater configured to apply heat to filling metal placed on the wafer to melt the filling metal; and a vacuum pump configured to generate pressure difference between the upper chamber and the lower chamber by the pressure of the lower chamber reduced by discharging air of the lower chamber 130 outside, only to fill the melted filling metal in the through-via-hole.

Abstract: A circuit substrate includes the following elements. A conductive layer and a dielectric layer are disposed on an inner circuit structure in sequence, and a plurality of conductive blind vias are embedded in the dielectric layer and connected to a portion of the conductive layer. A plating seed layer is disposed between each of the first blind vias and the first conductive layer. Another conductive layer is disposed on the dielectric layer, wherein a portion of the another conductive layer is electrically connected to the conductive layer through the conductive blind vias. A third plating seed layer is disposed between the third conductive layer and each of the first blind vias and on the first dielectric layer.

Abstract: A manufacturing process of a circuit substrate is provided. A conductive structure including a first patterned conductive layer, a first dielectric layer, a second dielectric layer, a first conductive layer, and a second conductive layer is provided. The first dielectric layer and the second dielectric layer are respectively disposed on two opposite surfaces of the first patterned conductive layer. The first conductive layer and the second conductive layer are respectively disposed on the first dielectric layer and the second dielectric layer. The first dielectric layer is between the first patterned conductive layer and the first conductive layer. The second dielectric layer is between the first patterned conductive layer and the second conductive layer. A conductive via is formed at the conductive structure. The first conductive layer and the second conductive layer are patterned to respectively form a second patterned conductive layer and a third patterned conductive layer.

Abstract: A process to form a via hole in a semiconductor wafer is disclosed. The process includes steps of, preparing a metal mask and etching the wafer by the metal mask as the etching mask. The preparation of the metal mask includes steps of: coating a nega-resist on the back surface of the wafer, carrying out the photolithography for the coated nega-resist, plating a metal selectively by the patterned photoresist, and removing the patterned photoresist.

Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

Abstract: An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semiconductor substrate; creating a plurality of voids inside the insulating layer, with the plurality of voids spanning across a predefined area and being substantially confined within a range of depth below a top surface of the insulating layer; creating at least one via hole in the insulating layer, with the via hole passing through the predefined area; and filling the via hole, and the plurality of voids inside the insulating layer through at least the via hole, with a conductive material to form a local metallization. A semiconductor structure having the local metallization is also provided.

Abstract: Provided is an electrically conductive via for reducing flux residue. The via has a first aperture having a first diameter size. The via further has a second aperture having a second diameter size. A chamber is disposed between the first aperture and the second aperture, the chamber having a third diameter size. At least one of the diameters being of a different dimension than the other two. In addition, the via may also provide improved test point access in addition to reducing flux residue.

Abstract: A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench therein, forming a conductive layer having a top lower than an opening of the trench in the trench, performing a selective metal chemical vapor deposition (CVD) to form a metal layer having a top lower than the substrate in the trench, and forming a protecting layer filling the trench on the metal layer.