By Altering Solid-state Characteristics Of Conductive Members, E.g., Fuses, In Situ Oxidation, Laser Melting (epo) Patents (Class 257/E21.592)
  • Patent number: 10192826
    Abstract: A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: January 29, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Ju Li, Kuo-Chin Hung, Min-Chuan Tsai, Wei-Chuan Tsai, Yi-Han Liao, Chun-Tsen Lu, Fu-Shou Tsai, Li-Chieh Hsu
  • Patent number: 10164074
    Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric layer, a gate electrode and source and drain regions. The gate dielectric layer extends into a first trench in the semiconductor substrate. The gate electrode is over the gate dielectric layer and is at least partially embedded in the first trench in the semiconductor substrate. The source and drain regions are in the semiconductor substrate and proximate the first trench in the semiconductor substrate.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Cheng Wu, Li-Feng Teng, Alexander Kalnitsky
  • Patent number: 9040370
    Abstract: A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiao-Lan Yang
  • Patent number: 9024410
    Abstract: A semiconductor device includes a first insulating film formed above a semiconductor substrate, a fuse formed above the first insulating film, a second insulating film formed above the first insulating film and the fuse and including an opening reaching the fuse, and a third insulating film formed above the second insulating film and in the opening.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: May 5, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Shigetoshi Takeda
  • Patent number: 9024411
    Abstract: A three-dimensionally (3d) confined conductor advantageously used as an electronic fuse and self-aligned methods of forming the same. By non-conformal deposition of a dielectric film over raised structures, a 3d confined tube, which may be sub-lithographic, is formed between the raised structures. Etching holes which intersect the 3d confined region and subsequent metal deposition fills the 3d confined region and forms contacts. When the raised structures are gates, the fuse element may be located at the middle of the line (i.e. in pre-metal dielectric). Other methods for creating the structure are also described.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventors: Junjun Li, Yan Zun Li, Chengwen Pei, Pinping Sun
  • Patent number: 9012277
    Abstract: Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and substantially diffusionless annealing techniques. One illustrative method disclosed herein includes forming first and second cavities in PMOS and NMOS device regions, respectively, of a semiconductor substrate, and thereafter performing first and second epitaxial deposition processes to form in situ doped first and second embedded material regions in the first and second cavities, respectively. The method further includes, among other things, performing a single heat treating process to activate dopants in the in situ doped first and second embedded material regions.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Patent number: 8999767
    Abstract: A method including etching a dual damascene feature in a dielectric layer, the dual damascene feature including a first via opening, a second via opening, and a trench opening, forming a seed layer within the dual damascene feature, the seed layer including a conductive material, and heating the seed layer causing the seed layer to reflow and fill the first via opening, fill the second via opening, and partially fill the trench opening to form a first via, a second via, and a fuse line, respectively, wherein the seed layer no longer remains along an entire length of a sidewall of the trench opening. The method further including forming an insulating layer on top of the fuse line, and forming a fill material on top of the insulating layer and substantially filling the trench opening.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chad M. Burke, Baozhen Li, Keith Kwong Hon Wong, Chih-Chao Yang
  • Patent number: 8952486
    Abstract: An improved electrical-fuse (e-fuse) device including a dielectric layer having a first top surface, two conductive features embedded in the dielectric layer and a fuse element. Each conductive feature has a second top surface and a metal cap directly on the second top surface. Each metal cap has a third top surface that is above the first top surface of the dielectric layer. The fuse element is on the third top surface of each metal cap and on the first top surface of the dielectric layer. A method of forming the e-fuse device is also provided.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Stephen M. Gates, Baozhen Li, Dan Edelstein
  • Patent number: 8921869
    Abstract: Light emitting devices and methods are disclosed. In one embodiment a light emitting device can include a submount and a plurality of light emitting diodes (LEDs) disposed over the submount. At least a portion of the submount can include a reflective layer at least partially disposed below a solder mask. One or more layers within the submount may include one or more holes, a rough surface texture, or combinations thereof to improve adhesion within the device. The device can further include a retention material dispensed about the plurality of LEDs. Devices and methods are disclosed for improved solder mask adhesion.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: December 30, 2014
    Assignee: Cree, Inc.
    Inventors: Erin R. F. Welch, Christopher P. Hussell, Jesse Colin Reiherzer, Joseph G. Clark
  • Patent number: 8912627
    Abstract: A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, David V. Horak, Charles W. Koburger, III, Shom Ponoth
  • Patent number: 8836077
    Abstract: A semiconductor device according to an embodiment of the present invention includes fuse patterns spaced apart from each other by a predetermined distance over a first interlayer insulation film; a second interlayer insulation film disposed between the fuse patterns over the first interlayer insulation film; and a capping film pattern formed over the fuse patterns and the second interlayer insulation films, the capping film pattern including a slot exposing the second interlayer insulation film.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: September 16, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jeong Youl Kim, Ki Soo Choi
  • Patent number: 8809165
    Abstract: A method for fusing a laser fuse in accordance with various embodiments may include: providing a semiconductor workpiece having a substrate region and at least one laser fuse; fusing the at least one laser fuse from a back side of the substrate region by means of an infrared laser beam.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: August 19, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gunther Mackh, Gerhard Leschik
  • Patent number: 8809997
    Abstract: An e-fuse structure includes a first doped region and a second doped region formed in a substrate. The first doped region has a first conductivity type and the second doped region has a second conductivity type different from the first conductivity type. The first and second doped regions contact each other. A conductive pattern is disposed on the first and second doped regions and contacts the first and second doped regions. A first contact plug is disposed on the conductive pattern in an area corresponding to the first doped region, and a second contact plug is disposed on the conductive pattern in an area corresponding to the second doped region.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongsang Cho, Intaek Ku, Donghoon Kim, Ikhwan Kim, Choulhwan Oh
  • Patent number: 8796723
    Abstract: Disclosed is a light-emitting device comprising: a carrier; a light-emitting element disposed on the carrier; a first light guide layer covering the light-emitting element; a second light guide layer covering the first light guide layer; a low refractive index layer between the first light guide layer and the second light guide layer to reflect the light from the second light guide layer; and a wavelength conversion layer covering the second light guide layer; wherein the low refractive index layer has a refractive index smaller than one of the refractive indices of first light guide layer and the second light guide layer.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: August 5, 2014
    Assignee: Epistar Corporation
    Inventors: Min-Hsun Hsieh, Chien-Yuan Wang, Tsung-Xian Lee, Chih-Ming Wang, Ming-Chi Hsu, Han-Min Wu
  • Patent number: 8779449
    Abstract: An LED array having N light-emitting diode units (N?3) comprises a permanent substrate, a bonding layer on the permanent substrate, a second conductive layer on the bonding layer, a second isolation layer on the second conductive layer, a crossover metal layer on the second isolation layer, a first isolation layer on the crossover metal layer, a conductive connecting layer on the first isolation layer, an epitaxial structure on the conductive connecting layer, and a first electrode layer on the epitaxial structure. The light-emitting diode units are electrically connected with each other by the crossover metal layer.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: July 15, 2014
    Assignee: Epistar Corporation
    Inventors: Li-Ping Jou, Yu-Chen Yang, Jui-Hung Yeh
  • Patent number: 8748888
    Abstract: A semiconductor integrated circuit includes a multi-chip package having a plurality of semiconductor chips. The semiconductor integrated circuit includes a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal. Here, the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: June 10, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jeong Woo Lee, Hyung Dong Lee, Jun Gi Choi, Sang Hoon Shin, Xiang Hua Cui
  • Patent number: 8742457
    Abstract: A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiao-Lan Yang
  • Patent number: 8729589
    Abstract: High voltage array light emitting devices, fixtures and methods are disclosed. In one embodiment a light emitting device can include a submount, a light emission area disposed over the submount and a retention material adapted to be dispensed about the light emission area. The light emitting device can be operable at high voltages which are greater than approximately 40 volts (V). In one aspect, the retention material can be least partially disposed within the light emission area such that the retention material physically separates a first section of the light emission area from a second section of the light emission area.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: May 20, 2014
    Assignee: Cree, Inc.
    Inventors: Christopher P. Hussell, Jesse C. Reiherzer, Jeffrey C. Britt, Praneet Athalye, Peter S. Andrews
  • Patent number: 8729663
    Abstract: On a silicon substrate 120 of a semiconductor device, a field oxide film 101 is provided. On the field oxide film 101, two fuses 104 are provided. Directly below the fuses 104 in the silicon substrate 120, an n-type well 102 is provided. Besides the n-type well 102, a p-type well 103 is provided in such a manner as to surround a region directly under the fuses 104 in the silicon substrate 120. A cover insulating film 108 is provided over the silicon substrate 120 and the field oxide film 101. A seal ring composed of a contact 106 and an interconnection 107 is embedded in the cover insulating film 108 so as to surround the fuses 104.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: May 20, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kiyotaka Miwa, Nayuta Kariya
  • Patent number: 8709931
    Abstract: A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: April 29, 2014
    Assignee: SK Hynix Semiconductor, Inc.
    Inventor: Byung-Duk Lee
  • Patent number: 8692375
    Abstract: A structure and design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, William R. Tonti, Chih-Chao Yang
  • Patent number: 8680544
    Abstract: The present disclosure involves a lighting instrument. The lighting instrument includes a board or substrate, for example, a printed circuit board. The lighting instrument also includes a plurality of light-emitting devices disposed on the substrate. The light-emitting devices may be light-emitting diode (LED) dies. The LED dies belong to a plurality of different bins. The bins are categorized based on the light output performance of the LED dies. In some embodiments, the LED dies may be binned based on the wavelength or radiant flux of the light output. The LED dies are distributed on the substrate according to a predefined pattern based on their bins. In some embodiments, the LED dies are bin-mixed in an interleaving manner.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: March 25, 2014
    Assignee: TSMC Solid State Lighting Ltd.
    Inventor: Chih-Lin Wang
  • Publication number: 20140070363
    Abstract: An electronic anti-fuse structure, the structure including an Mx level comprising a first Mx metal and a second Mx metal, a dielectric layer located above the Mx level, an Mx+1 level located above the dielectric layer; and a metallic element in the dielectric layer and positioned between the first Mx metal and the second Mx metal, wherein the metallic element is insulated from both the first Mx metal and the second Mx metal.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali Eliahu Lustig, Andrew H. Simon
  • Patent number: 8638589
    Abstract: An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: January 28, 2014
    Assignee: eMemory Technology Inc.
    Inventors: Hau-Yan Lu, Hsin-Ming Chen, Ching-Sung Yang
  • Publication number: 20140021578
    Abstract: An electronic fuse structure including a first Mx metal comprising a conductive cap, an Mx+1 metal located above the Mx metal, wherein the Mx+1 metal does not comprise a conductive cap, and a via, wherein the via electrically connects the Mx metal to the Mx+1 metal in a vertical orientation.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 23, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junjing Bao, Elbert Emin Huang, Yan Zun Li, Dan Moy
  • Patent number: 8629049
    Abstract: A fabrication method for fabricating an electrically programmable fuse method includes depositing a polysilicon layer on a substrate, patterning an anode contact region, a cathode contact region and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, depositing a silicide layer on the polysilicon layer, and forming a plurality of anisometric contacts on the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran
  • Publication number: 20130341757
    Abstract: The present disclosure relates to a method of fabricating a semiconductor device. A semiconductor device includes a bond pad and a fuse layer. The bond pad includes a coating on an upper surface. A dielectric layer is formed over the bond pad and the fuse layer. A passivation layer is formed over the dielectric layer. An etch is performed to form a bond pad opening and a fuse opening. The etch is performed using only a single mask. The fuse opening defines a fuse window. The upper surface of the bond pad is exposed by substantially removing the coating from the entire upper surface.
    Type: Application
    Filed: June 25, 2012
    Publication date: December 26, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Marcus Yang, Chih-Hao Lin, Hong-Seng Shue, Ruei-Hung Jang
  • Patent number: 8592941
    Abstract: The disclosure relates generally to fuse structures, methods of forming and programming the same, and more particularly to fuse structures having crack stop voids. The fuse structure includes a semiconductor substrate having a dielectric layer thereon and a crack stop void. The dielectric layer includes at least one fuse therein and the crack stop void is adjacent to two opposite sides of the fuse, and extends lower than a bottom surface and above a top surface of the fuse. The disclosure also relates to a design structure of the aforementioned.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Tom C. Lee, Kevin G. Petrunich, David C. Thomas
  • Patent number: 8592288
    Abstract: An integrated circuit including a substrate of a semiconductor material and first metal portions of a first metallization level or of a first via level defining pixels of an image. The pixels are distributed in first pixels, for each of which the first metal portion is connected to the substrate, and in second pixels, for each of which the first metal portion is separated from the substrate by at least one insulating portion.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: November 26, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Patent number: 8586466
    Abstract: Electrical fuses and methods for forming an electrical fuse. The electrical fuse includes a current shunt formed by patterning a first layer comprised of a first conductive material and disposed on a top surface of a dielectric layer. A layer stack is formed on the current shunt and the top surface of the dielectric layer surrounding the current shunt. The layer stack includes a second layer comprised of a second conductive material and a third layer comprised of a third conductive material. The layer stack may be patterned to define a fuse link as a first portion of the layer stack directly contacting the top surface of the dielectric layer and a terminal as a second portion separated from the top surface of the dielectric layer by the current shunt.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Tom C. Lee, Thomas L. McDevitt, William J. Murphy
  • Patent number: 8575639
    Abstract: Light emitting devices for light emitting diodes (LEDs) are disclosed. In one embodiment a light emitting device can include a submount and a light emission area disposed over the submount. The light emission area can include one or more light emitting diodes (LEDs), a fillet at least partially disposed about the one or more the LEDs, and filling material. The filling material can be disposed over a portion of the one or more LEDs and a portion of the fillet.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: November 5, 2013
    Assignee: Cree, Inc.
    Inventor: Christopher P. Hussell
  • Patent number: 8575718
    Abstract: The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam, William Tonti
  • Patent number: 8569775
    Abstract: An LED array having N light-emitting diode units (N?3) comprises a permanent substrate, a bonding layer on the permanent substrate, a second conductive layer on the bonding layer, a second isolation layer on the second conductive layer, a crossover metal layer on the second isolation layer, a first isolation layer on the crossover metal layer, a conductive connecting layer on the first isolation layer, an epitaxial structure on the conductive connecting layer, and a first electrode layer on the epitaxial structure. The light-emitting diode units are electrically connected with each other by the crossover metal layer.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: October 29, 2013
    Assignee: Epistar Corporation
    Inventors: Li-Ping Jou, Yu-Chen Yang, Jui-Hung Yeh
  • Patent number: 8564000
    Abstract: Light emitting devices for light emitting diodes (LEDs) are disclosed. In one embodiment a light emitting device can include a substrate, one or more LEDs disposed over the substrate, and the LEDs can include electrical connectors for connecting to an electrical element. A light emitting device can further include a retention material disposed over the substrate and the retention material can be disposed over at least a portion of the electrical connectors. The LEDs can be connected in a pattern that is non-linear.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: October 22, 2013
    Assignee: Cree, Inc.
    Inventors: Christopher P. Hussell, Peter Scott Andrews, Jesse Colin Reiherzer, David T. Emerson
  • Patent number: 8564004
    Abstract: A light emitter package comprising a light emitter disposed on a surface and a primary optic comprising an encapsulant disposed over the light emitter is disclosed. The package further comprises at least one intermediate element on the surface and at least partially surrounding the light emitter such that the intermediate element at least partially defines the shape of the primary optic. The intermediate element is configured so at least a portion of the intermediate element can be removed.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: October 22, 2013
    Assignee: Cree, Inc.
    Inventors: Eric Tarsa, Bernd Keller, Peter Guschl, Gerald Negley
  • Publication number: 20130249046
    Abstract: There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.
    Type: Application
    Filed: March 26, 2012
    Publication date: September 26, 2013
    Inventors: Hsiang-Ming Chou, Kuo-Liang Pan, Chien-Feng Tseng, Yi-Chiu Tsai, Chien-Shao Tang, Hsin-Han Chen
  • Publication number: 20130241031
    Abstract: Methods of forming an electrically programmable fuse (e-fuse) structure and the e-fuse structure are disclosed. Various embodiments of forming the e-fuse structure include: forming a dummy poly gate structure to contact a surface of a silicon structure, the dummy poly gate structure extending only a part of a length of the silicon structure; and converting an unobstructed portion of the surface of the silicon structure to silicide to form a thinned strip of the silicide between two end regions.
    Type: Application
    Filed: March 14, 2012
    Publication date: September 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yan Zun Li, Zhengwen Li, Chengwen Pei, Jian Yu
  • Patent number: 8519507
    Abstract: An electrically programmable fuse that includes an anode contact region and a cathode contact region are formed of a polysilicon layer having a silicide layer formed thereon, and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, and a plurality of anisometric contacts formed on the silicide layer of the cathode contact region or on both the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran
  • Patent number: 8519428
    Abstract: A vertical stacked light emitting structure includes a substrate unit, a stacked type light emitting module, and a flip-chip type light emitting module. The substrate unit includes a substrate body. The stacked type light emitting module includes a first light emitting unit and a light guiding unit. The first light emitting unit includes at least one first LED bare chip disposed on and electrically connected to the substrate body, and the light guiding unit includes at least one light guiding body disposed on the first LED bare chip. The flip-chip type light emitting module includes a second light emitting unit. The second light emitting unit includes at least one second LED bare chip disposed on the light guiding body and electrically connected to the substrate body. Hence, the first LED bare chip, the light guiding body, and the second LED bare chip are stacked on top of one another sequentially.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: August 27, 2013
    Assignee: Azurewave Technologies, Inc.
    Inventors: Chi-Hsing Hsu, Chun-Yu Lu, Ming-Che Kuo
  • Patent number: 8518762
    Abstract: Provided is a method for manufacturing a semiconductor device having favorable electric characteristics with a high yield. A groove and/or a contact hole reaching a semiconductor region or a conductive region is formed in an insulating film covering the semiconductor region or the conductive region; a first conductive film is formed in the groove and/or the contact hole; the first conductive film is exposed to plasma generated from a mixed gas of an oxidizing gas and a halogen-based gas and to an atmosphere containing water to be fluidized partially or entirely; and a second conductive film is formed over the first conductive film.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: August 27, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Yuta Endo
  • Patent number: 8513769
    Abstract: Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Charles T. Black, Matthew E. Colburn, Timothy J. Dalton, Daniel C. Edelstein, Wai-Kin Li, Anthony K. Stamper, Haining S. Yang
  • Patent number: 8487404
    Abstract: The present invention provides fuse patterns and a method of manufacturing the same. According to the present invention, an insulating layer and a contact plug are filled between fuse patterns which are formed to have their ends broken and are isolated from each other. In case of a fail cell, the insulating layer is broken owing a difference in an electrical bias (current or voltage) between a metal wire and the fuse patterns, and a short is generated between the fuse patterns. Accordingly, embodiments avoid damage to a semiconductor substrate associated with a conventional fuse repair method employing laser energy, and the area of a fuse box can be reduced.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: July 16, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ki Soo Choi
  • Patent number: 8486773
    Abstract: A semiconductor film having an impurity region to which at least an n-type or p-type impurity is added and a wiring are provided. The wiring includes a diffusion prevention film containing a conductive metal oxide, and a low resistance conductive film over the diffusion prevention film. In a contact portion between the wiring and the semiconductor film, the diffusion prevention film and the impurity region are in contact with each other. The diffusion prevention film is formed in such a manner that a conductive film is exposed to plasma generated from a mixed gas of an oxidizing gas and a halogen-based gas to form an oxide of a metal material contained in the conductive film, the conductive film in which the oxide of the metal material is formed is exposed to an atmosphere containing water to be fluidized, and the fluidized conductive film is solidified.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: July 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tetsuhiro Tanaka
  • Patent number: 8476157
    Abstract: An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.?doped regions. Another N.sup.+doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.?doped regions on the substrate. An anti-fuse is defined over the N.sup.+doped region. Two insulator regions are deposited over the two P.sup.?doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: July 2, 2013
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8471296
    Abstract: A method forms an eFuse structure that has a pair of adjacent semiconducting fins projecting from the planar surface of a substrate (in a direction perpendicular to the planar surface). The fins have planar sidewalls (perpendicular to the planar surface of the substrate) and planar tops (parallel to the planar surface of the substrate). The tops are positioned at distal ends of the fins relative to the substrate. An insulating layer covers the tops and the sidewalls of the fins and covers an intervening substrate portion of the planar surface of the substrate located between the fins. A metal layer covers the insulating layer. A pair of conductive contacts are connected to the metal layer at locations where the metal layer is adjacent the top of the fins.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Louis C. Hsu, William R. Tonti, Chih-Chao Yang
  • Publication number: 20130153960
    Abstract: A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiao-Lan Yang
  • Publication number: 20130147009
    Abstract: A semiconductor device includes: a fuse pattern formed at a first level, a first line pattern formed at a second level lower than the first level, a second line pattern formed at a third level higher than the first level, a first contact plug coupling the fuse pattern to the first line pattern 310, a second contact plug coupling the fuse pattern to the second line pattern, and a fuse blowing region provided over first line pattern and overlapping with the first contact plug at least partially.
    Type: Application
    Filed: November 9, 2012
    Publication date: June 13, 2013
    Applicant: Sk hynix Inc.
    Inventor: Sk hynix Inc.
  • Patent number: 8455908
    Abstract: Light emitting devices and methods are disclosed. In one embodiment a light emitting device can include a submount and a plurality of light emitting diodes (LEDs) disposed over the submount. At least a portion of the submount can include a reflective layer at least partially disposed below a solder mask. One or more layers within the submount may include one or more holes, a rough surface texture, or combinations thereof to improve adhesion within the device. The device can further include a retention material dispensed about the plurality of LEDs. Devices and methods are disclosed for improved solder mask adhesion.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: June 4, 2013
    Assignee: Cree, Inc.
    Inventors: Erin R. F. Welch, Christopher P. Hussell, Jesse Colin Reiherzer, Joseph Clark
  • Patent number: 8445362
    Abstract: An apparatus and method for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dan Moy, Stephen Wu, Peter Wang, Brian W. Messenger, Edwin Soler, Gabriel Chiulli
  • Publication number: 20130113071
    Abstract: A semiconductor device includes a fuse configured to be programmed in response to a laser, a protective layer formed under the fuse and overlapping with a portion of the fuse, and a heat emission portion coupled with the protective layer.
    Type: Application
    Filed: September 14, 2012
    Publication date: May 9, 2013
    Inventor: Min-Yung LEE