By Altering Solid-state Characteristics Of Conductive Members, E.g., Fuses, In Situ Oxidation, Laser Melting (epo) Patents (Class 257/E21.592)
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Patent number: 7728407Abstract: A semiconductor device includes a semiconductor substrate, and an electrical fuse including a first conductor including a first cutting target region, and a second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on the semiconductor substrate, wherein a flowing-out region is formed of the first conductor flowing toward outside between the first cutting target region and the second cutting target region in a condition of cutting the electrical fuse.Type: GrantFiled: May 16, 2007Date of Patent: June 1, 2010Assignee: NEC Electronics CorporationInventor: Takehiro Ueda
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Publication number: 20100124825Abstract: A Cl2 gas plasma is generated at a site within a chamber between a substrate and a metal member. The metal member is etched with the Cl2 gas plasma to form a precursor. A nitrogen gas is excited in a manner isolated from the chamber accommodating the substrate. A metal nitride is formed upon reaction between excited nitrogen and the precursor, and formed as a film on the substrate. After film formation of the metal nitride, a metal component of the precursor is formed as a film on the metal nitride on the substrate. In this manner, a barrier metal film with excellent burial properties and a very small thickness is produced at a high speed, with diffusion of metal being suppressed and adhesion to the metal being improved.Type: ApplicationFiled: January 26, 2010Publication date: May 20, 2010Applicant: CANON ANELVA CORPORATIONInventors: Hitoshi Sakamoto, Naoki Yahata, Ryuichi Matsuda, Yoshiyuki Ooba, Toshihiko Nishimori
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Patent number: 7718552Abstract: A method and device of nanostructured titania that is crack free. A method in accordance with the present invention comprises depositing a Ti film on a surface, depositing a masking layer on the Ti film, etching said masking layer to expose a limited region of the Ti film, the limited region being of an area less than a threshold area, oxidizing the exposed limited region of the Th.ucsbi film, and annealing the exposed limited region of the Ti film.Type: GrantFiled: April 4, 2006Date of Patent: May 18, 2010Assignee: The Regents of the University of CaliforniaInventors: Zuruzi Abu Samah, Noel C. MacDonald, Marcus Ward, Martin Moskovits, Andrei Kolmakov, Cyrus R. Safinya
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Publication number: 20100117190Abstract: A fuse structure for an IC device and methods of fabricating the structure are provided. The fuse structure comprises a metal-containing conductive strip formed over a portion of a semiconductor substrate. A dielectric layer is formed over the semiconductor substrate, covering the conductive strip. A first interconnect and a second interconnect are formed in vias extending through the dielectric layer, each physically and electrically connecting to a part of the conductive layer. First and second wiring structures are formed over the dielectric layer in electrical contact with the first and second interconnects respectively. The contact area between one of the interconnects and the strip is chosen so that electromigration will occur when a pre-selected current is applied to the fuse structure.Type: ApplicationFiled: November 13, 2008Publication date: May 13, 2010Inventors: Harry CHUANG, Kong-Beng Thei, Sheng-Chen Chung, Mong-Song Liang
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Patent number: 7713793Abstract: A method for manufacturing a fuse of a semiconductor device comprises forming an island-type metal fuse in a region where a laser is irradiated, so that laser energy may not be dispersed in a fuse blowing process, thereby improving repair efficiency.Type: GrantFiled: May 8, 2008Date of Patent: May 11, 2010Assignee: Hynix Semiconductor Inc.Inventors: Hyung Jin Park, Won Ho Shin
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Publication number: 20100109122Abstract: Methods of fabricating a multi-layer semiconductor structure are provided. In one embodiment, a method includes depositing a first dielectric layer over a semiconductor structure, depositing a first metal layer over the first dielectric layer, patterning the first metal layer to form a plurality of first metal lines, and depositing a second dielectric layer over the first metal lines and the first dielectric layer. The method also includes removing a portion of the second dielectric layer over selected first metal lines to expose a respective top surface of each of the selected first metal lines. The method further includes reducing a thickness of the selected first metal lines to be less than a thickness of the unselected first metal lines. A multi-layer semiconductor structure is also provided.Type: ApplicationFiled: November 5, 2008Publication date: May 6, 2010Applicant: STMICROELECTRONICS INC.Inventors: Hai Ding, Fuchao Wang, Zhiyong Xie
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Patent number: 7709401Abstract: An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.Type: GrantFiled: February 22, 2008Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventors: Fen Chen, Cathryn Jeanne Christiansen, Michael Anthony Shinosky, Timothy Dooling Sullivan
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Patent number: 7704804Abstract: A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which is formed simultaneously with the formation of the interconnect structure. This produces a reliable and repeatable fuse structure that has controllable passivation layer over the fuse structure that is easily manufactured.Type: GrantFiled: December 10, 2007Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter
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Publication number: 20100099222Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.Type: ApplicationFiled: December 21, 2009Publication date: April 22, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Rajendra D. Pendse, KyungOe Kim, Taewoo Kang
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Publication number: 20100096722Abstract: The present invention relates to a fuse in a semiconductor device and method for fabricating the same. An oxide film is formed on sidewalls of a barrier metal layer in a bottom portion of a fuse pattern, thereby preventing the barrier metal layer from being exposed. As a result, the oxidation of the barrier metal layer is inhibited to improve characteristics of the device.Type: ApplicationFiled: December 22, 2008Publication date: April 22, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Jeong Soo Kim, Won Ho Shin
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Patent number: 7701035Abstract: The present invention relates to a laser fuse structure for high power applications. Specifically, the laser fuse structure of the present invention comprises first and second conductive supporting elements (12a, 12b), at least one conductive fusible link (14), first and second connection elements (20a, 20b), and first and second metal lines (22a, 22b). The conductive supporting elements (12a, 12b), the conductive fusible link (14), and the metal lines (22a, 22b) are located at a first metal level (3), while the connect elements (20a, 20b) are located at a second, different metal level (4) and are connected to the conductive supporting elements (12a, 12b) and the metal lines (22a, 22b) by conductive via stacks (18a, 18b, 23a, 23b) that extend between the first and second metal levels (3, 4).Type: GrantFiled: November 30, 2005Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: Stephen E. Greco, Erik L. Hedberg, Dae-Young Jung, Paul S. McLaughlin, Christopher D. Muzzy, Norman J. Rohrer, Jean E. Wynne
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Publication number: 20100090253Abstract: Programmable power management using a nanotube structure is disclosed. In one embodiment, a method includes coupling a nanotube structure of an integrated circuit to a conductive surface when a command is processed, and enabling a group of transistors of the integrated circuit based on the coupling the nanotube structure to the conductive surface. A current may be applied to the nanotube structure to couple the nanotube structure to the conductive surface. The nanotube structure may be formed from a material chosen from one or more of a polymer, carbon, and a composite material. The group of transistors may be enabled during an activation sequence of the integrated circuit. In addition, one or more transistors of the group of transistors may be disengaged from the one or more power sources (e.g., to minimize leakage) when the nanotube structure is decoupled from the conductive surface.Type: ApplicationFiled: December 16, 2009Publication date: April 15, 2010Inventor: JONATHAN BYRN
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Patent number: 7691684Abstract: A method of forming an antifuse forms a material layer and then patterns the material layer into a fin. The center portion of the fin is converted into a substantially non-conductive region and the end portions of the fin into conductors. The process of converting the center portion of the fin into an insulator allows a process of heating the fin above a predetermined temperature to convert the insulator into a conductor. Thus, the fin-type structure that can be selectively converted from an insulator into a permanent conductor using a heating process.Type: GrantFiled: July 31, 2008Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Chung H. Lam, Edward J. Nowak
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Patent number: 7682957Abstract: A method of forming a pad and a fuse in a semiconductor device. A copper layer located in both a fuse region and a pad region is formed in a dielectric layer. A first insulating layer is formed on the dielectric layer to cover the copper layer and selectively etched to expose the copper layer in the fuse region. An aluminum fuse is formed on the first insulating layer in the fuse region and connected to the exposed copper layer. A second insulating layer is formed on both the aluminum fuse and the first insulating layer and selectively etched together with the first insulating layer to expose the underlying copper layer in the pad region. An aluminum pad is formed on the second insulating layer in the pad region and connected to the exposed copper layer in the pad region. At least one third insulating layer is formed on both the aluminum pad and the second insulating layer and selectively etched to expose the aluminum pad only.Type: GrantFiled: December 29, 2005Date of Patent: March 23, 2010Assignee: Dongbu Electronics Co., Ltd.Inventor: Yeong Sil Kim
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Patent number: 7682867Abstract: Disclosed are an organic thin-film transistor and a manufacturing method thereof, the organic thin-film transistor comprising a support and provided thereon, a gate electrode, an insulation layer, a source electrode, a drain electrode, and an organic semiconductor layer, the support comprising at least one of resins, and the organic semiconductor layer containing at least one of organic semiconducting materials, wherein a phase transition temperature of one of the organic semiconducting materials is not more than a glass transition point of one of the resins.Type: GrantFiled: June 8, 2007Date of Patent: March 23, 2010Assignee: Konica Minolta Holdings, Inc.Inventor: Katsura Hirai
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Patent number: 7682958Abstract: A method for producing an integrated circuit including a fuse element, a fuse-memory element or a resistor element is disclosed. In one embodiment, at least one metallization layer is applied onto a substrate. A hard mask is applied onto the at least one metallization layer. The at least one metallization layer is wet chemically etched by using the hard mask and the fuse element. The fuse-memory element or the resistor element is formed in a region in which the at least one metallization layer has been etched.Type: GrantFiled: July 31, 2007Date of Patent: March 23, 2010Assignee: Infineon Technologies AGInventors: Georg Seidemann, Reinhard Goellner
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Publication number: 20100059766Abstract: An integrated circuit including a substrate of a semiconductor material and first metal portions of a first metallization level or of a first via level defining pixels of an image. The pixels are distributed in first pixels, for each of which the first metal portion is connected to the substrate, and in second pixels, for each of which the first metal portion is separated from the substrate by at least one insulating portion.Type: ApplicationFiled: August 10, 2009Publication date: March 11, 2010Applicant: STMicroelectronics (Rousset) SASInventors: Pascal Fornara, Fabrice Marinet
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Patent number: 7674691Abstract: An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.Type: GrantFiled: March 7, 2007Date of Patent: March 9, 2010Assignee: International Business Machines CorporationInventors: Alberto Cestero, Byeongju Park, John M. Safran
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Patent number: 7666790Abstract: A method for fabricating a silicide gate field effect transistor includes masking a silicon source/drain region prior to forming the silicide gate by annealing a metal silicide forming metal layer contacting a silicon-containing gate. The silicide gate may be either a fully silicided gate or a partially silicided gate. After unmasking the source/drain region a silicide layer may be formed upon the source/drain region, and also upon the partially silicided gate. The second silicide layer and the partially silicided gate also provide a fully silicided gate.Type: GrantFiled: April 27, 2006Date of Patent: February 23, 2010Assignee: International Business Machines CorporationInventors: Zhijiong Luo, William K. Henson, Christian Lavoie, Huilong Zhu
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Patent number: 7666717Abstract: A non-volatile device includes a semiconductor substrate having a fuse window region. At least one fuse crosses the fuse window region. Field regions are arranged outside of the fuse window region and arranged under end portions of the at least one fuse. An isolation layer is configured to isolate the field regions. A fuse insulating layer is interposed between the at least one fuse and the field regions.Type: GrantFiled: October 5, 2006Date of Patent: February 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Sun Sel, Sung-Nam Chang, Dae-Woong Kang, Bong-Tae Park
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Publication number: 20100038747Abstract: An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.Type: ApplicationFiled: August 15, 2008Publication date: February 18, 2010Applicant: International Business Machines CorporationInventors: Kaushik Chanda, Ronald G. Filippi, Joseph M. Lukaitis, Ping-Chuan Wang
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Publication number: 20100013045Abstract: The present invention provides a method of integrating a structure, e.g. a fuse, for use in a semiconductor device, the method comprises several steps, the first step is providing a first layer of sacrificial material (1) on a substrate. The second step is providing the structure (5) on the first layer of sacrificial material, the structure having two terminal portions. The third step is providing a second layer of sacrificial material (3) over the first layer of sacrificial material and over a length of the structure between the terminal portions such that the length of the structure is surrounded by sacrificial material, said length defining a usable portion of the structure. The fourth step is providing a layer of dielectric material such that the first and second layers of sacrificial material and the structure are encased by the layer of dielectric material and the substrate. The fifth step is forming a passage through the dielectric material to provide access to the sacrificial material.Type: ApplicationFiled: August 7, 2006Publication date: January 21, 2010Inventor: Andrew Weeks
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Patent number: 7645696Abstract: Methods of depositing thin seed layers that improve continuity of the seed layer as well as adhesion to the barrier layer are provided. According to various embodiments, the methods involve performing an etchback operation in the seed deposition chamber prior to depositing the seed layer. The etch step removes barrier layer overhang and/or oxide that has formed on the barrier layer. It some embodiments, a small deposition flux of seed atoms accompanies the sputter etch flux of argon ions, embedding metal atoms into the barrier layer. The embedded metal atoms create nucleation sites for subsequent seed layer deposition, thereby promoting continuous seed layer film growth, film stability and improved seed layer-barrier layer adhesion.Type: GrantFiled: June 22, 2006Date of Patent: January 12, 2010Assignee: Novellus Systems, Inc.Inventors: Alexander Dulkin, Anil Vijayendran, Tom Yu, Daniel R. Juliano
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Patent number: 7642570Abstract: A rescue structure to repair an open wire includes a first metal layer having at least a rescue line, an isolation layer formed on the first metal layer, and a second metal layer formed on the isolation layer. The second metal layer has at least a signal line crossing the rescue line to form an enlarged intersection node. The intersection node is particularly arranged far from the side where the rescue line is used for signal transmission.Type: GrantFiled: December 4, 2006Date of Patent: January 5, 2010Assignee: AU Optronics Corp.Inventors: Chu-Yu Liu, Shyh-Feng Chen, Wen-Bin Chen
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Patent number: 7633136Abstract: A semiconductor device includes an interlayer insulating film on a substrate. A runner part includes a plurality of runner lines spaced apart from each other by a regular interval under the interlayer insulating film. A fuse cut part includes a plurality of fuse lines spaced apart from each other by a wider interval than the interval between the runner lines. A via in the interlayer insulating film connects a fuse line and a runner line to each other.Type: GrantFiled: December 6, 2006Date of Patent: December 15, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Man-Jong Yu
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Patent number: 7629234Abstract: A method is used in processing structures on or within a semiconductor substrate using N series of laser pulses to obtain a throughput benefit, wherein N?2. The structures are arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction. The N series of laser pulses propagate along N respective beam axes until incident upon selected structures in N respective distinct rows. The method determines a joint velocity profile for simultaneously moving in the lengthwise direction the N laser beam axes substantially in unison relative to the semiconductor substrate so as to process structures in the N rows with the respective N series of laser pulses, whereby the joint velocity profile is such that the throughput benefit is achieved while ensuring that the joint velocity profile represents feasible velocities for each of the N series of laser pulses and for each of the respective N rows of structures processed with the N series of laser pulses.Type: GrantFiled: February 4, 2005Date of Patent: December 8, 2009Assignee: Electro Scientific Industries, Inc.Inventor: Kelly J. Bruland
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Publication number: 20090294901Abstract: A fuse structure for an integrated circuit device includes an elongated metal interconnect layer defined within an insulating layer; a metal cap layer formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer formed on both the metal cap layer and the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer.Type: ApplicationFiled: June 3, 2008Publication date: December 3, 2009Applicant: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Jeffrey P. Gambino, Stephan Grunow, Chao-Kun Hu, Sujatha Sankaran, Andrew H. Simon, Theodorus E. Standaert
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Publication number: 20090278229Abstract: A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer.Type: ApplicationFiled: May 12, 2008Publication date: November 12, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Lynne M. Gignac, Chao-Kun Hu
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Publication number: 20090273414Abstract: A filter assembly includes an electrically conductive input member, an electrically conductive output member, and filter elements. Each filter element includes a connection disposed in an open or closed configuration, and a band filter, which may be a band-pass filter or a band-stop filter. A generic filter assembly is first manufactured having all connections in their open or closed configurations. A channel-selective filter assembly is then further manufactured by structural modification of one or more of the connections. Each connection of the channel-selective filter assembly is in its open or closed configuration independently of each other connection of each other filter element. Each frequency channel in a cable television (CATV) network, for example, is restricted or permitted by the channel-selective filter assembly.Type: ApplicationFiled: April 30, 2008Publication date: November 5, 2009Inventors: Ahmet Burak Olcen, Erdogan Alkan
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Publication number: 20090267180Abstract: A semiconductor device that has a reduced fuse thickness without compromising the bondability of an associated pad and a method for manufacturing the same is described. The semiconductor device includes a pad and a fuse formed on a planar level. The pad and fuse are formed using a metal according to the metal used for the planar level on which the pad and fuse are formed. The pad is formed such that the center portion of the pad is positioned lower than that of the fuse. During the opening of the pad, the thickness of the fuse is reduced without reducing the thickness of the pad. A subsequent repair process can then be easily performed on the fuse having the reduced thickness without degrading the bondability of the pad.Type: ApplicationFiled: October 3, 2008Publication date: October 29, 2009Inventor: Jun Ki KIM
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Patent number: 7601564Abstract: A semiconductor device includes an anti-fuse portion and a memory cell portion each including a MOSFET structure having a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film; wherein a depletion ratio in the gate electrode of the anti-fuse portion is different from the depletion ratio in the gate electrode of the memory cell portion, and the depletion ratio in the gate electrode of the anti-fuse portion is lower than the depletion ratio in the gate electrode of the memory cell portion.Type: GrantFiled: August 31, 2007Date of Patent: October 13, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Yasunori Okayama
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Patent number: 7579266Abstract: When the film thickness of an insulating film on a fuse connected to a circuit is not uniform within a wafer surface, there was a problem that disconnection of the fuse might become insufficient due to the insufficient intensity of a laser or disconnection of even an adjacent fuse due to excessive laser irradiation might occur. Further, a problem also occurred that after disconnection of the fuse, moisture entered from exterior through the region in which the fuse has been disconnected, so that the quality of a film underlying the fuse was adversely affected. After a SiON film, a SiN film, and a SiO2 film have been formed to cover the fuse in this stated order, etching is performed to the SiN film, which is an etching stopper film. The SiON film having a uniform and desired film thickness is thereby formed on the fuse.Type: GrantFiled: November 30, 2007Date of Patent: August 25, 2009Assignee: NEC Electronics CorporationInventor: Takashi Sakoh
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Publication number: 20090206381Abstract: An anti-fuse includes a gate dielectric layer formed over a substrate, a gate electrode including a body portion and a plurality of protruding portions extending from the body portion, wherein the body portion and the protruding portions are formed to contact on the gate dielectric layer, and a junction region formed in a portion of the substrate exposed by sidewalls of the protruding portions.Type: ApplicationFiled: February 12, 2009Publication date: August 20, 2009Inventors: Chang-Hee Shin, Ki-Seok Cho, Seong-Do Jeon
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Patent number: 7576014Abstract: A semiconductor device with a fuse 3a to be cut for a circuit modification, of which passivation film coating the uppermost wiring layer is formed in a two-layer structure including a first insulating film 11 with high filling capability and a second insulating film 12 blocking penetration of moisture or impurities. An opening 21 formed in a specific depth through the insulating films on the fuse 3a is coated by a third insulating film 13 with the blocking capability. This prevents the penetration of moisture or impurities, and the corrosion of the fuse 3a.Type: GrantFiled: November 22, 2005Date of Patent: August 18, 2009Assignee: Panasonic CorporationInventors: Takashi Miyake, Hiroyuki Doi
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Patent number: 7569429Abstract: Disclosed are an antifuse having a uniform amorphous silicon (antifuse material) thickness and a method for fabricating such an antifuse device. The antifuse is located between overlying and underlying conductive layers, and includes: a contact and/or via hole in an insulating layer on the underlying conductive layer; a lower metal layer contacting inner surfaces of the contact and/or via hole and a top surface of the insulating layer; a filling layer contacting the lower barrier metal layer and at least partially filling the contact and/or via hole; an antifuse material layer contacting a top surface of the filling layer and a part of the lower metal layer; and an upper metal layer on the antifuse material layer.Type: GrantFiled: December 29, 2005Date of Patent: August 4, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Keun Soo Park
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Patent number: 7569467Abstract: A semiconductor device has a multi-layer wiring in which resistance against migration of the semiconductor device is raised to improve the yield. Semiconductor device 100 includes a first interconnect (wiring) 112, formed in a first interlayer insulating film 106 on a semiconductor substrate, not shown, a via 128 provided on the first interconnect (wiring) 112 so that the via is connected to the first interconnect (wiring) 112, and a different element containing electrically conductive film 114. The different element containing electrically conductive film is formed selectively on a site on the top of the first interconnect (wiring) 112 where the first wiring is contacted with the bottom of the via 128. The different element containing electrically conductive film contains a metal of a main component of the first interconnect (wiring) 112 and a different element different from the metal of the main component.Type: GrantFiled: October 6, 2006Date of Patent: August 4, 2009Assignee: NEC Electronics CorporationInventor: Hiroaki Katou
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Patent number: 7566952Abstract: Shielded circuit pad is provided where the parasitic capacitance is tuned out by the inclusion of a shunt transmission line stub which reduces the substrate induced loss in millimeter-wave applications. The circuit pad is located on the substrate, with a shield located beneath the circuit pad, and the shunt transmission line stub attached to the circuit pad. Accordingly, controlled impedance is obtained for millimeter-wave applications. The spacing between the circuit pad and the shield may then be minimized.Type: GrantFiled: January 5, 2005Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: Brian A. Floyd, Ullrich R. Pfeiffer, Scott K. Reynods
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Publication number: 20090179301Abstract: A fuse includes a main fuse region and a plurality of cutting regions extend from the main fuse region.Type: ApplicationFiled: December 30, 2008Publication date: July 16, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Keun Soo Song
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Patent number: 7557030Abstract: A method for fabricating a recess gate in a semiconductor device is provided. The method includes selectively etching an active region of a substrate to form a recess pattern, performing a post treatment on the recess pattern using a plasma, and forming a gate pattern in the recess pattern.Type: GrantFiled: November 8, 2006Date of Patent: July 7, 2009Assignee: Hynix Semiconductor Inc.Inventors: Seung-Bum Kim, Ki-Won Nam
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Patent number: 7556989Abstract: A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.Type: GrantFiled: March 22, 2006Date of Patent: July 7, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Tai-Heui Cho, Kun-Gu Lee
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Publication number: 20090141533Abstract: A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.Type: ApplicationFiled: November 29, 2007Publication date: June 4, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Deok-kee Kim, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran, Kenneth J. Stein
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Patent number: 7537969Abstract: A fuse structure (100) suitable for incorporation in an integrated circuit presents a reduced thermal conduction footprint to the substrate (103). A patterned material stack (102) is formed on a substrate (103) and at least a portion of a material disposed between the substrate (103) and an upper portion of the fuse structure (100) is selectively etched so as to reduce the thermal conduction pathway between the upper portion and the substrate (103). In a further aspect of the present invention, the reduced cross-section of the fuse structure (100) has an increased current density resulting in a lower amount of current being needed to program the fuse.Type: GrantFiled: September 18, 2004Date of Patent: May 26, 2009Assignee: NXP B.V.Inventors: Piebe Zijstra, Ann Killian
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Patent number: 7529147Abstract: The semiconductor device has a semiconductor substrate; an electric fuse provided on the semiconductor substrate, and having a first fuse link and a second fuse link connected in series; and a terminal provided between the first fuse link and the second fuse link, wherein the first fuse link and the second fuse link are configured as being different from each other in current value necessary for blowing.Type: GrantFiled: November 2, 2006Date of Patent: May 5, 2009Assignee: NEC Electronics CorporationInventor: Takehiro Ueda
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Publication number: 20090103389Abstract: Disclosed is a semiconductor memory device including a plurality of banks, a plurality of data input/output terminals, control signal terminals, address signal terminals, and at least one or a plurality of virtual chips, each of which has the banks grouped together, thereby being operable as one independent chip. Each of the data input/output terminals are allocated in dedicated manner to the one virtual chip or one of the plurality of virtual chips. The control signal terminals and the address signal terminals are shared among the one or the plurality of virtual chips.Type: ApplicationFiled: October 16, 2008Publication date: April 23, 2009Applicant: Elpida Memory, Inc.Inventor: Kazuhiko Kajigaya
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Patent number: 7517763Abstract: In a semiconductor device and a method of fabricating the same, a fuse and a capacitor are formed at a same level on a semiconductor substrate having a fuse area and a capacitor area. The fuse is placed on the fuse area, and a lower plate is placed on the capacitor area. The lower plate is located on a same plane as the fuse. Further, an upper plate is located above the lower plate, and a capping layer is interposed between the lower plate and the upper plate. Therefore, the fuse and the capacitor can be formed at the same time, thereby minimizing photolithography and etch process steps.Type: GrantFiled: May 30, 2007Date of Patent: April 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Han Park, Ki-Young Lee
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Patent number: 7510914Abstract: Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.Type: GrantFiled: June 7, 2006Date of Patent: March 31, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Chul Yoon, Jong-Kyu Kim, Jang-Bin Yim, Sang-Dong Kwon, Sung-Gil Choi
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Publication number: 20090039480Abstract: The semiconductor device includes a fuse structure disposed on a substrate. An interlayer dielectric disposed on the fuse structure. A first contact plug, a second contact plug, and a third contact plug penetrate the interlayer dielectric and wherein each of the first contact plug, the second contact plug and the third contact plug are connected to the fuse structure. A first conductive pattern and a second conductive pattern are disposed on the interlayer dielectric. The first conductive pattern and the second conductive pattern are electrically connected to the first contact plug and second contact plug, respectively.Type: ApplicationFiled: August 6, 2008Publication date: February 12, 2009Inventors: KYOUNG-WOO LEE, Andrew Tae Kim, Hong-Jae Shin
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Patent number: 7485576Abstract: A method of forming a conductive pattern in which the conductive pattern can be easily formed at a low temperature without a photolithography process by forming the conductive pattern using a laser ablation method and an inkjet method, an organic thin film transistor manufactured using the method, and a method of manufacturing the organic thin film transistor. The method of forming a conductive pattern in a flat panel display device includes preparing a base member, forming a groove having the same shape as the conductive pattern in the base member, and forming the conductive pattern by applying a conductive material into the groove. The base member has one of a structure including a plastic substrate having the groove and a structure including a substrate and an insulating layer which is arranged on the substrate and which has the groove.Type: GrantFiled: December 8, 2005Date of Patent: February 3, 2009Assignees: Samsung SDI Co., Ltd., Samsung SDI Germany GmbHInventors: Min-Chul Suh, Jae-Bon Koo, Taek Ahn, Hye-Dong Kim, Fischer Joerg, Werner Humbs
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Publication number: 20090026575Abstract: Provided are a semiconductor device which substantially prevents repair failure and a method of manufacturing the same. The semiconductor device includes a plurality of first fuses formed apart from each other on a semiconductor substrate, and on which a protective layer is formed; a first insulating layer filled in between the first fuses and configured to expose the protective layer; a plurality of second fuses formed between the first fuses and on the first insulating layer; and a second insulating layer formed on the first insulating layer, wherein the second insulating layer includes a fuse window configured to fully expose the second fuses and the protective layer formed on the first fuses.Type: ApplicationFiled: October 1, 2008Publication date: January 29, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Bo-sung Kim
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Publication number: 20090026570Abstract: Methods and structures for discharging plasma formed during the fabrication of semiconductor device are disclosed. The semiconductor device includes a wordline, a common ground line and a fuse structure for electrically coupling the wordline and the common ground line until a break signal is applied via the fuse structure.Type: ApplicationFiled: December 20, 2007Publication date: January 29, 2009Inventors: Masahiko Higashi, Naoki Takeguchi