Using Laser, E.g., Laser Cutting, Laser Direct Writing, Laser Repair (epo) Patents (Class 257/E21.596)
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Patent number: 9634179Abstract: A method and resulting structure of patterning a metal film pattern over a substrate, including forming a metal film pattern over the substrate; depositing a coating over the substrate surface and the metal film pattern; and removing the coating over the metal film pattern by laser irradiation. The substrate and coating do not significantly interact with the laser irradiation, and the laser irradiation interacts with the metal film pattern and the coating, resulting in the removal of the coating over the metal film pattern. The invention offers a technique for the formation of a metal pattern surrounded by a dielectric coating for solar cells, where the dielectric coating may function as an antireflection coating on the front surface, internal reflector on the rear surface, and may further may function as a dielectric barrier for subsequent electroplating of metal patterns on either surface.Type: GrantFiled: January 23, 2013Date of Patent: April 25, 2017Assignee: TETRASUN, INC.Inventors: Adrian Bruce Turner, Qing Yuan Ong, Oliver Schultz-Wittmann
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Patent number: 9040389Abstract: In one embodiment, a method of forming a semiconductor device comprises forming a groove on and/or over a first side of a substrate. A dicing layer is formed from a second side of the substrate using a laser process. The second side is opposite the first side. The dicing layer is disposed under the groove within the substrate. The substrate is singulated through the dicing layer.Type: GrantFiled: October 9, 2012Date of Patent: May 26, 2015Assignee: Infineon Technologies AGInventors: Gunther Mackh, Maria Heidenblut, Adolf Koller, Anatoly Sotnikov
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Patent number: 9034733Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.Type: GrantFiled: January 21, 2014Date of Patent: May 19, 2015Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
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Patent number: 8969220Abstract: Examples of methods and systems for laser processing of materials are disclosed. Methods and systems for singulation of a wafer comprising a coated substrate can utilize a laser outputting light that has a wavelength that is transparent to the wafer substrate but which may not be transparent to the coating layer(s). Using techniques for managing fluence and focal condition of the laser beam, the coating layer(s) and the substrate material can be processed through ablation and internal modification, respectively. The internal modification can result in die separation.Type: GrantFiled: December 14, 2012Date of Patent: March 3, 2015Assignee: IMRA America, Inc.Inventors: Alan Y. Arai, Gyu Cheon Cho, Jingzhou Xu
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Patent number: 8927395Abstract: In a wafer processing method, a modified layer is formed inside a wafer along planned dividing lines by irradiating the wafer with a laser beam with such a wavelength as to be transmitted through the wafer from the back surface side of the wafer along the dividing lines. A first modified layer is formed near the back surface of the wafer by irradiating the wafer with the light focal point of the laser beam positioned near the back surface of the wafer. The wafer is then irradiated with the light focal point of the laser beam positioned on the front surface side. Then plural second modified layers are formed in a multi-layering manner with sequential movement of the light focal point toward an area leading to the first modified layer. The wafer is divided into individual devices along the dividing lines by applying an external force to the wafer.Type: GrantFiled: March 12, 2014Date of Patent: January 6, 2015Assignee: Disco CorporationInventor: Masaru Nakamura
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Patent number: 8841170Abstract: A method of singulating semiconductor devices in the close proximity to active structures by controlling interface charge of semiconductor device sidewalls is provided that includes forming a scribe on a surface of a semiconductor devices, where the scribe is within 5 degrees of a crystal lattice direction of the semiconductor device, cleaving the semiconductor device along the scribe, where the devices are separated, using a coating process to coat the sidewalls of the cleaved semiconductor device with a passivation material, where the passivation material is disposed to provide a fixed charge density at a semiconductor interface of the sidewalls, and where the fixed charge density interacts with charge carriers in the bulk of the material.Type: GrantFiled: October 21, 2011Date of Patent: September 23, 2014Assignees: The Regents of the University of California, Naval Research LaboratoryInventors: Vitaliy Fadeyev, Hartmut F. W. Sadrozinski, Marc Christophersen, Bernard F. Phlips
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Patent number: 8828891Abstract: For modulating laser light for forming a modified region SD3 at an intermediate position between a position closer to a rear face 21 and a position closer to a front face 3 with respect to an object 1, a quality pattern J having a first brightness region extending in a direction substantially orthogonal to a line 5 and second brightness regions located on both sides of the first brightness region in the extending direction of the line 5 is used. After forming modified regions SD1, SD2 at positions closer to the rear face 21 but before forming modified regions SD4, SD5 at positions closer to the rear face 21 while using the front face 3 as a laser light entrance surface, the modified region SD3 is formed at the intermediate position by irradiation with laser light modulated according to a modulation pattern including the quality pattern J.Type: GrantFiled: January 5, 2011Date of Patent: September 9, 2014Assignee: Hamamatsu Photonics K.K.Inventor: Takeshi Sakamoto
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Patent number: 8785813Abstract: Various embodiments may be used for laser-based modification of target material of a workpiece while advantageously achieving improvements in processing throughput and/or quality. Embodiments of a method of processing may include focusing and directing laser pulses to a region of the workpiece at a pulse repetition rate sufficiently high so that material is efficiently removed from the region and a quantity of unwanted material within the region, proximate to the region, or both is reduced relative to a quantity obtainable at a lower repetition rate. Embodiments of an ultrashort pulse laser system may include a fiber amplifier or fiber laser. Various embodiments are suitable for at least one of dicing, cutting, scribing, and forming features on or within a semiconductor substrate. Workpiece materials may include metals, inorganic or organic dielectrics, or any material to be micromachined with femtosecond, picosecond, and/or nanosecond pulses.Type: GrantFiled: March 15, 2012Date of Patent: July 22, 2014Assignee: IMRA America, Inc.Inventors: Lawrence Shah, Gyu Cheon Cho, Jingzhou Xu
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Patent number: 8765525Abstract: A method of manufacture of an integrated packaging system includes: providing a substrate; mounting an integrated circuit on the substrate; mounting an interposer substrate having an interposer pad on the integrated circuit; covering an encapsulant over the integrated circuit and the interposer substrate; forming a hole through the encapsulant aligned over the interposer pad; and placing a conductive connector on and in direct contact with the interposer pad.Type: GrantFiled: June 16, 2011Date of Patent: July 1, 2014Assignee: STATS ChipPAC Ltd.Inventors: In Sang Yoon, DeokKyung Yang, Sungmin Song
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Patent number: 8753923Abstract: A wafer processing method of dividing a wafer along streets. The wafer processing method includes a protective tape attaching step of attaching a protective tape to the front side of the wafer, a modified layer forming step of holding the wafer through the protective tape on a chuck table of a laser processing apparatus under suction and next applying a laser beam having a transmission wavelength to the wafer from the back side of the wafer along the streets, thereby forming a modified layer inside the wafer along each street, and a wafer dividing step of canceling suction holding of the wafer by the chuck table and next applying an air pressure to the wafer now placed on the holding surface in the condition where horizontal movement of the wafer is limited, thereby dividing the wafer along each street where the modified layer is formed, thus obtaining individual devices.Type: GrantFiled: March 7, 2013Date of Patent: June 17, 2014Assignee: Disco CorporationInventors: Satoshi Kobayashi, Jinyan Zhao
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Patent number: 8728910Abstract: To provide an olefinic expandable substrate and a dicing film that exhibits less contamination characteristics, high expandability without necking, which cannot be achieved by conventional olefinic expandable substrates. In order to achieve the object, an expandable film comprises a 1-butene-?-olefin copolymer (A) having a tensile modulus at 23° C. of 100 to 500 MPa and a propylenic elastomer composition (B) comprising a propylene-?-olefin copolymer (b1) and having a tensile modulus at 23° C. of 10 to 50 MPa, wherein the amount of the component (B) is 30 to 70 weight parts relative to 100 weight parts in total of components (A) and (B).Type: GrantFiled: September 28, 2011Date of Patent: May 20, 2014Assignee: Mitsui Chemicals, Inc.Inventors: Eiji Hayashishita, Katsutoshi Ozaki, Mitsuru Sakai, Setsuko Oike
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Patent number: 8685834Abstract: A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the electrode, a conductive material electrically connecting the electrode and terminal, and an encapsulant covering the terminal, conductive material, and electrode, but exposing the cover plate overlying the center region of the chip.Type: GrantFiled: November 6, 2009Date of Patent: April 1, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pei-Haw Tsao, Chender Huang, Chuen-Jye Lin
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Patent number: 8664089Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and fluid machining the semiconductor wafer to remove the backmetal layer from the singulation lines.Type: GrantFiled: August 20, 2012Date of Patent: March 4, 2014Assignee: Semiconductor Components Industries, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder
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Patent number: 8617964Abstract: A laser processing method for preventing particles from occurring from cut sections of chips obtained by cutting a silicon wafer is provided. An irradiation condition of laser light L for forming modified regions 77 to 712 is made different from an irradiation condition of laser light L for forming the modified regions 713 to 719 such as to correct the spherical aberration of laser light L in areas where the depth from the front face 3 of a silicon wafer 11 is 335 ?m to 525 ?m. Therefore, even when the silicon wafer 11 and a functional device layer 16 are cut into semiconductor chips from modified regions 71 to 719 acting as a cutting start point, twist hackles do not appear remarkably in the areas where the depth is 335 ?m to 525 ?m, whereby particles are hard to occur.Type: GrantFiled: December 1, 2011Date of Patent: December 31, 2013Assignee: Hamamatsu Photonics K.K.Inventors: Takeshi Sakamoto, Kenichi Muramatsu
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Patent number: 8564026Abstract: In various embodiments, a chip may include a substrate; a coating, the coating covering the substrate at least partially and the coating being designed for being stripped at least partially by means of laser ablation; wherein between the substrate and the coating, a laser detector layer is arranged at least partially, the laser detector layer being designed for generating a detector signal for ending the laser ablation.Type: GrantFiled: September 29, 2011Date of Patent: October 22, 2013Assignee: Infineon Technologies AGInventor: Franz-Peter Kalz
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Patent number: 8549733Abstract: A transducer and method of forming a transducer is disclosed. The method comprises locating a feed wire for forming a drive pin on a reed surface, welding a first end of the feed wire to the reed, cutting the feed wire to form a drive pin, and securing the drive pin to a paddle. The first end of the feed wire can be welded to the reed by a laser welding operation. The laser melts the reed to form a molten reed material, and the feed wire is pushed through the molten reed material to form a weld between the feed wire and the reed, once the molten reed material solidifies. The wire coil is then cut with a second laser to form the drive pin. The drive pin is then adhered to a paddle with an adhesive.Type: GrantFiled: July 9, 2010Date of Patent: October 8, 2013Assignee: Shure Acquisition Holdings, Inc.Inventors: Kevin M. Bedwell, Lajos Frohlich
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Patent number: 8536025Abstract: A resized wafer using a negative photoresist ring, methods of manufacture and design structures thereof are disclosed. The method includes forming a ring within a radius of a wafer. The method also includes patterning a photoresist formed on the wafer, by exposing the photoresist to energy. Additionally, the method includes forming troughs in a substrate of the wafer based on the patterning of the photoresist, wherein the ring blocks formation of the troughs underneath the ring. The method also includes filling the troughs with a metal and resizing the wafer at an area of the ring.Type: GrantFiled: December 12, 2011Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: Dennis P. Hogan, Gregory S. Jankowski, Robert K. Leidy
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Patent number: 8482018Abstract: Disclosed is a light emitting device. The light emitting device comprises a light emitting semiconductor layer comprising a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, a second electrode layer supporting the light emitting semiconductor layer while surrounding the light emitting semiconductor layer, and a first passivation layer between a side of the light emitting semiconductor layer and the second electrode layer.Type: GrantFiled: October 2, 2008Date of Patent: July 9, 2013Assignee: LG Innotek Co., Ltd.Inventors: Bong Cheol Kang, Duk Kyu Bae
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Patent number: 8461020Abstract: In a device processing method, a laser beam is applied to a wafer along division lines from the back side of the wafer, thereby forming a division start point inside the wafer along the division lines at a depth not reaching the finished thickness of each device. A protective member is attached to the front side of the wafer before or after performing the division start points are formed. An external force is applied through the protective member to the wafer, thereby dividing the wafer along the division lines to obtain the individual devices. The back side of the wafer is ground to remove the modified layers, and a silicon nitride film is formed on at least the side surface of each device. The silicon nitride film has a gettering effect and is formed on the side surface of each device, which surface is formed by a cleavage plane.Type: GrantFiled: April 19, 2012Date of Patent: June 11, 2013Assignee: Disco CorporationInventors: Seiji Harada, Yoshikazu Kobayashi
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Patent number: 8455332Abstract: A method of manufacturing a light-emitting device using laser scribing to improve overall light output is disclosed. Upon placing a semiconductor wafer having light emitting diode (“LED”) devices separated by streets on a wafer chuck, the process arranges a first surface of semiconductor wafer containing front sides of the LED devices facing up and a second surface of semiconductor wafer containing back sides of the LED devices facing toward the wafer chuck. After aligning a laser device over the first surface of the semiconductor wafer above a street, the process is configured to focus a high intensity portion of a laser beam generated by the laser device at a location in a substrate closer to the back sides of the LED devices.Type: GrantFiled: May 1, 2009Date of Patent: June 4, 2013Assignee: Bridgelux, Inc.Inventors: Norihito Hamaguchi, Ghulam Hasnain
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Method of dividing a semiconductor wafer having semiconductor and metal layers into separate devices
Patent number: 8445361Abstract: A method of dividing a semiconductor wafer having a metal layer includes removing all or substantially all of the semiconductor material in scribe streets while the wafer is supported by a support, turning over the wafer and while using a second support to support the wafer, introducing a heat energy flux into the metal layer to remove metal of the metal layer from the scribe streets.Type: GrantFiled: September 28, 2011Date of Patent: May 21, 2013Inventor: Paul C. Lindsey, Jr. -
Patent number: 8435869Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor laminated structure on a substrate as a wafer including semiconductor laser structures; forming a first groove between the semiconductor laser structures on a major surface of the wafer; separating the wafer to laser bars including at least two of the semiconductor laser structures arrayed in a bar shape, after forming the first groove; forming a second groove in the first groove of the laser bars, the second groove having a width no wider than the first groove; and separating one of the laser bars into respective semiconductor lasers along the second groove.Type: GrantFiled: August 25, 2010Date of Patent: May 7, 2013Assignee: Mitsubishi Electric CorporationInventors: Misao Hironaka, Harumi Nishiguchi, Kyosuke Kuramoto, Masatsugu Kusunoki
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Patent number: 8431467Abstract: An object to be processed is restrained from warping at the time of laser processing. A modified region M2 is formed within a wafer 11, and fractures a2, b2 extending in directions parallel to the thickness direction of the wafer 11 and tilted with respect to a plane including lines 5 are generated from the modified region M2. A modified region M3 is formed within the wafer 11, and a fracture a3 extending in a direction parallel to the thickness direction of the wafer 11 and tilted with respect to the plane including the lines 5 is generated from the modified region M3 so as to connect with the fracture b2. That is, the fractures a2, a3, b2 are generated so as to be connected together.Type: GrantFiled: August 19, 2011Date of Patent: April 30, 2013Assignee: Hamamatsu Photonics K.K.Inventor: Takeshi Sakamoto
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Patent number: 8415232Abstract: A wafer is divided into individual devices along division lines formed on the front side of the wafer. The devices are respectively formed in a plurality of regions partitioned by the division lines. A protective member is provided on the front of the wafer, and the back of the wafer is ground to a predetermined thickness. A laser beam is applied to the wafer from the back side of the wafer along the division lines with the focal point of the laser beam set inside the wafer at a position corresponding to each division line, thereby forming a plurality of modified layers inside the wafer along the division lines. The wafer is divided along the modified layers into the individual devices, and the back side of the wafer is ground to remove the modified layers and reduce the thickness of each device to the finished thickness.Type: GrantFiled: October 20, 2011Date of Patent: April 9, 2013Assignee: Disco CorporationInventors: Keiichi Kajiyama, Takatoshi Masuda
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Patent number: 8378252Abstract: A method and apparatus is presented for obtaining high resolution positional feedback from motion stages 52 in indexing systems 10 without incurring the costs associated with providing high resolution positional feedback from the entire range of motion by combining low resolution/low cost feedback devices 72 with high resolution/high cost feedback devices 74, 76, 78, 80, 82, 84, 86, 88.Type: GrantFiled: May 27, 2010Date of Patent: February 19, 2013Assignee: Electro Scientific Industries, Inc.Inventor: Mehmet Ermin Alpay
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Patent number: 8349700Abstract: A method for manufacturing a semiconductor device 1, comprising a first step of providing a photosensitive adhesive (insulating resin layer 7) on a board 3 which has a connecting terminal, a second step of patterning the photosensitive adhesive by light exposure and development so that openings 13 are formed where the connecting terminal is exposed, a third step of filling the openings 13 with a conductive material to form a conductive layer 9, and a fourth step of directly bonding a semiconductor chip 5 having a connecting electrode section to the photosensitive adhesive while electrically connecting the connecting terminal of the board 3 and the connecting electrode section of the semiconductor chip 5 via the conductive layer 9.Type: GrantFiled: December 2, 2008Date of Patent: January 8, 2013Assignee: Hitachi Chemical Company, Ltd.Inventors: Takashi Masuko, Takashi Kawamori, Kazuyuki Mitsukura, Shigeki Katogi
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Patent number: 8349673Abstract: A method of producing a plurality of transistors each including a source/drain electrode pair comprising a conductor material and a channel comprising semiconductor material between the source and drain electrodes of said source/drain electrode pair; the method comprising (i) forming over a substrate at least a first layer of said conductor material or a precursor thereto and a second layer of said semiconductor material or a precursor thereto; and (ii) thereafter removing selected portions of at least said first and second layers so as to define at least two adjacent source/drain electrode pairs that are unconnected to each other within said first and second layers.Type: GrantFiled: April 3, 2006Date of Patent: January 8, 2013Assignee: Plastic Logic LimitedInventors: Paul A. Cain, Carl Hayton, Anoop Menon, Thomas M. Brown
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Patent number: 8334169Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit having an active side and a non-active side; forming a channel through the integrated circuit; forming an indent, having a flange and an indent side, from a peripheral region of the non-active side; and forming a conformal interconnect, having an offset segment, a sloped segment, and a flange segment, under the indent.Type: GrantFiled: April 27, 2011Date of Patent: December 18, 2012Assignee: Stats Chippac Ltd.Inventors: Reza Argenty Pagaila, Byung Tai Do, Linda Pei Ee Chua
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Patent number: 8324636Abstract: A method of manufacturing a light-emitting device using laser scribing to improve overall light output is disclosed. Upon placing a semiconductor wafer having light emitting diode (“LED”) devices separated by streets on a wafer chuck, the process arranges a first surface of semiconductor wafer containing front sides of the LED devices facing up and a second surface of semiconductor wafer containing back sides of the LED devices facing toward the wafer chuck. After aligning a laser device over the first surface of the semiconductor wafer above a street, the process is configured to focus a high intensity portion of a laser beam generated by the laser device at a location in a substrate closer to the back sides of the LED devices.Type: GrantFiled: October 18, 2010Date of Patent: December 4, 2012Assignee: Bridgelux, Inc.Inventors: Norihito Hamaguchi, Ghulam Hasnain
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Patent number: 8318536Abstract: A method, comprises drilling a set of one or more microvias in a semiconductor package with an aperture, wherein drilling the set of microvias comprises to use an aperture that has a phase shift region to reduce a spot size of a drilling beam that is used to form the set of microvias.Type: GrantFiled: December 31, 2007Date of Patent: November 27, 2012Assignee: Intel CorporationInventor: Yonggang Li
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Patent number: 8227977Abstract: A structure for repairing a line defect in which a short can be easily repaired using an adjacent wiring line despite limited repairing space and a method of repairing the defect are disclosed.Type: GrantFiled: August 13, 2009Date of Patent: July 24, 2012Assignee: Samsung Mobile Display Co., Ltd.Inventors: Zail Lhee, Keun Kim, Jin-Gyu Kang
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Patent number: 8211749Abstract: An integrated circuit packaging system is provided including forming a first device wafer having a first backside and a first active side; forming a waferscale spacer wafer having a waferscale spacer and a first opening; mounting the waferscale spacer wafer on the first backside; and singulating an first integrated circuit die having the waferscale spacer from the first device wafer having the first backside with the waferscale spacer wafer thereon.Type: GrantFiled: August 18, 2006Date of Patent: July 3, 2012Assignee: STATS ChipPAC Ltd.Inventors: Sang-Ho Lee, Jong-Woo Ha, Soo-San Park
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Patent number: 8178425Abstract: An optical device wafer processing method for dividing an optical device wafer into a plurality of individual optical devices. The optical device wafer is composed of a substrate and a semiconductor layer formed on the front side of the substrate. The optical devices are partitioned by a plurality of crossing division lines formed on the semiconductor layer.Type: GrantFiled: January 21, 2011Date of Patent: May 15, 2012Assignee: Disco CorporationInventors: Tasuku Koyanagi, Hiroshi Morikazu
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Patent number: 8158490Abstract: A method for producing a Group III nitride-based compound semiconductor device includes, before bonding a support substrate to an epitaxial layer formed on an epitaxial growth substrate, forming trenches in such a manner as to extend from the top surface of a stacked structure including the epitaxial layer to at least the interface between the epitaxial growth substrate and the bottom surface of the epitaxial layer. The trenches divide the epitaxial layer into extended device areas which encompass respective product device structures, and stress relaxation areas. A plurality of laser irradiations are performed for laser lift-off such that, after each laser irradiation, the expanded device areas and the stress relaxation areas are formed by a laser-irradiated area and a laser-unirradiated area, and a strip-shaped laser-unirradiated stress relaxation area is formed at a boundary between the laser-irradiated area and the laser-unirradiated area.Type: GrantFiled: March 30, 2010Date of Patent: April 17, 2012Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Umemura, Masahiro Ohashi
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Patent number: 8158493Abstract: Various embodiments may be used for laser-based modification of target material of a workpiece while advantageously achieving improvements in processing throughput and/or quality. Embodiments of a method of processing may include focusing and directing laser pulses to a region of the workpiece at a pulse repetition rate sufficiently high so that material is efficiently removed from the region and a quantity of unwanted material within the region, proximate to the region, or both is reduced relative to a quantity obtainable at a lower repetition rate. Embodiments of an ultrashort pulse laser system may include at least one of a fiber amplifier or fiber laser. Various embodiments are suitable for at least one of dicing, cutting, scribing, and forming features on or within a semiconductor substrate. Workpiece materials may also include metals, inorganic or organic dielectrics, or any material to be micromachined with femtosecond, picosecond, and/or nanosecond pulses.Type: GrantFiled: December 17, 2009Date of Patent: April 17, 2012Assignee: IMRA America, Inc.Inventors: Lawrence Shah, Gyu Cheon Cho, Jingzhou Xu
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Patent number: 8153476Abstract: An electronic component includes a substrate, a functional element formed on the substrate, a plurality of terminals including a first terminal electrode connected to the functional element and a second terminal electrode layered on the first terminal electrode, and a feed line, one end of which is electrically connected to the first terminal electrode and the other end of which reaches an edge of the substrate, wherein the feed line includes a first portion directly reaching the edge, and a second portion branching from the first portion and then reaching the edge.Type: GrantFiled: March 4, 2011Date of Patent: April 10, 2012Assignee: Taiyo Yuden Co., Ltd.Inventors: Yasufumi Kaneda, Akira Moriya, Kaoru Sakinada, Shunichi Aikawa, Yoshinori Kondou, Takashi Yamashita
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Patent number: 8124454Abstract: Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non- (or low) thermally conductive and/or non- (or low) electrically conductive carrier substrate that has been removed.Type: GrantFiled: October 11, 2006Date of Patent: February 28, 2012Assignee: SemiLEDS Optoelectronics Co., Ltd.Inventors: Chen-Fu Chu, Trung Tri Doan, Chuong Anh Tran, Chao-Chen Cheng, Jiunn-Yi Chu, Wen-Huang Liu, Hao-Chun Cheng, Feng-Hsu Fan, Jui-Kang Yen
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Patent number: 8115191Abstract: A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation.Type: GrantFiled: August 14, 2009Date of Patent: February 14, 2012Assignee: International Business Machines CorporationInventors: Guy Cohen, Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw
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Patent number: 8043969Abstract: A first layer is formed over a substrate, a light absorbing layer is formed over the first layer, and a layer having a light-transmitting property is formed over the light absorbing layer. The light absorbing layer is selectively irradiated with a laser beam via the layer having a light-transmitting property. When the light absorbing layer absorbs energy of the laser beam, due to emission of gas that is within the light absorbing layer, or sublimation, evaporation, or the like of the light absorbing layer, a part of the light absorbing layer and a part of the layer having a light-transmitting property in contact with the light absorbing layer are removed. By using the remaining part of the layer having a light-transmitting property or the remaining part of the light absorbing layer as a mask and etching the first layer, the first layer can be processed into a desired shape.Type: GrantFiled: June 30, 2010Date of Patent: October 25, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Koichiro Tanaka, Hironobu Shoji, Shunpei Yamazaki
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Patent number: 8026154Abstract: An object to be processed is restrained from warping at the time of laser processing. A modified region M2 is formed within a wafer 11, and fractures a2, b2 extending in directions parallel to the thickness direction of the wafer 11 and tilted with respect to a plane including lines 5 are generated from the modified region M2. A modified region M3 is formed within the wafer 11, and a fracture a3 extending in a direction parallel to the thickness direction of the wafer 11 and tilted with respect to the plane including the lines 5 is generated from the modified region M3 so as to connect with the fracture b2. That is, the fractures a2, a3, b2 are generated so as to be connected together.Type: GrantFiled: June 6, 2007Date of Patent: September 27, 2011Assignee: Hamamatsu Photonics K.K.Inventor: Takeshi Sakamoto
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Patent number: 8026158Abstract: Systems and methods process structures on or within a semiconductor substrate using a series of laser pulses. In one embodiment, a deflector is configured to selectively deflect the laser pulses within a processing window. The processing window is scanned over the semiconductor substrate such that a plurality of laterally spaced rows of structures simultaneously pass through the processing window. As the processing window is scanned, the deflector selectively deflects the series of laser pulses among the laterally spaced rows within the processing window. Thus, multiple rows of structures may be processed in a single scan.Type: GrantFiled: June 1, 2007Date of Patent: September 27, 2011Assignee: Electro Scientific Industries, Inc.Inventors: Kelly J. Bruland, Mark A. Unrath, Douglas E. Holmgren
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Patent number: 8017521Abstract: A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer having a plurality of die. A trench is formed between the semiconductor die. The trench extending partially through the semiconductor wafer. The portion of the semiconductor wafer below the trench along a backside of the wafer maintaining structural support for the wafer during the processing steps of forming a plurality of conductive vias between the die, and forming traces to electrically connect the conductive vias to contact pads on the die. The portion of the semiconductor wafer below the trench along the backside of the wafer is removed. The semiconductor wafer is singulated to separate the die. The singulation can be performed through the conductive vias to make half conductive vias or between the conductive vias to make full conductive vias. The die can be stacked and electrically connected through the conductive vias.Type: GrantFiled: July 31, 2009Date of Patent: September 13, 2011Assignee: STATS ChipPAC, Ltd.Inventors: Byung Tai Do, Heap Hoe Kuan, Linda Pei Ee Chua
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Patent number: 7998840Abstract: A wafer laser processing method for forming deteriorated layers in the inside of a wafer having a device area and a peripheral excess area surrounding the device area, the surface of the device area being higher than the surface of the peripheral excess area, involving a first step for forming a deteriorated layer in the insides of the peripheral excess area and device area by applying a laser beam to the peripheral excess area and the device area with its focal point set in the material of the peripheral excess area and the device area from the front surface side of the wafer; and a second step for forming a deteriorated layer in the inside of the device area by applying a laser beam to the device area with its focal point set in the material of the device area without applying the laser beam to the peripheral excess area.Type: GrantFiled: May 19, 2009Date of Patent: August 16, 2011Assignee: Disco CorporationInventor: Yosuke Watanabe
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Patent number: 7993975Abstract: A semiconductor-device manufacturing method includes: forming terminals on a wafer and across each of dicing lines along which the wafer is cut into a plurality of semiconductor chips; preparing a plurality of pre-cut substrates each including a substrate body capable of being cut along corresponding one of cutting lines into a pair of same structured substrate pieces, connection pads provided on a top surface of the substrate body, and external terminals formed on a bottom surface of the substrate body and connected to the connection pads; mounting the pre-cut substrates onto the wafer while the cutting lines of the pre-cut substrates match the dicing lines; and simultaneously dicing the wafer and the pre-cut substrates along the dicing lines matching the cutting lines.Type: GrantFiled: December 18, 2008Date of Patent: August 9, 2011Assignee: Elpida Memory, Inc.Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe
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Patent number: 7989313Abstract: A process is disclosed for creating semiconductor devices such as RFID assemblies wherein an array of dies mounted to a substrate is spaced apart at a first pitch, and the substrate is removed after the positions of the dies in the array is fixed by a solidifiable substance. The solidifiable substance is then removed without changing the relative positions of the dies in the array. All or a selected portion of the array of dies is then electrically attached to a plurality of straps or interposers arranged in a corresponding array. The spacing, or pitch, between the dies in the die array may be changed before or after the substrate is removed to match the pitch of the straps or interposers in the corresponding array. An RFID device created using the process inventive is also disclosed.Type: GrantFiled: April 16, 2008Date of Patent: August 2, 2011Assignee: Avery Dennison CorporationInventors: Haochuan Wang, Ali Mehrabi, Kouroche Kian, Dave N. Edwards, Akiko Tanabe, Mark Licon, Jay Akhave
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Patent number: 7972903Abstract: An insulating film covering the lower surface of an external connection electrode of a semiconductor construct is formed. A mask metal layer in which there is formed an opening having a planar size smaller than that of the external connection electrode is formed on the insulating film. The mask metal layer is used as a mask to apply a laser beam to the insulating film, such that a connection opening reaching the external connection electrode is formed in the insulating film. A wiring line is formed on the insulating film in such a manner as to be connected to the external connection electrode via the connection opening.Type: GrantFiled: January 26, 2009Date of Patent: July 5, 2011Assignee: Casio Computer Co., Ltd.Inventor: Hiroyasu Jobetto
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Patent number: 7955906Abstract: A method and system for locally processing a predetermined microstructure formed on a substrate without causing undesirable changes in electrical or physical characteristics of the substrate or other structures formed on the substrate are provided. The method includes providing information based on a model of laser pulse interactions with the predetermined microstructure, the substrate and the other structures. At least one characteristic of at least one pulse is determined based on the information. A pulsed laser beam is generated including the at least one pulse. The method further includes irradiating the at least one pulse having the at least one determined characteristic into a spot on the predetermined microstructure. The at least one determined characteristic and other characteristics of the at least one pulse are sufficient to locally process the predetermined microstructure without causing the undesirable changes.Type: GrantFiled: July 1, 2008Date of Patent: June 7, 2011Assignee: GSI Group CorporationInventors: James J. Cordingley, Jonathan S. Ehrman, David M. Filgas, Shepard D. Johnson, Joohan Lee, Donald V. Smart, Donald J. Svetkoff
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Patent number: 7952176Abstract: A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming a channel through the integrated circuit; forming an indent, having a flange and an indent side, from a peripheral region of the non-active side; and forming a conformal interconnect, having an offset segment, a sloped segment, and a flange segment, under the indent.Type: GrantFiled: December 9, 2008Date of Patent: May 31, 2011Assignee: Stats Chippac Ltd.Inventors: Reza Argenty Pagaila, Byung Tai Do, Linda Pei Ee Chua
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Patent number: 7947574Abstract: A laser processing method is provided, which, even when a substrate formed with a laminate part including a plurality of functional devices is thick, can cut the substrate and laminate part with a high precision. This laser processing method irradiates a substrate 4 with laser light L while using a rear face 21 as a laser light entrance surface and locating a light-converging point P within the substrate 4, so as to form modified regions 71, 72, 73 within the substrate 4. Here, the quality modified region 71 is formed at a position where the distance between the front face 3 of the substrate 4 and the end part of the quality modified region 71 on the front face side is 5 ?m to 15 ?m. When the quality modified region 71 is formed at such a position, a laminate part 16 (constituted by interlayer insulating films 17a, 17b here) formed on the front face 3 of the substrate 4 is also cut along a line to cut with a high precision together with the substrate 4.Type: GrantFiled: March 26, 2010Date of Patent: May 24, 2011Assignee: Hamamatsu Photonics K.K.Inventors: Takeshi Sakamoto, Kenshi Fukumitsu
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Patent number: 7943518Abstract: A semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI is provided. A semiconductor substrate is provided with an element electrode having at least its surface constituted of an aluminum electrode. The surface of the aluminum electrode is roughened. An oxide film is provided on the aluminum electrode. A conductive film is provided on the oxide film. The aluminum electrode, oxide film and conductive film form a capacitor.Type: GrantFiled: August 24, 2007Date of Patent: May 17, 2011Assignee: Panasonic CorporationInventors: Koichi Hirano, Tetsuyoshi Ogura, Seiichi Nakatani