Abstract: The sensor assembly comprises a substrate (1), such as a flexible printed circuit board, and a sensor chip (2) flip-chip mounted to the substrate (1), with a first side (3) of the sensor chip (2) facing the substrate (1). A sensing area (4) and contact pads (5) are integrated on the first side (3) of the sensor chip (2). Underfill (18) and/or solder flux is arranged between the sensor chip (2) and the substrate (1). The sensor chip (2) extends over an edge (12) of the substrate (1), with the edge (12) of the substrate (1) extending between the contact pads (5) and the sensing area (4) over the whole sensor chip (2). A dam (16) can be provided along the edge (12) of the substrate (1) for even better separation of the underfill (18) and the sensing area (4). This de sign allows for a simple alignment of the sensor chip on the substrate (1) and prevents underfill (18) from covering the sensing area (4).

Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.

Abstract: A method of manufacturing a semiconductor package includes forming a protection layer on a support plate, stacking substrates on the protection layer, electrically connecting the substrates to each other, forming a molding layer on the support plate, and removing the support plate while the protection layer remains on the substrates. The stacked substrates are offset from adjacent substrates.

Abstract: Some embodiments herein relate to a transmitter. The transmitter includes an integrated circuit (IC) package including a first antenna configured to radiate a first electromagnetic signal therefrom. A printed circuit board (PCB) substrate includes a waveguide configured to receive the first electromagnetic signal and to generate a waveguide signal based thereon. A second antenna can be electrically coupled to the waveguide and can radiate a second electromagnetic signal that corresponds to the waveguide signal. Other devices and methods are also disclosed.

Abstract: A semiconductor mounting substrate according to the present invention comprises: a substrate; a semiconductor device, mounted on this substrate; solder bumps, which connect the semiconductor device and the substrate; a first resin, filled in a space between the semiconductor device and the substrate; and electronic components, mounted on a face side of the semiconductor device where the semiconductor device is mounted, wherein bond strength reinforcing resin section is provided at least between a side face in the vicinity of a corner part of the semiconductor device and a substrate surface of the substrate in a position corresponding to the corner part.

Abstract: A method of manufacturing a semiconductor wafer bonding product according to the present invention includes: a step of preparing a spacer formation film including a support base having a sheet-like shape and a spacer formation layer provided on the support base and having photosensitivity; a step of attaching the spacer formation layer to a semiconductor wafer having one surface from a side of the one surface; a step of forming a spacer by subjecting exposure and development to the spacer formation layer to be patterned and removing the support base; a step of bonding a transparent substrate to a region of the spacer, with which the removed support base made contact, so as to be included within the region. This makes it possible to manufacture a semiconductor wafer bonding product in which the semiconductor wafer and the transparent substrate are bonded together through the spacer uniformly and reliably.

Abstract: A wiring board includes a stacked body having a plurality of insulating layers and a plurality of wiring layers which are alternately stacked, and a solder-resist layer being formed on one side of the stacked body and covering the wiring layer exposed to the one side of the stacked body. The insulating layer is exposed to the other side of the stacked body. The solder-resist layer is in a transparent or semitransparent light yellow color.

Abstract: An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing the first electronic element and the first surface of the substrate. The resin mold further seals the second electronic element on the second surface of the substrate. The second surface of the substrate has a portion, which is exposed from the resin mold. The second electronic element is not disposed on the portion of the second surface.

Abstract: An electronic component has a substrate, a die bonding pad provided on an upper surface of the substrate, a semiconductor element bonded onto the die bonding pad by a die bonding resin, a conductive pattern disposed adjacent to the die bonding pad, and a coating member covering the conductive pattern. At least an outer peripheral portion of a surface of the die bonding pad is made of an inorganic material. The inorganic material of the outer peripheral portion is exposed. The die bonding pad and the conductive pattern are separated by an air gap such that the coating member does not come into contact with the die bonding pad.

Abstract: To provide a photosensitive adhesive which is sufficiently excellent in terms of all the properties of attachment, pattern formability, thermocompression bondability and high-temperature adhesion, and which has thermocompression bondability for adherends after patterning by exposure and development, and is capable of alkali development, as well as a film adhesive, an adhesive sheet, an adhesive pattern, a semiconductor wafer with an adhesive layer and a semiconductor device, which employ the same. A photosensitive adhesive comprising (A) an imide group-containing resin with a fluoroalkyl group, (B) a radiation-polymerizable compound, (C) a photoinitiator and (D) a thermosetting component.

Abstract: A method for assembling an optically pumped solid-state laser having an extended cavity. The method includes the steps of providing a casing, mounting a TEC and a base plate in the casing, and mounting a plurality of laser components on the base plate using a UV and heat curing adhesive. Once the laser components are correctly positioned and aligned on the base plate, the adhesive is pre-cured using UV radiation. Final curing of the adhesive is obtained by subjecting the entire laser package to an ambient temperature of at least 100° C. The base plate is preferably selected to have a CTE similar to that of the laser components in order to facilitate the high temperature curing. A preferred material for the base plate is AlSiC.

Abstract: An electrical connection support for receiving a semiconductor component includes an electrical connection plate having electrical connection pads. A stand-off structure is provided over the electrical connection pads. The stand-off structure may include a supplementary layer provided on a zone of the electrical connection plate which includes the electrical connection pads of the plate and is outside of a place configured to receive a semiconductor component. The stand-off structure further includes electrical connection vias passing through the supplementary layer. These vias are electrically connected to the electrical connection pads of the plate and have outer faces for making external electrical connection (for example, to another electrical connection support in a stacked structure).

Abstract: Disclosed is an adhesive composition which includes (a) an epoxy resin, (b) a curing agent and (c) a polymer compound incompatible with said epoxy resin, and further optionally includes (d) a filler and/or (e) a curing accelerator. Also disclosed are a process for producing an adhesive composition, including mixing (a) the epoxy resin and (b) the curing agent with (d) the filler, followed by mixing the resultant mixture with (c) the polymer compound incompatible with the epoxy resin; an adhesive film including the above-mentioned adhesive composition formed into a film; a substrate for mounting a semiconductor including a wiring board and the above-mentioned adhesive film disposed thereon on its side where chips are to be mounted; and a semiconductor device which includes the above-mentioned adhesive film or the substrate for mounting a semiconductor.

Abstract: A DC-DC buck converter in multi-die package is proposed having an output inductor, a low-side Schottky diode and a high-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a first die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the first die pad via an insulating die bond. Alternatively, the first die pad is grounded. The vertical MOSFET is a top drain N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the first die pad. The PRC is attached atop the first die pad via a conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration.

Abstract: A semiconductor device having a semiconductor substrate including a first surface and a second surface corresponding to a back surface with respect to the first surface and having first through electrodes which extend through the first surface and the second surface, semiconductor chips which are mounted over the first surface of the semiconductor substrate and each of which is constituted of a material of the same kind as the semiconductor substrate and has a circuit element electrically connected to the first through electrodes, stress relaxing sections which are provided with first conductors formed over the second surface of the semiconductor substrate and electrically connected to the first through electrodes of the semiconductor substrate and having flexibility, and external connecting terminals provided over the stress relaxing sections and connected to the first conductors respectively.

Abstract: In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

Abstract: A stack package includes a substrate, a lower semiconductor chip stacked on the substrate and electrically connected to the substrate through a lower via, a plurality of upper semiconductor chips stacked on the lower semiconductor chip and electrically connected to the lower via through an upper via, wherein the upper semiconductor chips are larger in size than the lower semiconductor chip, and an edge guide electrically connecting edge vias of the upper semiconductor chips and the substrate.

Abstract: A highly flexible semiconductor device of a stacked-type semiconductor device which transfers information by inductive coupling between inductors, in which LSI chips can be stacked even when a transmitter circuit and a receiver circuit are arranged at different positions from each other when viewed in a stacking direction. The semiconductor device has an interposer including a first inductor which is inductively coupled with a transmitter circuit of a first LSI chip to be stacked, and a second inductor which is inductively coupled with a receiver circuit of a second LSI chip to be stacked, the first inductor and the second inductor being electrically connected. An interchip communication is made from the first LSI chip to the second LSI chip.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone. The inventive package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate which performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the die and the package, and providing an exterior surface for making electrical connections between package and a user's printed circuit board. In some embodiments, the acoustic port is located in the substrate directly under the silicon condenser die which decreases the thickness of the inventive package.

Abstract: A stacking carrier and a stacking method are provided. The stacking method is used between a wafer and a stacking carrier having the same shape. The stacking method includes the following steps. Firstly, an adhesive layer is coated on a surface of the carrier. Then, the adhesive layer corresponding to an edge of the carrier is partially removed, thereby defining at least one adhesive layer indentation. Afterwards, the wafer is stacked on the carrier through the adhesive layer having the adhesive layer indentation.

Abstract: A system and method for forming an embedded chip package is disclosed. The embedded chip package includes a first chip portion having a plurality of pre-patterned re-distribution layers joined together to form a pre-patterned lamination stack, with the pre-patterned lamination stack having a die opening extending therethrough. The embedded chip package also includes a die positioned in the die opening and a second chip portion having at least one uncut re-distribution layer, with the second chip portion affixed to each of the first chip portion and the die and being patterned to be electrically connected to both of the first chip portion and the die.

Abstract: A fabrication method for integrating chip(s) onto a flexible substrate in forming a flexible micro-system. The method includes a low-temperature flip-chip and a wafer-level fabrication process. Using the low-temperature flip-chip technique, the chip is bonded metallically onto the flexible substrate. To separate the flexible substrate from the substrate, etching is used to remove the sacrificial layer underneath the flexible substrate. The instant disclosure applies standardized micro-fabrication process for integrating chip(s) onto the flexible substrate. Without using special materials or fabrication procedures, the instant disclosure offers a cost-effective fabrication method for flexible micro-systems.

Abstract: A thermosetting tape is adopted as a dicing tape and, after package dicing, the thermosetting tape is heated, then a desired one of divided CSPs is picked up by an inverting collet. Since the thermosetting tape is heated o a predetermined temperature so that its adhesive force becomes zero, the CSP can be picked up by the inverting collet without peeling it off from the thermosetting tape. Thus, peel-off charging does not occur and therefore it is not necessary to perform a destaticizing process. As a result, it is possible to improve the production efficiency in assembling the semiconductor device (CSP).

Abstract: A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias.

Abstract: Methods and apparatus for eliminating wire sweep and shorting while avoiding the use of under-bump metallization and high cost attendant to the use of conventional redistribution layers. An anisotropically conductive (z-axis) conductive layer in the form of a film or tape is applied to an active surface of a die and used as a base for conductive redistribution bumps formed on the anisotropically conductive layer, bonded to ends of conductive columns thereof and wire bonded to bond pads of the die. Packages so formed may be connected to substrates either with additional wire bonds extending from the conductive redistribution bumps to terminal pads or by flip-chip bonding using conductive bumps formed on the conductive redistribution bumps to connect to the terminal pads. The acts of the methods may be performed at the wafer level. Semiconductor die assemblies may be formed using the methods.

Abstract: A semiconductor device includes an upper circuit board which has a plurality of upper-layer wirings including a plurality of first upper-layer wirings, and has a plurality of first and second lower-layer wirings. A first semiconductor structure body is provided on an upper side of the upper circuit board and is electrically connected to the first upper-layer wirings. A lower circuit board which is provided on a peripheral part of a lower side of the upper circuit board, the lower circuit board including a plurality of external connection wirings that are electrically connected to the second lower-layer wirings, and an opening portion which exposes the first lower-layer wirings. A second semiconductor structure body which is disposed in the opening portion of the lower circuit board, second semiconductor structure body including a plurality of external connection electrodes that are electrically connected to the first lower-layer wirings of the upper circuit board.

Abstract: An apparatus having a substrate, an LED light source attached to the substrate, an electrical connector attached to the substrate and electrically connected to the LED light source, a potting material on the substrate and covering at least a portion of the electrical connector; and a barrier separating the potting material from the LED light source, the barrier having a height that exceeds the thickness of the potting material on the substrate.

Abstract: A semiconductor device has a plurality of similar sized semiconductor die each with a plurality of bond pads formed over a surface of the semiconductor die. An insulating layer is formed around a periphery of each semiconductor die. A plurality of conductive THVs is formed through the insulating layer. A plurality of conductive traces is formed over the surface of the semiconductor die electrically connected between the bond pads and conductive THVs. The semiconductor die are stacked to electrically connect the conductive THVs between adjacent semiconductor die. The stacked semiconductor die are mounted within an integrated cavity of a substrate or leadframe structure. An encapsulant is deposited over the substrate or leadframe structure and the semiconductor die. A thermally conductive lid is formed over a surface of the substrate or leadframe structure. The stacked semiconductor die are attached to the thermally conductive lid.

Abstract: Exemplary semiconductor device packaging structure and packaging method are provided. The packaging method uses an adhesive layer to bond multiple wafer pieces onto a first surface of a carrier substrate, each adjacent two of the wafer pieces having a gap formed therebetween for exposing a part of the adhesive layer. A packaging layer is filled in each of the gaps. At least one through silicon via is formed each of the wafer pieces to expose a bonding pad formed on an active surface of the wafer pieces. Redistribution circuit layers are formed on back surfaces of the respective wafer pieces and filled into the through silicon vias for electrical connection with the bonding pads. A sawing process is performed to saw starting from each of the packaging layers to a second surface of the carrier substrate, and thereby multiple semiconductor device packaging structures are obtained.

Abstract: A light emitting device includes a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region, a metal p-contact disposed on the p-type region, and a metal n-contact disposed on the n-type region. The metal p-contact and the metal n-contact are both formed on the same side of the semiconductor structure. The light emitting device is connected to a mount by a bonding structure. The bonding structure includes a plurality of metal regions separated by gaps and a metal structure disposed between the light emitting device and the mount proximate to an edge of the light emitting device. The metal structure is configured such that during bonding, the metal structure forms a continuous seal between the light emitting device and the mount.

Abstract: A wiring substrate is provided, including an insulating resin layer which is provided on both surfaces of a sheet-like fibrous body and with which the sheet-like fibrous body is impregnated, and a through wiring provided in a region surrounded by the insulating resin layer. The through wiring is formed using a conductive material, the conductive material is exposed on both surfaces of the insulating resin layer, the sheet-like fibrous body is positioned in the conductive material, and the sheet-like fibrous body is impregnated with the conductive material. A manufacturing method of the wiring substrate is also provided.

Abstract: Electrically and thermally enhanced die-up ball grid array (BGA) packages are described. A BGA package includes a stiffener, substrate, a silicon die, and solder balls. The die is mounted to the top of the stiffener. The stiffener is mounted to the top of the substrate. A plurality of solder balls are attached to the bottom surface of the substrate. A top surface of the stiffener may be patterned. A second stiffener may be attached to the first stiffener. The substrate may include one, two, four, or other number of metal layers. Conductive vias through a dielectric layer of the substrate may couple the stiffener to solder balls. An opening may be formed through the substrate, exposing a portion of the stiffener. The stiffener may have a down-set portion. A heat slug may be attached to the exposed portion of the stiffener. A locking mechanism may be used to enhance attachment of the heat slug to the stiffener. The heat slug may be directly attached to the die through an opening in the stiffener.

Abstract: An integrated circuit package in package system including: providing a substrate; mounting a wire bonded die with an active side over the substrate; connecting the active side to the substrate with bond wires; mounting a structure over the wire bonded die having a wire-in-film adhesive between the structure and the wire bonded die and overhangs at ends of the structure between the wire-in-film adhesive and the substrate; mounting support structures at the overhangs between the wire-in-film adhesive and the substrate; and encapsulating the wire bonded die and the structure with an encapsulation.

Abstract: A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate having a component side and a system side; coupling a first integrated circuit die on the component side; coupling stacking interconnects on the component side around the first integrated circuit die; forming a package body on the component side, the first integrated circuit die, and the stacking interconnects; forming vertical insertion cavities through the package body and on the stacking interconnects; and forming a trench, in the package body, adjacent to the vertical insertion cavities for reducing a package warping stress.

Abstract: A method of manufacture of an integrated circuit package system including: providing a selective slot die paddle having selective slots and edge pieces around the perimeter; providing extended leads protruding into the selective slots; mounting an integrated circuit die on the selective slot die paddle; and coupling bond wires between the integrated circuit die, the edge pieces, the extended leads, or a combination thereof.

Abstract: An apparatus includes a coreless substrate with an embedded die that is integral to the coreless substrate, and at least one device assembled on a surface that is opposite to a ball-grid array disposed on the coreless substrate. The apparatus may include an over-mold layer to protect the at least one device assembled on the surface.

Abstract: Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor wafer that has plural semiconductor chips. Each of the plural semiconductor chips includes a first principal side and a second and opposite principal side. Material is removed from the semiconductor wafer to define at least one rounded corner of the first principal side of at least one of the plural semiconductor chips.

Abstract: A method for fabricating an encapsulant cavity integrated circuit package system includes: forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.

Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.

Abstract: An integrated semiconductor device includes a plurality of semiconductor elements having different integrated element circuits or different sizes; an insulating material arranged between the semiconductor elements; an organic insulating film arranged entirely on the semiconductor elements and the insulating material; a fine thin-layer wiring that arranged on the organic insulating film and connects the semiconductor elements; a first input/output electrode arranged on an area of the insulating material; and a first bump electrode formed on the first input/output electrode.

Abstract: A semiconductor memory device includes: a wiring board including an element mounting portion and connection pads; a first element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the element mounting portion of the wiring board in a way that pad arrangement sides of the semiconductor elements face in the same direction, and that the electrode pads are exposed; a second element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the first element group in a way that pad arrangement sides of the semiconductor elements face in the same direction as that of the first element group, and that the electrode pads are exposed, the second element group being disposed to be offset from the first element g

Abstract: A semiconductor package having a structure in which heat produced in the interior of the package is effectively spread to the outside of the package is provided. The semiconductor package includes one or more semiconductor chips, one or more substrates (PCBs) having the semiconductor chips respectively attached thereto, a plurality of conductive balls such as a plurality of solder balls to provide voltages and signals to the one or more semiconductor chips, and a heat sink positioned to spread heat produced in the interior of the package to the outside and directly connected to at least one of the plurality of solder balls.

Abstract: An integrated circuit device includes a semiconductor chip having an active surface with a plurality of chip contact pads, a rewiring substrate and an electrically conductive inductor coil for magnetically aligning the semiconductor chip with the rewiring substrate.

Abstract: An integrated circuit package includes a microelectromechanical systems (MEMS) device embedded in a packaging substrate. The MEMS device is located on a die embedded in the packaging substrate and covered by a hermetic seal. Low-stress material in the packaging substrate surrounds the MEMS device. Additionally, interconnects may be used as standoffs to reduce stress on the MEMS device. The MEMS device is embedded a distance into the packaging substrate leaving for example, 30-80 microns, between the hermetic seal of the MEMS device and the support surface of the packaging substrate. Embedding the MEMS device results in lower stress on the MEMS device.

Abstract: A method for producing a plurality of semiconductor chips is specified. A plurality of semiconductor bodies is provided on a substrate, wherein the semiconductor bodies are spaced apart from one another by interspaces. A structured carrier is provided, having a plurality of elevations. The structured carrier is positioned relative to the substrate in such a way that the elevations of the structured carrier extend into the interspaces between the semiconductor bodies A mechanically stable assemblage is produced, comprising the substrate and the structured carrier. The assemblage is singulated into a plurality of semiconductor chips.

Abstract: A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.

Abstract: A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema.

Abstract: A portable memory card and methods of manufacturing same are disclosed. The portable memory includes a substrate having a plurality of holes formed therein. During the encapsulation process, mold compound flows over the top surface of the substrate, through the holes, and down into a recessed section formed in the bottom mold cap plate to form a projection of mold compound on the bottom surface of the substrate.

Abstract: In thin film transistors (TFTs) having an active layer of crystalline silicon adapted for mass production, a catalytic element is introduced into doped regions of an amorphous silicon film by ion implantation or other means. This film is crystallized at a temperature below the strain point of the glass substrate. Further, a gate insulating film and a gate electrode are formed. Impurities are introduced by a self-aligning process. Then, the laminate is annealed below the strain point of the substrate to activate the dopant impurities. On the other hand, Neckel or other element is also used as a catalytic element for promoting crystallization of an amorphous silicon film. First, this catalytic element is applied in contact with the surface of the amorphous silicon film. The film is heated at 450 to 650° C. to create crystal nuclei. The film is further heated at a higher temperature to grow the crystal grains. In this way, a crystalline silicon film having improved crystallinity is formed.

Abstract: A semiconductor device with a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads (103) in pad locations has an encapsulated region on the top surface of the substrate, extending to the edge of the substrate, enclosing the chip, and having contact apertures (703) at the pad locations for external communication with the pad metal surfaces. The apertures may have not-smooth sidewall surfaces and may be filled with solder material (704) to contact the pads. Metal-filled surface grooves (710) in the encapsulated region, with smooth groove bottom and sidewalls, are selected to serve as customized routing interconnections, or redistribution lines, between selected apertures and thus to facilitate the coupling with another semiconductor device to form a package-on-package assembly.