Abstract: This invention provides a method for fabricating a semiconductor device and a carrier applied therein. The method includes the steps of: disposing a chip-mounted substrate in an opening of a carrier; forming at least a storage aperture and at least an inspection aperture in the carrier; infusing an adhesive into the storage aperture to fill a gap between the substrate and carrier with the adhesive by capillarity; determining whether the inspection aperture is filled with the adhesive to ascertain whether the gap is completely filled with the adhesive; in response to a positive result, performing a molding process to form a molding compound for encapsulating the chip; and performing implantation of solder ball and a singulation process to form a semiconductor device with desirable dimensions.

Abstract: An integrated circuit package system includes: providing a package carrier; forming a first channel in the package carrier; mounting a first integrated circuit device over the package carrier and adjacent to the first channel; mounting a second integrated circuit device over the package carrier and adjacent to the first channel; and forming a contiguous underfill fillet with the first channel and under both the first integrated circuit device and the second integrated circuit device.

Abstract: A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved.

Abstract: Microelectronic imaging units and methods for manufacturing microelectronic imaging units are disclosed herein. In one embodiment, a method includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes disposing a plurality of discrete stand-offs on the support member. The discrete stand-offs are arranged in arrays relative to corresponding imaging dies. The method further includes electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member, and attaching a plurality of covers to corresponding stand-off arrays so that the covers are positioned over the image sensors.

Abstract: A method for manufacturing an adhesive substrate with a die-cavity sidewall is disclosed. A region for forming die-cavity sidewall is defined on one surface of the substrate. The substrate is laminated with a sacrificial film, a partially cured resin is formed between the substrate and the sacrificial film. And then, an aperture is routed through the substrate, the partially cured resin, and the sacrificial film. The aperture is located corresponding to the region so that the substrate has a die-cavity sidewall formed inside the aperture. Thereafter, the sacrificial film is removed to expose the partially cured resin on the substrate so that the substrate with a die-cavity sidewall can have good adhesion.

Abstract: A plurality of film substrates (2) having a bare chip (1) mounted on one side or both sides are joined into a laminated state by joint portions (3) and are attached to a motherboard (4) through junction by a joint portion (8) at a location off the mounting areas of the bare chips (1), thereby achieving a lower profile, higher lamination, and higher capacity.

Abstract: A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting and receiving signals to and from a second substrate, input-output circuits disposed on the first region or the second region, the input-out circuits corresponding to the first communication units, and a control circuit for controlling input to and output from the input-output circuits disposed on the first region or the second region of the first substrate. Each of the input-output circuits includes an output circuit for outputting a signal to a second communication unit of the second substrate corresponding to the first communication unit and an input unit for receiving a signal sent from the corresponding second communication unit.

Abstract: The present invention relates to a stackable semiconductor package and the method for making the same. The stackable semiconductor package comprises a first substrate, a semiconductor device, a plurality of stud bumps, a plurality of first wires, a second substrate, and a molding compound. The semiconductor device is disposed on the first substrate and electrically connected to the first substrate. The stud bumps are above the semiconductor device. The first wires are used for electrically connecting the stud bumps and the first substrate. The stud bumps are in contact with the second substrate. The molding compound encapsulates the first substrate, the semiconductor device, the stud bumps, the first wires, and the second substrate, and thus, the second substrate will not undergo wire bonding, and will not be suspended and shake or sway, as present in a conventional stackable semiconductor package.

Abstract: A semiconductor device may includes a first semiconductor substrate provided on a second semiconductor substrate in a system-in-package arrangement. The first semiconductor substrate may include a plurality of through electrodes formed in first semiconductor substrate. The second semiconductor substrate may include a transistor layer formed over the second semiconductor substrate and a multilayer metal layer formed over the second semiconductor substrate. A plurality of connection electrodes for electrically connecting the first semiconductor substrate to the second semiconductor substrate.

Abstract: Techniques for integrated circuit packaging in a flip chip configuration that ensures a migration path between related integrated circuits and utilizes core I/O (or area I/O) are provided. An integrated circuit, having a superset of functional circuit elements as compared to a reference integrated circuit, includes first and second sets of interconnection elements to connect to a package substrate. The first and second sets have matching arrangements, and corresponding interconnection elements of the first and second set have consistent functional assignments. The first and second sets include interconnection elements of mixed functional assignments. The first set is disposed within an area matching a size and shape of the reference integrated circuit, while the second set is disposed outside the area. In a specific embodiment, the first set includes an I/O signal and is located in the core area.

Abstract: The present invention discloses a tool structure for chip redistribution and method of chip redistribution. The tool structure comprises a base substrate, a separable adhesion film formed on the base substrate, and the patterned glues placed on the separable adhesion film for fixating the dice covered by the core paste materials formed on a fixed substrate. The fixed substrate is bonding on the core paste materials and dice to form the panel wafer. The method comprises printing the pluralities of patterned glues placed on the separable adhesion film and the bonding pluralities of dice covered by the core paste materials, and then, the fixed substrate is bonding on the core paste materials and pluralities of dice. The method further comprises curing and separating the glues and the pluralities of dice with the fixed substrate, and then cleaning the residual glues on the panel wafer (pluralities of dice).

Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluorethylene, filled with fibers which may be glass fibers or ceramic fibers.

Abstract: A multilayer substrate includes an insulating base member having a plurality of resin films, an electric element embedded in the insulating base member, and a spacer. The resin films are made of a thermoplastic resin and stacked and attached to each other. At least one resin film has a through hole for inserting the electric element. The one resin film further has a plurality of protruding members. One protruding member opposes to another one protruding member so that the one and the another one contact and sandwich the electric element. The spacer is arranged between the one resin film and an adjacent resin film and is disposed at a base portion of one of the protruding members.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.

Abstract: A method for creating a plurality of semiconductor assemblies that includes the steps of creating a plurality of quasi-wafers, each quasi-wafer comprising a plurality of semiconductor devices; transferring the plurality of semiconductor devices on each quasi-wafers onto a carrier having a functional adhesive; and bonding the plurality of semiconductor devices to a substrate.

Abstract: Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 ?m, a DeltaWarp of less than 30 ?m, a bow of less than 10 ?m and a DeltaBow of less than 10 ?m. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.

Abstract: Some embodiments of the present invention relate to a semiconducting device and method that include a substrate and a first die that is attached to the substrate. The first die includes active circuitry (e.g., a flash memory array or logic circuitry) on an upper surface of the first die. The semiconducting device further includes a spacer that covers the active circuitry on the upper surface of the first die and a second die that is stacked onto the spacer and the first die. The spacer extends from a first side of the first die to an opposing second side of the first die. The spacer also extends near a third side of the first die and an opposing fourth side of the first die such that the active circuitry is exposed near the third and fourth sides of the first die.

Abstract: A method for producing a laser diode component having an electrically insulating housing basic body (1) and electrical connecting conductors (5a, 5b), which are led out from the housing basic body and are accessible from outside the housing basic body (1). The housing basic body (1) is produced from a material which is transmissive to a laser radiation to be emitted by the laser diode component, and comprises a chip mounting region (3). A beam axis (100) of the laser diode component runs through the housing basic body (1). A housing that can be produced in this way and laser diode component having a housing of this type are also disclosed.

Abstract: A carrier structure for a semiconductor chip and a method for manufacturing the same are disclosed. The method includes the following steps: providing a carrier board having at least one through cavity, wherein a removable film is formed on the surface of the carrier board, and a semiconductor chip is temporarily fixed in the through cavity by the removable film; filling the gap between the through cavity of the carrier board and the semiconductor chip with an adhesive material in order to fix the semiconductor chip; and removing the removable film. The disclosed method can reduce the alignment error resulted from the tiny shift of the semiconductor chip caused by jitters before the semiconductor is fixed in the cavity, thereby to increase the accuracy of the alignment, to facilitate fine wiring, and to meet the trend toward compact size of semiconductor packages.

Abstract: A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Abstract: Provided are a semiconductor package and a method for manufacturing the same. The semiconductor package includes: a substrate having a top surface on which a lead is formed and a bottom surface opposite to the top surface; a semiconductor chip attached to the top surface of the substrate and having an active surface on which a chip pad is formed and a back surface opposite to the active surface; a redistribution pattern electrically connected to the chip pad and extending from the active surface to a lateral surface of the semiconductor chip; and an interconnector electrically connecting the redistribution to the lead on the lateral surface of the semiconductor chip.

Abstract: The invention relates to a semiconductor component (1) comprising a semiconductor chip (3) provided with a passivation layer (2), and to methods for producing the same. In this case, the passivation layer (2) covers the topmost interconnect structure (4) of the semiconductor chip (1) whilst leaving contact areas (5) free. The passivation layer (2) is in direct adhesive contact with the plastic housing composition (6) of the semiconductor component (1), wherein the passivation layer (2) comprises a polymer (7) with embedded mineral-ceramic nanoparticles (8).

Abstract: The present invention is related in general to a wafer-level packaging technique for micro-electro-mechanical systems (MEMS). A cap structure is provided encapsulating a MEMS element formed on a base substrate. A channel communicates etching holes provided on said cap structure, for the passage of an etching fluid to a chamber in which the MEMS element is housed. The holes are arranged in such a manner that they do not overlap, which allows the provision of a large number of etching holes above the MEMS element, but prevents a sealing material from reaching the MEMS element. The invention provides a low cost wafer-level packaging technique for MEMS devices, that reduces the total etching time of the sacrificial material and provides a reinforced protective cap structure for the MEMS package.

Abstract: A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passivation layer on the dielectric layer top surface and on the electrically conducting bond pad, wherein the first passivation layer comprises a first hole directly above the electrically conducting bond pad, and (iv) an electrically conducting solder bump filling the first hole and electrically coupled to the electrically conducting bond pad; and (b) forming a second passivation layer on the first passivation layer, wherein second passivation layer is in direct physical contact with the electrically conducting solder bump, and wherein the electrically conducting solder bump is exposed to a surrounding ambient immediately after said forming the second passivation layer is performed.

Abstract: A stacked semiconductor package may include a wiring substrate. A first semiconductor chip may be disposed on the wiring substrate and wire-bonded to the wiring substrate. An interposer chip may be disposed on the wiring substrate and sire bonded to the wiring substrate. The interposer chip may include a circuit element and a bonding pad being electrically connected. A second semiconductor chip may be disposed on the interposer chip and wire-bonded to the interposer chip. The second semiconductor chip may be electrically connected to the wiring substrate through the interposer chip.

Abstract: Methods of wafer-to-wafer bonding are disclosed. These methods use a force-transposing substrate providing redistribution of the applied force to the local bonding areas across the wafer. Certain versions of the Present Invention also provide a compliant force-distributing member along with applying bonding material to bonding areas in selectable locations. A predetermined sequence of external force loading and temperature steps ensure creating bonds between the wafers in the bonding areas. The disclosed methods improve wafer bonding, by increasing its uniformity and strength across the wafer, increase both reproducibility and yield process and decrease cost of semiconductor and MEMS devices.

Abstract: An integrated circuit module comprises a chip, the chip comprising a substrate with a first main area and a second main area, the first main area comprising two half-sets of pads, the chip further comprising an integrated circuit with components and two half-sets of connection lines, the connection lines connecting the components of the integrated circuit to the pads, the integrated circuit further comprising a changeover device, the changeover device having two switching states in order to interchange the electrical assignment between the half-sets of the connection lines and the half-sets of the pads, and a carrier, the carrier comprising contact pieces. The chip is arranged on the carrier with one of the two main areas of the chip facing the carrier and the contact pieces of the carrier are connected to the pads of the chip, wherein one of the two switching states of the changeover device is selected, depending on which of the two main areas of the chip is the area facing the carrier.

Abstract: A semiconductor component arrangement having a semiconductor component, a mount, and an adhesive, wherein the adhesive connects the semiconductor component to the mount and the adhesive contains a marker substance. Also disclosed is a method for inspecting the connection of a semiconductor component to a mount. The semiconductor component is fixed on the mount using an adhesive, wherein the adhesive contains a marker substance, the mount with the semiconductor component is cleaned, and the mount is inspected for residues of the adhesive on the basis of radiation which is characteristic of the marker substance.

Abstract: A die has a part that is sealed with a cap. The seal can be hermetic or non-hermetic. If hermetic, a layer of glass or metal is formed in the surface of the die, and the cap has a layer of glass or metal at a peripheral area so that, when heated, the layers form a hermetic seal. A non-hermetic seal can be formed by bonding a cap with a patterned adhesive. The cap, which can be silicon or can be a metal paddle, is electrically coupled to a fixed voltage to shield the part of the die.

Abstract: An exemplary assembly comprises a printed wiring board having a first surface, and a package including a plurality of solder joints, such as solder balls, on one surface of the package. An anchor via is defined through the first surface of the printed wiring board, and conductive material situated in the anchor via is connected to or integral with a respective solder joint of the package.

Abstract: The present invention includes a temporary fixing step of temporarily fixing a semiconductor element on an adherend interposing an adhesive sheet therebetween, a wire-bonding step of bonding wires to the semiconductor element, and a step of sealing the semiconductor element with a sealing resin, and in which the loss elastic modulus of the adhesive sheet at 175° C. is 2000 Pa or more.

Abstract: For molding semiconductor chips on a wiring substrate matrix with a sealing resin, the wiring substrate matrix is placed on a lower die cavity block of a lower die, and, thereafter, an upper die is brought down, whereby an outer peripheral portion of a cavity of the upper die comes into abutment against an outer peripheral portion of a main surface of the wiring substrate matrix, causing the substrate matrix to be deformed a sufficient extent to prevent resin leakage. Thereafter, block pins provided on the upper die push down the lower die cavity block. Thus, when clamping the wiring substrate matrix using both upper and lower dies, it is possible to suppress or prevent the application of excessive pressure to the wiring substrate matrix and to suppress or prevent deformation or cracking caused by crushing of the wiring substrate matrix. Consequently, the semiconductor device manufacturing yield can be improved.

Abstract: With the objective of enabling a reduction in the size of a final semiconductor device and its thinning, and attaining facilitation of a manufacturing process, the semiconductor device includes a circuit chip having a flat mounted surface, a circuit chip smaller in size than the former circuit chip, and a sheet-like support. The latter circuit chip is formed over a substrate and has a flat back surface fixed to the substrate and a flat surface positioned on the side opposite to the back surface. The support is bonded to the surface of the latter circuit chip and supports the latter circuit chip. Then, the back surface of the latter circuit chip supported by the support is peeled from the substrate and pressed against the mounted surface, thereby fixing the back surface of the latter circuit chip and the mounted surface by an intermolecular bonding force (e.g., hydrogen bonding).

Abstract: A method for producing a semiconductor device includes the steps of forming a predetermined device in a device layer grown on a semiconductor substrate with a sacrificial layer provided therebetween; and removing the sacrificial layer by etching to separate the semiconductor substrate from the device layer while a supporting substrate is bonded to the side of the device layer, wherein in the step of removing the sacrificial layer, a groove extending from the device layer to the sacrificial layer is formed before the sacrificial layer is removed, and the etching solution is allowed to penetrate to the sacrificial layer through the groove.

Abstract: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.

Abstract: A high-density electrical package utilizing an array of high performance demountable electrical contacts such as UEC, T-Spring, F-Spring and their equivalent contained in a carrier in the form of an interposer between one or more components and a substrate. The carrier is made of a thermally conductive metal or contains thermally conductive metal to provide heat-spreading or dissipation functions in addition to the function of the retention and alignment of the electrical contacts. The above interposer is used for chip attach for a single chip or a stack of chips in the package. The interposer provides electrical connections through individual electrical contact to another chip or to the substrate of the package. It provides also the heat spreading or dissipation function to the chips connected thermally to a particular interposer. The interposer can further be connected thermally to an external heat spreader when necessary.

Abstract: Provided are a semiconductor device capable of mounting a plurality of semiconductor chips in compact on a leadframe and reducing manufacturing costs, and a method of manufacturing the same.

Abstract: This disclosure relates to lids and methods for forming and using them. One embodiment of these lids enables MEMS protected by the lids to be smaller. Another of these lids enables testing of a group of conjoined, lidded MEMS. Also, processes for forming and using these lids are also disclosed. One of these processes forms lids from a lid precursor residing over an assembly MEMS.

Abstract: An inverted pyramid multi-die package provides, for each die pad on an upper die, a rigid support underneath extending to a substrate. Such configuration reduces both the wire sweep and weakening torques. A lower die, smaller than the upper die in at least one dimension, may be positioned between the upper die and the substrate. The two dice may or may not contact each other, or they may contact each other via an intermediate spacer. The lower die may be a flip chip. The multi-die package may be fashioned without the lower die or the substrate. Wire sweep is reduced, because the second die is smaller than the upper die in at least one dimension. Weakening torques are reduced, because spacers at the periphery of the upper die absorb the impact of bonding wires thereon.

Abstract: An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper surface configured to electrically couple a first end of a first electrically conductive lead wire. A second end of the first electrically conductive lead wire is bonded to the integrated circuit die. The upper surface is further configured to electrically couple a first end of a second electrically conductive lead wire and a second end of the second electrically conductive lead wire is bonded to a lead finger of the electrical package.

Abstract: A method of manufacturing a module, formed of a semiconductor element flip-chip bonded to a substrate and chip component soldered to the substrate, is disclosed. The method includes a step of mounting the chip component and the semiconductor element to the substrate, a first injection step for injecting first resin from a center of a lateral face of the semiconductor element into a gap between the semiconductor element and the substrate, a second injection step for applying second resin having a greater viscosity than the first resin to corners of the semiconductor element before the first resin reaches the corners, and a curing step for heating the module. This method allows mounting the chip component closer to the semiconductor element, so that the component can be mounted at a higher density on the module.

Abstract: There is provided a flip chip mounting process which is high in productivity and reliability, and thus can be applicable to the flip chip mounting of the next-generation LSI. This flip chip mounting process comprises the steps of supplying a resin (13) containing solder powder and a convection additive (12) onto a wiring substrate (10) having a plurality of electrode terminals (11), then bringing a semiconductor chip (20) having a plurality of connecting terminals (11) into contact with a surface of the supplied resin (13), and then heating the wiring substrate (10) to a temperature that enables the solder powder to melt. This heating step is carried out at a temperature higher than the boiling point of the convection additive (12) to allow the boiling convection additive (12) to move within the resin (12).

Abstract: A method for manufacturing a semiconductor apparatus including a plurality of device chips aligned approximately in an L-shape at the perimeter of the two adjacent sides of a flexible substrate and a circuit coupled with the device chip, the method including: aligning, on a temporal substrate, the plurality of device chips approximately in an L-shape, in an arrangement as on a surface of the flexible substrate, so as to form a group of device chips, and arranging a plurality of arrays of device chips on the temporal substrate, each array of device chips formed by the plurality of groups of device chips arranged in a band-shape, from one long side to the other long side of the temporal substrate, each L-shape formed by the group of device chips pointing towards the same direction, a front of the band-shape being a corner of a perimeter of the group; delaminating the group of device chips as one unit from the temporal substrate, transferring onto the surface of the flexible substrate; and coupling each of the d

Abstract: A wiring board (20) includes a first wiring portion (10) having a plurality of wiring layers (1) and a plurality of external connecting bumps (5), and a second wiring portion (15) integrated with the first wiring portion in the direction of thickness. The thermal expansion coefficient of the second wiring portion is made smaller than that of the first wiring portion, and equal to that of a semiconductor chip (30) to be mounted on the wiring board. This suppresses the internal stress resulting from the thermal expansion coefficient difference between the semiconductor chip and wiring board, and increases the reliability of a semiconductor device (50) obtained by mounting the semiconductor chip on the wiring board. The sizes of the opposing surfaces of the first and second wiring portions are also made equal.

Abstract: A method of producing a sheet 1 with IC tags comprises the steps of: preparing and feeding a sheet 21a with electrical conductors formed thereon; providing an adhesive 18 on the sheet 21a with electrical conductors; preparing multiple IC chips 20 and successively feeding the IC chips 20; successively arranging each IC chip 20 on the electrical conductors 22 of the sheet 21a; and fixing each IC chip 20 onto the electrical conductors 22 through the adhesive 18. The sheet 21a with electrical conductors formed thereon includes a non-conductive sheet 21 and a pair of electrical conductors 22. The pair of electrical conductors 22 of the sheet 21a with the electrical conductors are provided on the non-conductive sheet 21, extend in the feed direction, and are spaced apart from each other.

Abstract: A semiconductor device (1, 1A, 21, 31, 41, 51) provided with a first semiconductor chip (3) having a first functional surface (3F) formed with a first functional element (3a), a protective resin layer (12) provided on the first functional surface, and an external connection terminal (10, 19, 52) provided on a peripheral portion of the first functional surface for external electrical connection, the external connection terminal having a bottom surface (10B, 19BB) exposed from a bottom surface (12B) of the protective resin layer facing away from the first functional surface and a side surface (10S, 19BS) exposed from a side surface (12S) of the protective resin layer.

Abstract: A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die. In some embodiments a spacer is mounted upon the first die, on a spacer attach region of the surface of the first die that is not within the die attach region, and which may be generally near a margin of the first die.

Abstract: In a semiconductor device comprising a ceramic substrate, a surface mount component, and sealing resin and obtained by division into pieces, the ceramic substrate is composed of a multiple piece substrate provided with dividing grooves for the division into pieces on both front and rear surfaces in advance, a plurality of the surface mount components are mounted on the multiple piece substrate and sealed collectively by the sealing resin, and the substrate is divided along the dividing grooves. Further, when the shortest distance from an end on the front surface of the ceramic substrate to an end of the surface mount component is set to “a” ?m, a thickness of the ceramic substrate is set to “b” ?m, and sum of depths of the dividing grooves on the front and rear surfaces of the ceramic substrate is set to “c” ?m, a relationship of a?269×c/b+151 is established.

Abstract: A first semiconductor element and second semiconductor element are bonded via die-bonding material. A first electrode of the first semiconductor element and a third electrode are joined, by means of flip-chip bonding, to a semiconductor carrier that has the third electrode on the one face of the semiconductor carrier and a fourth electrode on the perimeter of the other face of the semiconductor carrier. The bonding pad of the second semiconductor element and the fourth electrode of the semiconductor carrier are connected via fine metal wire by means of wire bonding. The periphery of the first semiconductor element and the wiring portion of the fine metal wire are filled with insulating sealing resin between the semiconductor carrier and second semiconductor element and the sealing fill region for the sealing resin is formed substantially the same as the external dimensions of the second semiconductor element.

Abstract: A semiconductor device includes a support body, a first substrate provided on a surface at one side of the support body, a second substrate provided on a surface at the other side of the support body, and a semiconductor chip provided on the first substrate exposed to an opening part piercing the support body and the second substrate. The first substrate includes a first dielectric layer and a wiring layer, a plurality of first electrodes connected to the semiconductor chip which first electrodes are provided on a first surface of the first substrate exposed to an inside of the opening part, and the second substrate includes a second dielectric layer made of a material substantially the same as the first dielectric layer.