Abstract: Embodiments include electronic assemblies and methods for forming electronic assemblies. One embodiment includes a method of forming a MEMS device assembly, including forming an active MEMS region on a substrate. A plurality of bonding pads electrically coupled to the active MEMS region are formed. A seal ring wetting layer is also formed on the substrate, the seal ring wetting layer surrounding the active MEMS region. A single piece solder preform is positioned on the bonding pads and on the seal ring wetting layer, the single piece solder preform including a seal ring region and a bonding pad region. The seal ring region is connected to the bonding pad region by a plurality of solder bridges. The method also includes heating the single piece solder preform to a temperature above the reflow temperature, so that the bridges split and the solder from the preform accumulates on the seal ring wetting layer and the bonding pads. A lid is coupled to the solder.

Abstract: A power semiconductor module includes a housing, terminal elements leading to the outside of the housing, an electrically insulated substrate arranged inside the housing, with the substrate being comprised of an insulating body and having on the first main face facing away from the base plate a plurality of connecting tracks electrically insulated from each other. The terminal and connecting elements are arranged on a connecting track in with contact faces contacting connecting tracks or power semiconductor components, with the individual contact faces having a plurality of partial contact faces. In one optional embodiment, each partial contact face has a maximum area of 20 mm2. In another embodiment, partial contact faces each are arranged at a distance of approximately 5 mm with regard to each other and the connection of the partial faces to the connecting tracks or the power semiconductor components is flush.

Abstract: The detachment of a semiconductor chip (1) from a foil (4) and picking the semiconductor chip (1) from the foil (4) takes place with the support of a chip ejector (6), that has a ramp (16), the surface (17) of which is formed concave and ends at a stripping edge (18) projecting from the surface (9) of the chip ejector (6), and a support area (13) with grooves (12) arranged next to the stripping edge (18). Vacuum can be applied to the grooves (12). The detachment and picking of the semiconductor chip (1) from the foil (4) takes place in that the wafer table (5) is shifted relative to the chip ejector (6) in order to pull the foil (4) over the stripping edge (18) protruding from the surface (9) of the chip ejector (6), whereby the semiconductor chip (1) temporarily detaches itself at least partially from the foil (4) and lands on the foil (4) above the support area (13), and in that the chip gripper (7) picks the semiconductor chip (1) presented on the support area (13).

Abstract: A semiconductor module structure and a method of forming the semiconductor module structure are disclosed. The structure incorporates a die mounted on a substrate and covered by a lid. A thermal compound is disposed within a thermal gap between the die and the lid. A barrier around the periphery of the die extends between the lid and the substrate, contains the thermal compound, and flexes in response to expansion and contraction of both the substrate and the lid during cycling of the semiconductor module. More particularly, either the barrier is formed of a flexible material or has a flexible connection to the substrate and/or to the lid. The barrier effectively contains the thermal compound between the die and the lid and, thereby, provides acceptable and controlled coverage of the thermal compound over the die for heat removal.

Abstract: A micro-electro-mechanical systems (MEMS) component includes a panel, a chip having an underside containing active component structures, where the chip is mounted on the panel via bumps, a frame structure on the panel and enclosing an installation site of the chip, and a jet-printed structure closing a seam between frame structure and chip. The jet-printed structure has an upper edge that is above a lower edge of the chip.

Abstract: Methods of forming a pattern of filled dielectric material on a substrate by thermal transfer processes are disclosed comprising exposing to heat a thermally imageable donor element comprising a substrate and a transfer layer of dielectric material. The exposure pattern is the image of the desired pattern to be formed on the substrate, such that portions of the layer of dielectric material are transferred onto the substrate where the electronic device is being formed. The filled dielectric material can be patterned onto a gate electrode of a thin film transistor. The pattern dielectric material may also form an insulating layer for interconnects. Donor elements for use in the process are also disclosed. Methods for forming thin film transistors and donor elements for use in the thermal transfer processes are also disclosed.

Abstract: A method of producing a multilayer wiring substrate is disclosed. The multilayer wiring substrate is free from a core substrate and includes a build up layer which includes an insulator layer and a wiring layer. One of a first main surface and a second main surface of the build up layer is formed with a metal supporting frame body. The method includes the steps of: forming a first insulator layer on a first main surface of a metal supporting plate, where the first insulator layer is included in the insulator layer and becomes a first resist layer which is positioned on the first main surface's side of the build up layer, and forming a first metal pad layer in a given position on a first main surface of the first insulator layer, where the first metal pad layer is included in the wiring layer and becomes a metal pad layer.

Abstract: A multilayer circuit carrier, electronic devices and panel, and a method for producing a multilayer circuit carrier include at least one semiconductor chip, at least one rewiring layer with a rewiring structure, and at least one insulation layer, which has passage structures.

Abstract: The invention relates to the manufacturing of a multilayer structure and especially it relates to the manufacturing of a three-dimensional structure and its use as an electronics assembly substrate and as a winding for transformers and inductors. When a multilayer structure is manufactured by folding a conductor-insulator-conductor laminate, where the conductor layers to be separated from each other follow each other on opposite sides of the conductor-insulator-conductor laminate in the sections following each other and where the insulator has been removed from the places where the conductor layers are to be connected together after folding, it is possible to manufacture a wide range of three-dimensional multilayer structures where the volume occupied by the windings over the total volume can be maximized. Alternatively, by using the method it is also possible to manufacture a multilayer structure where components have been buried inside.

Abstract: Example embodiments relate to a semiconductor package, a method of manufacturing the semiconductor package, a stacked semiconductor package including the semiconductor package, and a method of manufacturing the stacked semiconductor package. Other example embodiments relate to a semiconductor package having a structure that allows at least two packages to be stacked, a method of manufacturing the semiconductor package, a stacked semiconductor package including the semiconductor package, and a method of manufacturing the stacked semiconductor package.

Abstract: A semiconductor spacer structure comprises in order a backgrinding tape layer, a spacer adhesive layer, a semiconductor spacer layer, an optional second spacer adhesive layer, a dicing tape layer. In a first method a spacer wafer having first and second sides, a backgrinding tape layer and a spacer adhesive layer between the first side and the backgrinding tape layer, is obtained. The second side is background and secured to a dicing tape. The backgrinding tape is removed and the resulting structure is diced to create spacer/adhesive die structures. A second method backgrinds the second side with the backgrinding tape layer at the first side. A protective cover layer is secured to the second side with a spacer adhesive layer therebetween. The backgrinding tape layer is removed and the remaining structure is secured to a dicing tape with the protective cover layer exposed. The protective cover layer is removed and the resulting structure is diced thereby creating spacer/adhesive die structures.

Abstract: Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

Abstract: Lands and Cu wirings are formed on surfaces of a glass epoxy substrate, and a solder mask is formed on the lands and the Cu wirings to form a chip-mounting substrate. A bottom surface of the chip-mounting substrate is made rough, and a semiconductor chip is mounted on a top surface of the chip-mounting substrate. Through holes communicating with the Cu wirings are formed on the solder mask to expose the Cu wirings. Solder balls are formed on the Cu wrings by thermal compression welding. Underfill material is injected into a clearance formed between the chip mounting substrate and a printed circuit board. Since the surface of the chip-mounting substrate is made rough, an area of a contact surface between the chip-mounting substrate and underfill material increases, hence an adhesive strength between the chip-mounting substrate and the printed circuit board is heightened.

Abstract: Provided is a hybrid integrated circuit device which can more effectively stabilize a circuit configured to operate at a high speed. A hybrid integrated circuit device of the embodiment includes a metal substrate provided with an insulating layer on a surface thereof, a conductive pattern formed on a surface of the insulating layer, a semiconductor element fixed onto the conductive pattern, a lead as external connecting means fixed to the conductive pattern in the periphery of the metal substrate, and a contact portion for electrically connecting the conductive pattern electrically connected to the semiconductor element to the metal substrate in the vicinity of the semiconductor element.

Abstract: A microelectronic subassembly includes a substrate having a first surface, and one or more microelectronic elements positioned above the first surface of the substrate, each microelectronic element having a contact bearing face confronting the first surface of the substrate and a back surface remote therefrom. The subassembly includes a substantially rigid plate attached to the back surfaces of the microelectronic elements, an array of flexible leads extending between the substrate and the microelectronic elements, the leads having first ends attached to the substrate and second ends attached to the contacts of the microelectronic elements, and an at least partially cured spacer material sandwiched between the substantially rigid plate and the substrate for holding the contact bearing faces of the microelectronic elements at a precise height above the substrate.