Abstract: A conductive structure for a semiconductor integrated circuit and method for forming the conductive structure are provided. The semiconductor integrated circuit has a pad and a passivation layer partially covering the pad to define a first opening portion having a first lateral size. The conductive structure electrically connects to the pad via the first opening portion. The conductive structure comprises a support layer defining a second opening portion. A conductor is formed in the second opening portion to serve as a bump having a planar top surface.

Abstract: The present invention comprises a semiconductor package comprising a bottom semiconductor package substrate which is populated with one or more electronic components. The electronic component(s) of the bottom substrate are covered or encapsulated with a suitable mold compound which hardens into a package body of the semiconductor package. The package body is provided with one or more vias through the completion of laser drilling process, such via(s) providing access to one or more corresponding conductive contacts of the bottom substrate. These vias are either lined or partially filled with a conductive metal material. Subsequently, a top semiconductor package substrate (which may optionally be populated with one or more electronic components) is mounted to the package body and electrically connected to the conductive metal within the via(s) of the package body.

Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Abstract: A silicon chip surface mounted via balls attached to its front surface, wherein the front and rear surfaces of the chip are covered with a thermosetting epoxy resin having the following characteristics: the resin contains a proportion ranging from 45 to 60% by weight of a load formed of carbon fiber particles with a maximum size of 20 ?m and with its largest portion having a diameter ranging between 2 and 8 ?m, on the front surface side, the loaded resin covers from 45 to 60% of the ball height, on the rear surface side, the loaded resin has a thickness ranging between 80 and 150 ?m.

Abstract: A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.

Abstract: Bump electrodes (conductive members) bonded onto lands disposed at a peripheral portion side than terminals (bonding leads) electrically coupled to pads (electrode pads) of a microcomputer chip (semiconductor chip) are sealed with sealing resin (a sealing body). Thereafter, the sealing resin is ground (removed) partially such that a part of each of the bump electrodes is exposed. The step of protruding the part of each of the bump electrodes from a front surface of the sealing resin is performed, after the grinding step.

Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Abstract: The present invention relates to a chip having a bump and a package having the same. The chip includes a chip body, at least one via, a passivation layer, an under ball metal layer and at least one bump. The via penetrates the chip body, and is exposed to a surface of the chip body. The passivation layer is disposed on the surface of the chip body, and the passivation layer has at least one opening. The opening exposes the via. The under ball metal layer is disposed in the opening of the passivation layer, and is connected to the via. The bump is disposed on the under ball metal layer, and includes a first metal layer, a second metal layer and a third metal layer. The first metal layer is disposed on the under ball metal layer. The second metal layer is disposed on the first metal layer. The third metal layer is disposed on the second metal layer. As the bumps can connect two chips, the chip is stackable, and so the density of the product is increased while the size of the product is reduced.

Abstract: A method comprises determining a warpage of an integrated circuit (IC) package design. The IC package design includes a substrate having a top solder mask on a first major surface and a bottom solder mask on a second major surface opposite the first major surface. The first major surface has an IC die mounted over the top solder mask. The design is modified, including modifying an average thickness of one of the group consisting of the top solder mask and the bottom solder mask, so as to reduce the warpage. An IC package is fabricated according to the modified design.

Abstract: There is provided a technology capable of suppressing the damage applied to a pad. When the divergence angle of an inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is very small in magnitude. In other words, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is sufficiently smaller in magnitude than the ultrasonic conversion load in a direction in parallel with the surface of the pad. Consequently, when the divergence angle of the inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad can be sufficiently reduced in magnitude, which can prevent pad peeling.

Abstract: An electronic device packaging structure is provided. The semiconductor device includes a semiconductor base, an emitter, a collector, and a gate. The emitter and the gate are disposed on a first surface of the semiconductor base. The collector is disposed on a second surface of the semiconductor base. A first passivation layer is located on the first surface of the semiconductor base surrounding the gate. A first conductive pad is disposed on the first passivation layer. A second conductive pad is disposed on the collector on the second surface. At least one conductive through via structure penetrates the first passivation layer, the first and second surfaces of the semiconductor base, and the collector to electrically connect the first and second conductive pads.

Abstract: A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.

Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.

Abstract: This description relates to an integrated circuit device including a semiconductor substrate, an under-bump-metallurgy (UBM) layer overlying the semiconductor substrate and a copper-containing pillar on the UBM layer. The copper-containing pillar includes a top surface, an upper sidewall surface adjacent to the top surface, and a lower sidewall surface adjacent to the UBM layer. The integrated circuit device further includes a barrier layer on the upper sidewall surface of the copper-containing pillar, wherein the barrier layer exposes the lower sidewall surface. The copper-containing pillar has a first height and the upper sidewall surface has a second height. The second height is greater than about 30 percent of the first height.

Abstract: Provided is a semiconductor element in which decrease in reliability of wiring is suppressed. A driver IC (10) has a plurality of output bumps (12) arranged in the direction (direction A) along the long sides (11a and 11b). The output bumps include a plurality of source bumps (12a) arranged near the center section of the long side, and a plurality of gate bumps (12b) arranged towards the end portions of the long side. The source bumps are arranged close to the long side (11a), and the gate bumps are arranged closer to the long side (11b) than the source bumps.

Abstract: A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve, an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to protruding TSV tips is on a portion of the sidewalls of protruding TSV tips. The passivation layers is absent from a distal portion of protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends which cover a portion of the TSV sidewalls, are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is ?25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends.

Abstract: A wafer-bump structure includes a wafer-state semiconductor die, a pre-treatment layer, a first ENIG laminate and at least one pillar bump. The wafer-state semiconductor die includes at least one die pad embedded therein and a passivation layer formed on the wafer-state semiconductor die and the die pad. The passivation layer includes an aperture for allowing access to a portion of the die pad. The pre-treatment layer is formed on the un-covered portion of the die pad. The first ENIG laminate is formed on the pre-treatment layer and an annular portion of the passivation layer around the pre-treatment layer. The pillar bump includes a conductive metal layer and a second ENIG laminate. The conductive metal layer is formed on the first ENIG laminate and another annular portion of the passivation layer around the first ENIG laminate. The second ENIG laminate is formed on the conductive metal layer and another annular portion of the passivation layer around the conductive metal layer.

Abstract: Semiconductor devices configured to test connectivity of micro bumps including one or more micro bumps and a boundary scan test block for testing connectivity of the micro bumps by scanning data input to the micro bumps and outputting the scanned data. The semiconductor device may include a first chip including solder balls and at least one or more switches electrically coupled with the respective solder balls, and a second chip stacked on top of the first chip and electrically coupled with the switches in direct access mode, including micro bumps that input/output signals transmitted from/to the solder balls.

Abstract: An under-bump metallization (UBM) structure for a semiconductor device is provided. The UBM structure has a center portion and extensions extending out from the center portion. The extensions may have any suitable shape, including a quadrangle, a triangle, a circle, a fan, a fan with extensions, or a modified quadrangle having a curved surface. Adjacent UBM structures may have the respective extensions aligned or rotated relative to each other. Flux may be applied to a portion of the extensions to allow an overlying conductive bump to adhere to a part of the extensions.

Abstract: A semiconductor device has a semiconductor die having a first surface and a second surface wherein at least one bond pad is formed on the first surface. A passivation layer is formed on the first surface of the semiconductor device, wherein a central area of the at least one bond is exposed. A seed layer is formed on exposed portions of the bond pad and the passivation layer. A conductive pillar is formed on the seed layer. The conductive pillar has a base portion wherein the base portion has a diameter smaller than the seed layer and a stress relief portion extending from a lateral surface of a lower section of the base portion toward distal ends of the seed layer. A solder layer is formed on the conductive pillar.

Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes providing a semiconductor chip that has a conductor pad and a passivation structure over the conductor pad. A first metallic layer is applied on the passivation structure and in electrical contact with the conductor pad. The first metallic layer covers a first portion but not a second portion of the passivation structure. A second metallic layer is applied to the first metallic layer. A polymer layer is applied to the second metallic layer. The polymer layer includes a first opening in alignment with the first metallic layer that exposes a portion of the second layer. A conducting solder barrier layer is applied to the exposed portion of the second metallic layer.

Abstract: A method for making an electric interconnection between two conducting layers, separated by at least one insulation or semi-conducting layer, which includes forming a stud extending between at least the lower conducting layer and the upper conducting layer, where the nature and/or the shape of the stud impart non-wettability properties relative to the material used for the separating layer.

Abstract: A method of manufacturing an integrated circuit, IC, package comprising radio frequency, RF, components, the method comprising: electrically connecting a printed circuit pattern on an external major surface of an IC assembly to an RF testing motherboard by bringing them together with an interposed adaptor layer, the adaptor layer comprising a double-sided PCB, printed circuit board, with conductive vias between its printed circuit layers; RF testing the IC assembly using the RF testing motherboard, while RF tuning components of the IC assembly; and separating the IC assembly and connecting its major surface to a solder ball grid array, BGA, which has substantially the same RF impedance as the adaptor at RF signal paths from the IC assembly to the BGA.

Abstract: Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.

Abstract: A method for detecting soft errors in an integrated circuit (IC) due to transient-particle emission, the IC comprising at least one chip and a substrate includes mixing an epoxy with a radioactive source to form a hot underfill (HUF); underfilling the chip with the HUF; sealing the underfilled chip; measuring a radioactivity of the HUF at an edge of the chip; measuring the radioactivity of the HUF on a test coupon; testing the IC for soft errors by determining a current radioactivity of the HUF at the time of testing based on the measured radioactivity; and after the expiration of a radioactive decay period of the radioactive source, using the IC in a computing device by a user.

Abstract: The embodiments of bump-on-trace (BOT) structures and their layout on a die described reduce stresses on the dielectric layer on the metal pad and on the metal traces of the BOT structures. By orienting the axes of the metal bumps away from being parallel to the metal traces, the stresses can be reduced, which can reduce the risk of delamination of the metal traces from the substrate and the dielectric layer from the metal pad. Further, the stresses of the dielectric layer on the metal pad and on the metal traces may also be reduced by orienting the axes of the metal traces toward the center of the die. As a result, the yield can be increased.

Abstract: A fingerprint sensor package, including a sensing side for sensing fingerprint information and a separate connection side for electrically connecting the fingerprint sensor package to a host device, is disclosed. The fingerprint sensor package can also include a sensor integrated circuit facing the sensing side and substantially surrounded by a fill material. The fill material includes vias at peripheral locations around the sensor integrated circuit. The fingerprint sensor package can further include a redistribution layer on the sensing side which redistributes connections of the sensor integrated circuit to the vias. The connections can further be directed through the vias to a ball grid array on the connection side. Some aspects also include electrostatic discharge traces positioned at least partially around a perimeter of the connection side. Methods of manufacturing arc also disclosed.

Abstract: A semiconductor device includes a semiconductor chip, an electrode pad formed on the semiconductor chip, an underlying barrier metal formed on the electrode pad, a solder bump formed on the underlying barrier metal, and an underfill material surrounding the underlying barrier metal and the solder bump. A junction interface of the solder bump with the underlying barrier metal corresponds to an upper surface of the underlying barrier metal, and a portion of the underfill material bonded to a side surface of the solder bump and an end surface of the underlying barrier metal forms a right angle or an obtuse angle.

Abstract: A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Abstract: In this semiconductor device, the through-hole is formed in the substrate, and is located under the conductive pattern. The insulating layer is located at the bottom surface of the through-hole. The conductive pattern is located on one surface side of the substrate. The opening pattern is formed in the insulating layer which is located between the through-hole and the conductive pattern, where the distance r3 from the circumference of the opening pattern to the central axis of the through-hole is smaller than the distance r1 in the through-hole. By providing the opening pattern, the conductive pattern is exposed at the bottom surface of the through-hole. The bump is located on the back surface side of the substrate, and is formed integrally with the through-electrode.

Abstract: This invention improves reliability of a semiconductor device and a manufacturing method thereof. A glass substrate is bonded on a surface of a silicon wafer formed with pad electrodes. Next, via holes are formed from a back surface of the silicon wafer to pad electrodes, and a groove is formed extending along a center line of a dicing line and penetrating the silicon wafer from its back surface. After then, in processes including heating treatment, cushioning pads, wirings, a solder mask, and solder balls are formed on the back surface of the silicon wafer. Finally, the silicon wafer bolstered by the glass substrate is separated into individual silicon dice by dicing.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps or interconnect structures formed over an active surface of the die. The bumps can have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. A plurality of conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites under pressure or reflow temperature so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the die and substrate. The masking layer can form a dam to block the encapsulant from extending beyond the semiconductor die. Asperities can be formed over the interconnect sites or bumps.

Abstract: Methods, systems, and apparatuses for printing under bump metallization (UBM) features on chips/wafers are provided. A wafer is received that has a surface defined by a plurality of integrated circuit regions. Each integrated circuit region has a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer. A plurality of UBM features are formed on the surface of the wafer in the form of an ink such that each UBM feature is formed electrically coupled with a corresponding terminal of the plurality of terminals. An ink jet printer may be used to print the ink in the form of the UBM feature. A UBM feature may be formed directly on a corresponding terminal, or on routing that is coupled to the corresponding terminal. A bump interconnect may be formed on the UBM feature.

Abstract: A first circuit element and a second element are mounted with their electrode forming surfaces facing a wiring layer. A first bump electrode formed integrally with the wiring layer on one face substantially penetrates a first insulating resin layer. A gold plating layer covering an element electrode of the first circuit element and a gold plating layer disposed on top of the first bump electrode are bonded together by Au—Au bonding. A second bump electrode formed integrally with the wiring layer on one face substantially penetrates the first and the second insulating resin layer. A gold plating layer covering an element electrode of the second circuit element and a gold plating layer disposed on top of the second bump electrode are bonded together by Au—Au bonding.

Abstract: Structures, methods, and systems for assessing bonding of electrodes in FCB packaging are disclosed. In one embodiment, a method comprises mounting a semiconductor chip with a plurality of first electrodes of a first shape to a mounted portion with a second electrode of a second shape, wherein the second shape is different from the first shape, bonding a respective one of the plurality of first electrodes and the second electrode using a first solder bump, generating an X-ray image of the first solder bump, and determining an acceptability of the bonding of the respective one of the plurality of first electrodes and the second electrode based on the X-ray image of the first solder bump.

Abstract: An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body.

Abstract: A method of coupling an integrated circuit to a substrate includes providing the substrate, forming a contact pad in the substrate, contacting the contact pad with a solder ball, and repeatedly exposing the solder ball to a thermal process to cause intermetallics based on a metal in the contact pad to be formed in the thermal ball.

Abstract: A bump contact electrically connects a conductor on a substrate and a contact pad on a semiconductor device mounted to the substrate. The first end of an electrically conductive pillar effects electrical contact and mechanical attachment of the pillar to the contact pad with the pillar projecting outwardly from the semiconductor device. A solder crown reflowable at a predetermined temperature into effecting electrical contact and mechanical attachment with the conductor is positioned in axial alignment with the second end of the pillar. A diffusion barrier electrically and mechanically joins the solder bump to the second end of the pillar and resists electro-migration into the first end of the solder crown of copper from the pillar. One diffusion barrier takes the form of a 2-20 micron thick control layer of nickel, palladium, titanium-tungsten, nickel-vanadium, or tantalum nitride positioned between the pillar and the solder crown.

Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.

Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.

Abstract: An underfill film for an electronic device includes a thermally conductive sheet. The electronic device may include a printed circuit board, an electrical component, an underfill, and the thermally conductive sheet. The underfill is situated between the circuit board and the component. The thermally conductive sheet is situated within the underfill, and together with the underfill, constitutes the underfill film. The device may include solder bumps affixing the component to the circuit board, the underfill film having holes within which the solder bumps are aligned. There may be solder bumps on the underside of the circuit board promoting heat dissipation. There may be heat sinks on the circuit board to which the thermally conductive sheet is affixed promoting heat dissipation. The thermally conductive sheet may be affixed to a chassis promoting heat dissipation. The thermally conductive sheet thus promotes heat dissipation from the component to at least the circuit board.

Abstract: A semiconductor device includes a semiconductor layer, an electrode pad that is composed of Au and is provided on the semiconductor layer, a silicon nitride film provided on the semiconductor layer and the electrode pad so that an end portion of the silicon nitride film is located, and a metal layer that contacts a part of a surface of the electrode pad and the end portion of the silicon nitride film and is provided so that another part of the surface of the electrode pad is exposed, the metal layer including any of Ti, Ta and Pt.

Abstract: A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacent to an outer periphery of the LSI core section on the semiconductor substrate and including a plurality of wiring layers, a first pad electrode disposed at an outer periphery of the first rewiring layer, and an insulation layer covering the first pad electrode. The semiconductor device includes a second rewiring layer provided on the LSI chip and including a rewiring connected to the first pad electrode. The semiconductor device includes a plurality of ball electrodes provided on the second rewiring layer. The first rewiring layer is electrically connected to the LSI core section and the first pad electrode.

Abstract: An interconnection component includes a plurality of through-substrate vias (TSVs) penetrating through a substrate. The plurality of TSVs includes an active TSV having a first end and a second end. The first end of the active TSV is electrically coupled to a signal-providing circuit. The second end of the active TSV is electrically coupled to an additional package component bonded to the interconnection component. The plurality of TSVs further includes a dummy TSV having a first end and a second end, wherein the first end is electrically coupled to the signal-providing circuit, and wherein the second end is open ended.

Abstract: A manufacturing method of a bump structure with an annular support includes the following steps. A substrate including pads and a passivation layer is provided. The passivation has first openings exposing a portion of the pads. An UBM material layer is formed to cover the passivation layer and the pads. A patterned photoresist layer, having second openings respectively exposing the UBM material layer over the pads, is formed on the UBM material layer. A diameter of each second opening located on a lower surface of the patterned photoresist layer is less than that located on an upper surface of the patterned photoresist layer. Bumps are formed in the second openings. A portion of the patterned photoresist layer is removed to form an annular support at a periphery of each bump. The UBM material layer is patterned using the annular supports and the bumps as masks to form UBM layers.

Abstract: A semiconductor chip, an electrode structure and a method of manufacture, the chip including a semiconductor substrate having a multi-level interconnection and an electrode pad connected to the interconnection, a protective film on the substrate, an insulating film on the protective film, a bump of a metal on the electrode pad, and a barrier layer between the side of the bump and the insulation film.

Abstract: A semiconductor package includes a device pad on a substrate. A first polymer layer overlies the substrate, and the first polymer layer has an opening to expose the device pad. In one embodiment, a redistribution layer (RDL) comprises a landing pad, and the RDL is positioned on the first polymer layer and conductively coupled to the device pad. A second polymer layer is on the RDL, and an under bump metal pad (UBM) is on the landing pad and extends onto a top surface of the second polymer layer. In one embodiment, a shortest distance from a center of the landing pad to an outer edge of the landing pad, and a shortest distance from a center of the UBM to an outer edge of the UBM are in a ratio that ranges from 0.5:1 up to 0.95:1.

Abstract: A package structure, a method of fabricating the package structure, and a package-on-package device are provided, where the package structure includes a metal sheet having perforations and a semiconductor chip including an active surface having electrode pads thereon, where the semiconductor chip is combined with the metal sheet via an inactive surface thereof. Also, a protective buffer layer is formed on the active surface to cover the conductive bumps, and the perforations are arranged around a periphery of the inactive surface of the semiconductor chip. Further, an encapsulant is formed on the metal sheet and in the perforations, for encapsulating the semiconductor chip and exposing the protective buffer layer; and a circuit fan-out layer is formed on the encapsulant and the protective buffer layer and having conductive vias penetrating the protective buffer layer and electrically connecting to the conductive bumps.

Abstract: A semiconductor device has a semiconductor die with die bump pads and substrate with trace lines having integrated bump pads. A solder mask patch is formed interstitially between the die bump pads or integrated bump pads. The solder mask patch contains non-wettable material. Conductive bump material is deposited over the integrated bump pads or die bump pads. The semiconductor die is mounted over the substrate so that the conductive bump material is disposed between the die bump pads and integrated bump pads. The bump material is reflowed without a solder mask around the integrated bump pads to form an interconnect between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within a footprint of the die bump pads or integrated bump pads during reflow. The interconnect can have a non-fusible base and fusible cap.

Abstract: A semiconductor device according to the present invention includes a semiconductor chip having a front surface and a rear surface, a sealing resin layer stacked on the front surface of the semiconductor chip, a post passing through the sealing resin layer in the thickness direction and having a side surface flush with a side surface of the sealing resin layer and a forward end surface flush with a front surface of the sealing resin layer, and an external connecting terminal provided on the forward end surface of the post.