Abstract: In one embodiment, a method of forming a multi-die semiconductor device is provided. A plurality of dice is mounted on a semiconductor substrate, and neighboring ones of the dice are separated by a distance at which a first one of the neighboring dice will contact a meniscus of a flange of the neighboring die during underfill to form a capillary bridge between the neighboring dice. Solder bumps are reflowed to electrically connect contact terminals of the plurality of dice to contact terminals on a top surface of the substrate. Underfill is deposited along one or more edges of one or more of the plurality of dice. As a result of the capillary bridge formed between neighboring dice, flow of underfill is induced between the bottom surfaces of the neighboring dice and the top surface of the substrate. The dispensed underfill is cured.

Abstract: A low-profile microelectronic package includes a die (110) (having a first surface (111) and a second surface (112)) and a package substrate (120). The substrate includes an electrically insulating layer (121) that forms a first side (126) of the substrate, an electrically conductive layer (122) connected to the die, and a protective layer (123) over the conductive layer that forms a second side (127) of the substrate. The first surface of the die is located at the first side of the substrate. The insulating layer has a plurality of pads (130) formed therein. The package further includes an array of interconnect structures (140) located at the first side of the substrate. Each interconnect structure in the array of interconnect structures has a first end (141) and a second end (142), and the first end is connected to one of the pads.

Abstract: An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.

Abstract: A stacked-chip packaging structure includes chip sets, a heat sink, a substrate, a circuit board, and solder balls. The chip sets are stacked together, each of which has a heat-dissipation structure and a chip. The heat-dissipation structure has a chip recess, through holes arranged in the chip recess, and an extending portion extending from the chip recess. The chip disposed in the chip recess has bumps. Each bump on the chip is correspondingly disposed in one of the through holes of the heat-dissipation structure. The extending portion of the heat-dissipation structure of each chip set contacts that of the neighboring chip set. The heat sink and the substrate are disposed at two opposite sides of the chip sets, respectively. The circuit board is below the substrate. The solder balls are between the circuit board and the substrate.

Abstract: A semiconductor device (1700), which comprises a workpiece (1201) with an outline (1711) and a plurality of contact pads (1205) and further an external part (1701) with a plurality of terminal pads (1702). This part is spaced from the workpiece, and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element (1203) interconnects each of the contact pads with its respective terminal pad. Thermoplastic material (1204) fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline (1711) substantially in line with the outline of the workpiece, and fills the space (1707) substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.

Abstract: A semiconductor package includes a device pad on a substrate. A polybenzoxazole (PBO) layer overlies the substrate, and the PBO layer has an opening to expose the device pad. A redistribution layer (RDL) comprises a landing pad, and the RDL is positioned on the PBO layer and conductively coupled to the device pad. A polymer layer is on the RDL, and an under bump metal pad (UBM) is on the landing pad and extends onto a top surface of the polymer layer. The UBM electrically connects to the landing pad through an opening in the polymer layer. A solder bump is secured to the UBM. A shortest distance from a center of the landing pad to an outer edge of the landing pad, and a shortest distance from a center of the UBM to an outer edge of the UBM are in a ratio that ranges from 0.5:1 up to 0.95:1.

Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.

Abstract: Micro-addition of a metal to a Sn-based lead-free C4 ball is employed to enhance reliability. Specifically, a metal having a low solubility in Sn is added in a small quantity corresponding to less than 1% in atomic concentration. Due to the low solubility of the added metal, fine precipitates are formed during solidification of the C4 ball, which act as nucleation sites for formation multiple grains in the solidified C4 ball. The fine precipitates also inhibit rapid grain growth by plugging grain boundaries and act as agents for pinning dislocations in the C4 ball. The grain boundaries enable grain boundary sliding for mitigation of stress during thermal cycling of the semiconductor chip and the package on the C4 ball. Further, the fine precipitates prevent electromigration along the grain boundaries due to their pinned nature.

Abstract: A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode 4 independently of each other. Bumps 11 (the diameter is from several tens to several hundreds of ?m) are formed only on the external output electrodes 4 of non-defective units among the units 10 formed on the SiC chip 9, meanwhile bumps are not formed on the external output electrodes 4 of defective units in which the withstand voltage is too low, or the leakage current is too much.

Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

Abstract: A semiconductor device includes a first structural body having a first surface and a second surface which faces away from the first surface, and formed with first electrode pads on the first surface, a stress buffer layer formed on the first electrode pads and the first surface of the first structural body, and having a plurality of holes which expose the first electrode pads, and a plurality of bumps formed to be electrically connected with the first electrode pads through the plurality of holes, wherein the plurality of bumps include first bumps which are filled in corresponding holes of the plurality of holes and second bumps which are formed on the first bumps and the stress buffer layer and are disposed over the first electrode pads and portions of the first surface outside the first electrode pads.

Abstract: Provided is a semiconductor device having a substrate, a semiconductor chip flip-chip mounted on the substrate, and a stacked film provided in a gap between the substrate and the semiconductor chip. The stacked film is composed of a protective film covering the surface of the substrate, and an underfill film formed between the solder resist film and the semiconductor chip. The protective film is roughened on the contact surface brought into contacting said underfill film.

Abstract: According to an embodiment, a chip-on-chip structure includes a first chip, a second chip, the first chip and the second chip being opposite to each other, a first electrode terminal, a second electrode terminal, a bump and a protecting material. The first electrode terminal is provided on the surface of the first chip at the side of the second chip. The second electrode terminal is provided on the surface of the second chip at the side of the first chip. The bump electrically connects the first electrode terminal and the second electrode terminal. The protecting material is formed around the bump between the first chip and the second chip. The protecting material includes a layer made of a material having heat-sensitive adhesive property.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.

Abstract: A method for making a microelectronic assembly includes providing a microelectronic element with first conductive elements and a dielectric element with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts and other of the first or second conductive elements may include a bond metal disposed between some of the conductive posts. An underfill layer may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer and at least deform the bond metal. The microelectronic element and the dielectric element can be heated to join them together. The height of the posts above the surface may be at least forty percent of a distance between surfaces of the microelectronic element and dielectric element.

Abstract: [Problem] A semiconductor device which achieves a fine pitch, a high throughput and a high connection reliability, especially in flip-chip mounting is provided. A method for manufacturing the semiconductor device and a circuit device using the semiconductor device are also provided. [Means for solving the problem] The semiconductor device has: an electrode; an insulating part having an opening on the electrode; a protruding part formed on the electrode; a protecting part which is formed at the periphery of the protruding part and electrically isolates the protruding part; and a bonding part which is formed on the protecting part by being spaced apart from the protruding part. An upper surface of the protruding part, an upper surface of the protecting part, and an upper surface of the bonding part form the same plane.

Abstract: It is described a bond pad structure and a method for producing the same, the bond pad structure (1), comprising: a substrate (3) having a surface (17) to be electrically contacted; a first isolator layer (5) contacting the surface (17) of the substrate in a first region (a); a first metal layer (9) contacting the surface (17) of the substrate (3) in a second region (b) adjacent the first region (a) and partly overlapping the first isolator layer (5); a second isolator layer (11) at least partly overlapping the first isolator layer (5) and the first metal layer (9); a second metal layer (13) at least partly overlapping the second isolator layer (11) in the second region (b); wherein a maximum thickness (U) of the second metal layer (13) perpendicular to the surface (17) of the substrate (3) is smaller than a maximum thickness (t0) of the first isolator layer (5) perpendicular to the surface (17) of the substrate (3).

Abstract: A semiconductor chip package and a method for manufacturing thereof includes sequentially forming upper dielectric layer patterns and lower dielectric patterns over a substrate to expose an underlying metal line such that the lower dielectric layer patterns overlap the metal line, positioning a solder ball over and contacting the lower dielectric layer patterns such that the solder ball does not contact the metal line, and then placing the solder ball in a contacting position over the metal line by performing an etching process on the lower dielectric layer patterns. Therefore, no cracks occur on the chip pads so that there is no concern of short phenomenon generated in the terminal.

Abstract: Methods and apparatuses for improved thermal, electrical and/or mechanical performance in integrated circuit (IC) packages are described. An IC circuit package comprises a substrate having a central opening. An IC die, resides within the opening in the substrate. Wirebonds couples a plurality of bond pads on a top surface of the IC die to a plurality of bond fingers on a top surface the substrate. An encapsulating material encapsulates at least the IC die and the wirebonds such that at least a bottom surface of the IC die is left exposed. The encapsulating material suspends the die such that at least a portion of the die is held within the opening in the substrate.

Abstract: A low-stress chip package is disclosed. The package includes two substrates. The first substrate includes an array of first conductive structures in the corner area of the chip, and an array of second conductive structures in the peripheral edge area of the chip. The first and second conductive structures each has a conductive pillar having elongated cross section in the plane parallel to the first substrate and a solder bump over the pillar. The package also includes a second substrate having an array of metal traces. The elongated pillars each form a coaxial bump-on-trace interconnect with a metal trace respectively. The long axis of the elongated cross section of a pillar in the corner area of the chip points to chip's center area, and the long axis of the elongated cross section of a pillar in chip's peripheral edge area aligns perpendicular to the edge.

Abstract: A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers.

Abstract: A method of making a multi-chip module may include forming an interconnect layer stack on a sacrificial substrate. The interconnect layer stack may include patterned electrical conductor layers and a dielectric layer between adjacent patterned electrical conductor layers. The method may further include electrically coupling a first integrated circuit (IC) die in a flip chip arrangement to an uppermost patterned electrical conductor layer, and forming a first underfill dielectric layer between the first IC die and adjacent portions of the interconnect layer stack. The method further may include removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at a second integrated circuit die in a flip chip arrangement to the lowermost patterned electrical conductor layer. Still further, the method may include forming a second underfill dielectric layer between the second IC die and adjacent portions of the interconnect layer stack.

Abstract: A method comprises depositing a first metal containing layer into a trench structure, which contacts a metalized area of a semiconductor structure. The method further includes patterning at least one opening in a resist to the first metal containing layer. The opening should be in alignment with the trench structure. At least a pad metal containing layer is formed within the at least one opening (preferably by electroplating processes). The resist and the first metal layer underlying the resist are then etched (with the second metal layer acting as a mask, in embodiments). The method includes flowing solder material within the trench and on pad metal containing layer after the etching process. The structure is a controlled collapse chip connection (C4) structure comprising at least one electroplated metal layer formed in a resist pattern to form at least one ball limiting metallurgical layer. The structure further includes an underlying metal layer devoid of undercuts.

Abstract: A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A first insulating layer is formed over the die. A recessed region with angled sidewall is formed in the peripheral area. A first conductive layer is formed over the first insulating layer outside the recessed region and further into the recessed region. A conductive pillar is formed over the first conductive layer within the recessed region. A second insulating layer is formed over the first insulating layer, conductive pillar, and first conductive layer such that the conductive pillar is exposed from the second insulating layer. A dicing channel partially through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the conductive pillar.

Abstract: The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate having an opening over the contact pad; and a conductive pillar over the opening of the passivation layer, wherein the conductive pillar comprises an upper portion substantially perpendicular to a surface of the substrate and a lower portion having tapered sidewalls.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, at least one first chip, a dielectric layer and at least one second chip. The first chip is attached and electrically connected to the substrate. The first chip includes a first active surface and a plurality of first signal coupling pads. The first signal coupling pads are disposed adjacent to the first active surface. The dielectric layer is disposed on the first active surface. The second chip is attached and electrically connected to the substrate by metal bumps. The second chip includes a second active surface and a plurality of second signal coupling pads. The second active surface contacts the dielectric layer. The second signal coupling pads are disposed adjacent to the second active surface, and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip.

Abstract: A semiconductor device according to this embodiment has an electrode (electrode pad) and an insulative film (protective resin film) formed on the electrode and having an opening for exposing the electrode. The semiconductor device further has an under bump metal (UBM layer) formed over the insulative film and connected with the electrode through the opening, and a solder ball formed over the under bump metal, and the contour line at the lower end of the solder ball is situated inside the contour line of the under bump metal, whereby generation of fracture in the insulative film caused by the stress upon mounting the semiconductor device is suppressed even when the solder ball is formed of a lead-free solder.

Abstract: The present invention relates to a stacked semiconductor package and a method for making the same. The method includes the steps of: forming and curing a first protective layer to cover a plurality of first bumps of a first wafer; cutting the first wafer to form a plurality of first dice; forming a third protective layer to cover a plurality of second bumps of a second wafer; picking up the first dice through the first protective layer, and bonding the first dice to the second wafer; removing part of the first protective layer; cutting the second wafer to form a plurality of second dice; and bonding the first dice and the second dice to a substrate. Whereby, the first protective layer can protect the first bumps, and the first protective layer can increase the total thickness and the flatness.

Abstract: A semiconductor device includes an insulating film base member and a wiring pattern that is formed on the insulating film base member. The wiring pattern has a surface, with at least a peripheral section of the surface being a peeled surface of the wiring pattern peeled from the insulating film base member. The semiconductor device further includes a plating layer that covers the surface of the wiring pattern, and an IC chip that has an active surface with a bump bonded to the wiring pattern. The peeled surface of the wiring pattern is peeled from the insulating film base member around a bonding position of the wiring pattern bonded with the bump.

Abstract: Provided is a semiconductor package and a method of fabricating the same. The semiconductor package includes: a package body including a plurality of sheets; semiconductor chips mounted in the package body; and an external connection terminal provided on a first side of the package body, wherein the sheets are stacked in a parallel direction to the first side.

Abstract: An integrated circuit (IC) includes a substrate having a semiconducting surface, a first array of devices on and in the semiconducting surface including first and second coacting current conducting nodes, a plurality of layers disposed on the substrate and including at a electrically conductive layers and dielectric layer, and a plurality of bump pads on or in the top surface of the dielectric layers. In the IC, the electrically conductive layers define electrical traces, where a first portion of the electrical traces contact a first portion of the bump pads exclusively to a portion of the first coacting current conducting nodes, where a second portion of the electrical traces contact a second portion of the bump pads exclusively to a portion of the second coacting current conducting nodes, and where the electrical traces are electrically isolated from one another by the dielectric layers.

Abstract: A semiconductor chip has a main surface, a back surface and a plurality of side surfaces. A plurality of electrodes is provided on the main surface of the semiconductor chip so as to be arranged in a plurality of lines. An insulating film is formed on the main surface of the semiconductor chip so as to expose at least one of the plurality of electrodes. A plurality of leads are formed on the insulating film, each of the plurality of leads having a first end and a second end, and the first end of the lead being connected to the one of the plurality of electrodes. A base resin film is formed on the insulting film and the plurality of leads, the base resin film having a plurality of electrodes holes exposing a part of the second end of each of the leads and a device hole in which the first end of the lead and the one of the plurality of electrodes are located.

Abstract: Disclosed is a semiconductor device 1 comprising: a semiconductor chip 10; a multilayer wiring structure 30 stacked on the semiconductor chip 10; and an electronic component 60,80 embedded in the multilayer wiring structure 30.

Abstract: A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a top surface, a bottom surface and a plurality of apertures formed at the bottom surface, wherein the bottom surface of the insulating layer comprises a disposing area and a non-disposing area. Each of the apertures is located at the disposing area and comprises a lateral wall and a base surface. A first thickness is formed between the base surface and the insulating layer, a second thickness is formed between the top surface and the bottom surface, and the second thickness is larger than the first thickness. The chip disposed on the top surface comprises a chip surface and a plurality of bumps. The heat dissipation paste at least fills the apertures and contacts the base surface.

Abstract: An opening is formed in a part of a rear protective film corresponding to the center of a dicing street by laser processing which applies a laser beam. The rear protective film is formed on the lower surface of a semiconductor wafer, and made of a resin. By using a resin cutting blade, parts of a sealing film and the upper side of the semiconductor wafer corresponding to the dicing street and both its sides are then cut to form a trench. By using a silicon cutting blade, parts of the semiconductor wafer and the rear protective film corresponding to the dicing street are then cut. In this case, cutting of the rear protective film with the silicon cutting blade is reduced by the opening.

Abstract: A device includes an interposer free from active devices therein. The interposer includes a substrate; a through-substrate via (TSV) penetrating through the substrate; and a low-k dielectric layer over the substrate.

Abstract: This invention relates to a packaging structure and method for manufacturing the packaging structure. The packaging structure comprises a substrate film, a plurality of chips, a compound resin layer and a support layer. The substrate film is formed with circuits having a plurality of terminals exposed from a solder mask. The chips, each of which has a plurality of pads, under bump metals (UBMs) formed on the pads, and composite bumps disposed onto the UBMs, are bonded onto the substrate film to form the first tape. The second tape comprises the support layer and the compound resin layer formed on the support layer. The first tape and the second tape are both in reel-form and are expanded towards a pair of rollers to be heated and pressurized for encapsulating the chips.

Abstract: The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation layer pattern, a second insulation layer pattern disposed on only a portion of the first insulation layer pattern, and redistribution line patterns electrically connected to the pads and disposed so as to extend across the second insulation layer pattern and the first insulation layer pattern. A method of fabricating the same is also provided.

Abstract: A method for manufacturing a semiconductor device includes: (a) forming a stress relaxation layer on a first surface having an electrode of a semiconductor substrate; (b) forming a wiring line so as to cover the electrode and the stress relaxation layer after step (a); (c) forming a solder resist layer on the wiring line after step (b); and (d) forming a protective layer on a second surface opposite to the first surface of the semiconductor substrate after step (c).

Abstract: An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed by forming a conductive layer (34, 46) over an encapsulant (32). The conductive layer includes a combination of a conductive glue (38, 48, 52) and a metal paint (36, 50). A wire loop (30) is coupled to the conductive layer and a leadframe (10).

Abstract: A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole.

Abstract: A semiconductor die has a conductive layer including a plurality of trace lines formed over a carrier. The conductive layer includes a plurality of contact pads electrically continuous with the trace lines. A semiconductor die has a plurality of contact pads and bumps formed over the contact pads. A plurality of conductive pillars can be formed over the contact pads of the semiconductor die. The bumps are formed over the conductive pillars. The semiconductor die is mounted to the conductive layer with the bumps directly bonded to an end portion of the trace lines to provide a fine pitch interconnect. An encapsulant is deposited over the semiconductor die and conductive layer. The conductive layer contains wettable material to reduce die shifting during encapsulation. The carrier is removed. An interconnect structure is formed over the encapsulant and semiconductor die. An insulating layer can be formed over the conductive layer.

Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a through silicon via (TSV) that is formed so that at least a part thereof penetrates through the semiconductor substrate, and an insulation ring. The insulation ring is formed so as to penetrate through the semiconductor substrate and so as to surround the TSV. The insulation ring includes a tapered portion and a vertical portion. The tapered portion has a sectional area which is gradually decreased from the first surface toward a thickness direction of the semiconductor substrate. The vertical portion has a constant sectional area smaller than the tapered portion.

Abstract: In one embodiment, a collar structure includes a non-conductive layer that relieves stress around the perimeter of each of the solder balls that connect the semiconductor die to the semiconductor chip package substrate, and another non-conductive layer placed underneath to passivate the entire surface of the die.

Abstract: Disclosed herein are an embedded ball grid array substrate and a manufacturing method thereof. The embedded ball grid array includes: a core layer having a cavity therein; a semiconductor device embedded in the cavity of the core layer; a first circuit layer having a circuit pattern including a wire bonding pad formed thereon; a second circuit layer having a circuit pattern including a solder ball pattern formed thereon; and a wire electrically connecting the semiconductor device to the wire bonding pad.

Abstract: An embedded package includes a first semiconductor chip having a first conductive line which has a first sunken area, a second semiconductor chip having a second conductive line which has a second sunken area, wherein the first semiconductor chip and the second semiconductor chip are arranged facing each other, and wherein the first sunken area and the second sunken area are arranged facing each other, a core layer surrounding the first semiconductor chip and the second semiconductor chip, wherein the core layer has a first circuit pattern coupled to an external terminal; and a bump formed in the first and second sunken areas, wherein the bump is coupled to the first circuit pattern.

Abstract: A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

Abstract: According to one embodiment, there is provided a semiconductor device including a semiconductor element, an electrode pad of the semiconductor element, a buffer coat film, and a micro-bump. The buffer coat film has an opening corresponding to the electrode pad. The micro-bump is electrically connected to the electrode pad through the opening. A contact area between the micro-bump and side surfaces of the opening is larger than a contact area between the micro-bump and a bottom surface of the opening.

Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. Wettable contact pads can be formed over the carrier. A second semiconductor die is mounted over the first semiconductor die. The second die is laterally offset with respect to the first die. An electrical interconnect is formed between an overlapping portion of the first die and second die. A plurality of first conductive pillars is disposed over the first die. A plurality of second conductive pillars is disposed over the second die. An encapsulant is deposited over the first and second die and first and second conductive pillars. A first interconnect structure is formed over the encapsulant, first conductive pillars, and second die. The carrier is removed. A second interconnect structure is formed over the encapsulant, second conductive pillars, and first die. A third conductive pillar is formed between the first and second build-up interconnect structures.