Cross-section Geometry (epo) Patents (Class 257/E23.046)
  • Patent number: 10264671
    Abstract: Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers, a cavity formed in at least one organic dielectric layer of the plurality of organic dielectric layers and a modular structure having first and second ports and a conductive member that is formed within the cavity. The conductive member provides modularity by being capable of connecting the first and second ports and also disconnecting the first and second ports.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventor: Feras Eid
  • Patent number: 9806006
    Abstract: Various structures and fabrication methods for leadless plastic chip carrier (QFN) packages which utilize carriers in strip format, wherein the leads (or terminals) are formed to be electrically isolated from one another within each unit and in which the units are formed to be electrically isolated from one another within the strip using chemical etching techniques.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: October 31, 2017
    Assignee: UTAC HEADQUARTERS PTD. LTD.
    Inventors: Tung Lok Li, Kin Pui Kwan
  • Patent number: 8921985
    Abstract: A semiconductor device includes: a semiconductor chip including a main surface electrode; a first mounting lead; a second mounting lead; a connection lead which overlaps with the main surface electrode, the first mounting lead and the second mounting lead when viewed in a thickness direction of the semiconductor chip and makes electrical conduction between the main surface electrode, the first mounting lead and the second mounting lead; and a resin portion which covers the semiconductor chip, the first mounting lead and the second mounting lead, wherein the resin portion has a resin bottom lying on the same plane as a bottom of the first mounting lead and a bottom of the second mounting lead.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: December 30, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Koshun Saito
  • Patent number: 8884413
    Abstract: A leadframe (e.g., incorporated in a device package) includes a feature (e.g., a die pad or lead) with a vent hole formed between first and second opposed surfaces. The cross-sectional area of the vent hole varies substantially between the surfaces (e.g., the vent hole has a constricted portion). The vent hole may be formed from a first opening extending from the first surface toward the second surface to a first depth that is less than a thickness of the leadframe feature, and a second opening extending from the second surface toward the first surface to a second depth that is less than the thickness of the leadframe feature, but that is large enough for the second opening to intersect the first opening. Vertical central axes of the openings are horizontally offset from each other, and the constricted portion of the vent hole corresponds to the intersection of the openings.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Philip H. Bowles, Stephen R. Hooper
  • Patent number: 8878361
    Abstract: A leadless package system includes: an integrated circuit die having contact pads; external contact terminals with a conductive layer and an external coating layer; connections between contact pads in the integrated circuit die and the external contact terminals; and an encapsulant encapsulates the integrated circuit die and the external contact terminals including the external coating layer.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: November 4, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Linda Pei Ee Chua, Heap Hoe Kuan
  • Patent number: 8853694
    Abstract: Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Uk Han, Jeong-Kyu Ha, Young-Shin Kwon, Seung-Hwan Kim, Kwan-Jai Lee
  • Patent number: 8836093
    Abstract: The present invention relates to the field of semiconductor chip packages, and more specifically to a lead frame and flip chip package device thereof. In one embodiment, a lead frame for electrically connecting a chip to outside leads, can include a plurality of lead fingers, where each of the plurality of lead fingers comprises a plurality of outburst regions extending from an edge thereof. In one embodiment, a flip chip package device can include: a chip and a plurality of solder bumps, where one surface of the chip is connected to a first surface of each of the plurality of solder bumps; and the lead frame, where second surfaces of each of the plurality solder bumps are connected with corresponding outburst regions of the lead frame to connect the chip to the lead frame through the solder bumps.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: September 16, 2014
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
    Inventor: Xiaochun Tan
  • Patent number: 8803303
    Abstract: In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur.
    Type: Grant
    Filed: December 25, 2013
    Date of Patent: August 12, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Koichi Kanemoto
  • Patent number: 8772923
    Abstract: A semiconductor device includes: leads (5) in each of which a cutout (5a) is formed; a die pad (11); a power element (1) held on the die pad (11); and a package (6) made of a resin material, and configured to encapsulate inner end portions of the leads (5), and the die pad (11) including the power element (1). The cutout (5a) is located in a region of each of the leads (5) including a portion of the lead (5) located at a boundary between the lead (5) and the package (6), and is filled with a resin material.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: July 8, 2014
    Assignee: Panasonic Corporation
    Inventor: Masanori Minamio
  • Patent number: 8759955
    Abstract: Conventional semiconductor devices have a problem that it is difficult to prevent the short circuit between chips and to improve accuracy in temperature detection with the controlling semiconductor chips. In a semiconductor device of the present invention, a first mount region to which a driving semiconductor chip is fixedly attached and a second mount region to which a controlling semiconductor chip is fixedly attached are formed isolated from each other. A projecting area is formed in the first mount region, and the projecting area protrudes into the second mount region. The controlling semiconductor chip is fixedly attached to the top surfaces of the projecting area and the second mount region by use of an insulating adhesive sheet material. This structure prevents the short circuit between the two chips, and improves accuracy in temperature detection with the controlling semiconductor chip.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: June 24, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Hideyuki Iwamura, Isao Ochiai
  • Patent number: 8742552
    Abstract: The semiconductor device according to the present invention includes a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead arranged around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package collectively sealing the semiconductor chip, the island, the lead and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: June 3, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Akihiro Koga, Taro Nishioka
  • Patent number: 8703535
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a warpage-compensation zone with a substrate-interior layer exposed from a top substrate-cover, and the warpage-compensation zone having contiguous exposed portion of the substrate-interior layer over corner portions of the package substrate; connecting an integrated circuit die to the package substrate with an internal interconnect; and forming an encapsulation over the integrated circuit die, with the encapsulation directly on the substrate-interior layer in the warpage-compensation zone.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: April 22, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: MinJung Kim, DaeSik Choi, MinWook Yu, YiSu Park
  • Patent number: 8698187
    Abstract: A light emitting device comprises a case having a space therein, the space defined by an inner bottom surface and an inner side surface of the case, a lead frame housed in the space, and having a bending portion bent along the inner side surface of the case, and a light emitting element electrically connected to the lead frame, wherein a rear surface of the bending portion is embedded in the case and a front surface of the bending portion is exposed from the inner side surface of the case so as to oppose the light emitting element, and wherein a projecting portion projected from the inner bottom surface and inclined to the inner side surface of the case is formed on the inner side surface of the case.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: April 15, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Hideki Kokubu, Kosei Fukui, Toshimasa Hayashi
  • Patent number: 8674487
    Abstract: A semiconductor package with a die pad, a die disposed on the die pad, and a first lead disposed about the die pad. The first lead includes a contact element, an extension element extending substantially in the direction of the die pad, and a concave surface disposed between the contact element and the extension element. A second lead having a concave surface is also disposed about the die pad. The first lead concave surface is opposite in direction to the second lead concave surface.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: March 18, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Lin-Wang Yu, Ping-Cheng Hu, Che-Chin Chang, Yu-Fang Tsai
  • Patent number: 8643158
    Abstract: A semiconductor package is assembled using first and second lead frames. The first lead frame includes a die flag and the second lead frame includes lead fingers. When the first and second lead frames are mated, the lead fingers surround the die flag. Side surfaces of the die flag are partially etched to form an extended die attach surface on the die flag, and portions of the top surface of each of the lead fingers also are partially etched to form lead finger surfaces that are complementary with the etched side surfaces of the die flag. A semiconductor die is attached to the extended die attach surface and bond pads of the semiconductor die are electrically connected to the lead fingers. An encapsulating material covers the die, electrical connections, and top surfaces of the die flag and lead fingers.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Peng Liu, Qingchun He, Ping Wu
  • Patent number: 8637976
    Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 28, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Kazutaka Shibata
  • Patent number: 8637965
    Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: January 28, 2014
    Assignees: Renesas Electronics Corporation, Hitachi Yonezawa Electronics Co., Ltd
    Inventor: Yoshihiko Shimanuki
  • Patent number: 8637966
    Abstract: In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: January 28, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Koichi Kanemoto
  • Patent number: 8629537
    Abstract: An integrated circuit package system is provided forming a die support system from a padless lead frame having die supports with each substantially equally spaced from another, and attaching an integrated circuit die having a peripheral area on the die supports.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: January 14, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 8629549
    Abstract: A carrier body for a semiconductor component, in particular for an optoelectronic semiconductor component, is specified. Said carrier body has a connecting layer and a conductor layer, which are connected to one another via main areas facing one another. The connecting layer, the conductor layer or both the connecting layer and the conductor layer has/have at least one thinned region in which the layer thickness of said layer(s) is less than the maximum layer thickness of said layer(s). The connecting layer is either completely electrically conductive and electrically insulated at least from parts of the conductor layer or it is electrically insulating at least in parts. Furthermore, a semiconductor component comprising the electrical connection conductor and also a method for producing the carrier body are specified.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: January 14, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Michael Zitzlsperger, Stefanie Marion Muetzel
  • Patent number: 8592967
    Abstract: A semiconductor apparatus comprising an integrated semiconductor circuit device having pluralities of electrode pads, pluralities of first external terminals connected to the electrode pads of the integrated semiconductor circuit device, an inductor disposed in a region surrounded by the first external terminals, and a resin portion sealing them, the integrated semiconductor circuit device being arranged on an upper surface of the inductor, and the inductor being exposed from a lower surface of the resin portion together with the first external terminals.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: November 26, 2013
    Assignee: Hitachi Metals, Ltd.
    Inventor: Tohru Umeno
  • Patent number: 8587099
    Abstract: A metal leadframe strip (500) for semiconductor devices is described. The leadframe strip has a plurality of sites (510) for assembling semiconductor chips. The sites alternate with zones (520) for connecting the leadframe to molding compound runners. The sites (510) have mechanically rough and optically matte surfaces (511, 512). The zones (520) have at least portions with mechanically flattened and optically shiny metal surfaces (521, 522). The flattened surface portions transition into the rough surface portions by a step.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: November 19, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Donald C. Abbott
  • Patent number: 8519525
    Abstract: A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: August 27, 2013
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Anup Bhalla, Jun Lu
  • Patent number: 8502357
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package lead having a retention structure around a perimeter of the package lead with a first concave surface, a ridge, and a second concave surface; forming a die attach paddle adjacent the package lead and having an another retention structure around a perimeter of the die attach paddle with an another first concave surface, an another ridge, and an another second concave surface; attaching an integrated circuit die to the die attach paddle; connecting a conductive connector to the integrated circuit die and the package lead; and applying an encapsulation over the integrated circuit die, the encapsulation conformed to the retention structure and exposing a portion of the package lead.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: August 6, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Patent number: 8502359
    Abstract: The semiconductor device according to the present invention includes a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead arranged around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package collectively sealing the semiconductor chip, the island, the lead and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: August 6, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Akihiro Koga, Taro Nishioka
  • Patent number: 8476746
    Abstract: A leadframe enhancing molding compound bondability includes a chip base and a pin holder. The chip bases includes a chip pad and a support, wherein the chip pad includes a side protrusion extending out of the support, and the side protrusion has a lower surface, and the support has a sidewall, and wherein the lower surface and the sidewall interconnect at an intersection line, and the lower surface is formed upwardly with a recess. Further, a pin holder includes a pin stand and a seat, wherein the pin stand has an edge portion extending out of the seat, the edge portion has a lower surface, the seat has a sidewall, and the lower surface and the sidewall interconnect at a crossing line. The lower surface of the pin stand is formed upward with a recess. As such, the bondability between the leadframe and the molding compound can be greatly enhanced.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: July 2, 2013
    Assignee: Kun Yuan Technology Co., Ltd.
    Inventors: Cheng-Yu Hsia, Chiao-Jung Yeh
  • Patent number: 8471381
    Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 25, 2013
    Assignee: Vishay-Siliconix
    Inventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
  • Patent number: 8421209
    Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: April 16, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Kazutaka Shibata
  • Patent number: 8405230
    Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: March 26, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jae Soo Lee, Geun Sik Kim, Sheila Marie L. Alvarez, Robinson Quiazon, Hin Hwa Goh, Frederick Rodriguez Dahilig
  • Patent number: 8330258
    Abstract: A system and method is disclosed for improving solder joint reliability in an integrated circuit package. Each terminal of a quad, flat, non-leaded integrated circuit package is formed having portions that define a solder slot in the bottom surface of the terminal. An external surface of the die pad of the integrated circuit package is also formed having portions that define a plurality of solder slots on the periphery of the die pad. When solder is applied to the die pad and to the terminals, the solder that fills the solder slots increases the solder joint reliability of the integrated circuit package.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: December 11, 2012
    Assignee: STMicroelectronics, Inc.
    Inventors: Anthony M. Chiu, Tong Yan Tee
  • Patent number: 8212343
    Abstract: A semiconductor chip package comprises a lead frame having a chip carrier having a first surface and an opposite second surface. A first semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the first semiconductor chip has an area larger that that of the chip carrier. A package substrate has a central region attached to the second surface of the chip carrier, having an area larger than that of the first semiconductor chip, wherein the package substrate comprises a plurality of fingers on a top surface thereof in a marginal region of the package substrate, which are arranged in an array with a row of inner fingers adjacent to the first semiconductor chip and a row of outer fingers adjacent to an edge of the package substrate, wherein the inner and outer fingers are electrically connected to the bonding pads of the first semiconductor chip and the lead frame respectively.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: July 3, 2012
    Assignee: Mediatek Inc.
    Inventor: Nan-Jang Chen
  • Patent number: 8203220
    Abstract: A method for manufacturing an integrated circuit package system includes: forming a first device unit, having first external interconnects arranged along a perimeter of the first device unit, and a second device unit, having second external interconnects arranged along a perimeter of the second device unit, in an array configuration; mounting an integrated circuit die over the first device unit; connecting the integrated circuit die and the first external interconnects; encapsulating with an encapsulation covering the integrated circuit die, the first device unit, and the second device unit with both the first external interconnects and the second external interconnects partially exposed; and forming a partial encapsulation cut in the encapsulation electrically isolating the first external interconnects and the second electrical interconnects.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: June 19, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Lionel Chien Hui Tay, Zigmund Ramirez Camacho, Jeffrey D. Punzalan, Arnel Trasporto
  • Patent number: 8106490
    Abstract: A semiconductor chip package comprises a lead frame having a chip carrier having a first surface and an opposite second surface. A first semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the first semiconductor chip has an area larger that that of the chip carrier. A package substrate has a central region attached to the second surface of the chip carrier, having an area larger than that of the first semiconductor chip, wherein the package substrate comprises a plurality of fingers on a top surface thereof in a marginal region of the package substrate, which are arranged in an array with a row of inner fingers adjacent to the first semiconductor chip and a row of outer fingers adjacent to an edge of the package substrate, wherein the inner and outer fingers are electrically connected to the bonding pads of the first semiconductor chip and the lead frame respectively.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: January 31, 2012
    Assignee: Mediatek Inc.
    Inventor: Nan-Jang Chen
  • Patent number: 8102040
    Abstract: An integrated package system with die and package combination includes forming a leadframe having internal leads and external leads, encapsulating a first integrated circuit on the leadframe, and encapsulating a second integrated circuit over the first integrated circuit.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: January 24, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Ming Ying, Il Kwon Shim
  • Patent number: 8089166
    Abstract: An integrated circuit package system includes a bottom pad with a bottom tie bar, attaching an integrated circuit die over the bottom pad, attaching a top pad with a top tie bar, over the integrated circuit die, and applying an encapsulant wherein the top tie bar integral to the top pad, is exposed on a side of the encapsulant.
    Type: Grant
    Filed: December 30, 2006
    Date of Patent: January 3, 2012
    Assignee: Stats Chippac Ltd.
    Inventor: OhSug Kim
  • Patent number: 8080883
    Abstract: A longest wiring and a shortest wiring alongside each other among the plurality of wirings are placed. Then, a longest wiring from among remaining wires which have not being placed yet, alongside an outside of a space surrounded by the wirings already placed and on a side of a shorter wiring of the wrings placed at outermost ends are placed. A shortest wiring from among remaining wires which have not placed yet, alongside an outside of a space surrounded by the wirings already placed and on a side of a longer wiring of the wirings placed at outermost ends is placed. These two processes are repeated.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: December 20, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Tamotsu Watarai
  • Patent number: 8067821
    Abstract: In accordance with the present invention, there are provided multiple embodiments of a semiconductor package, each embodiment including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, each embodiment of the semiconductor package of the present invention includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads, the exposed portions of the bottom surfaces of which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of both rows thereof being exposed in a common exterior surface of the package body.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: November 29, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: YeonHo Choi, Timothy L. Olson
  • Patent number: 8067271
    Abstract: An integrated circuit package system is provided including forming an external interconnect and a tie bar, forming a lead tip and a lead body of the external interconnect, forming a hole in the external interconnect, forming a slot in the tie bar, connecting an integrated circuit die and the external interconnect, and molding the external interconnect and the tie bar with the slot and the hole filled.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Sung Uk Yang
  • Patent number: 8026591
    Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: September 27, 2011
    Assignee: Rohm Co., Ltd.
    Inventor: Kazutaka Shibata
  • Patent number: 8022514
    Abstract: An integrated circuit package system including forming a leadframe having a lead with a leadfinger support of a predetermined height, and attaching an integrated circuit die with an electrical interconnect at a predetermined collapse height determined by the predetermined height of the leadfinger support.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: September 20, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Arnel Senosa Trasporto, Jeffrey D. Punzalan
  • Patent number: 8018041
    Abstract: An integrated circuit package system provides a leadframe having a short lead finger and a long lead finger, and the long lead finger and the short lead finger reside substantially within the same horizontal plane. A first die is placed in the leadframe. A second die is offset from the first die. The offset second die is attached over the first die and the long lead finger with an adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: September 13, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan
  • Patent number: 7993979
    Abstract: A leadless package system includes: providing a chip carrier having indentations defining a pattern for a protrusion for external contact terminals; placing an external coating layer in the indentations in the chip carrier; layering a conductive layer on top of the external coating layer; depositing an internal coating layer on the conductive layer; patterning the internal coating layer and the conductive layer to define external contact terminals with a T-shape profile; connecting an integrated circuit die to the external contact terminals; encapsulating the integrated circuit die and external contact terminals; and separating the chip carrier from the external coating layer.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: August 9, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Linda Pei Ee Chua, Heap Hoe Kuan
  • Patent number: 7972906
    Abstract: A clip structure and semiconductor die package. The clip structure includes a first portion and a second portion, with a connecting structure located between the first and second portion. The clip structure is substantially planar. The semiconductor die package includes a semiconductor die located between a leadframe structure and a clip structure. Slots are formed within the molding material covering portions of the semiconductor die package. The slots are located between a first portion and the second portion of the clip structure, and the slot overlap with the semiconductor die.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: July 5, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Erwin Victor R. Cruz, Maria Cristina B. Estacio
  • Patent number: 7968996
    Abstract: An integrated circuit package system provides a leadframe having a short lead finger, a long lead finger, and a support bar. A first die is placed in the leadframe. An adhesive is attached to the first die, the long lead finger, and the support bar. A second die is offset from the first die. The offset second die is attached to the adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: June 28, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan
  • Patent number: 7947534
    Abstract: An integrated circuit package system is provided including: forming a plurality of leads with a predetermined thickness and a predetermined interval gap between each of the plurality of leads; configuring each one of the plurality of leads to include first terminal ends disposed adjacent an integrated circuit and second terminal ends disposed along a periphery of a package; and forming the second terminal ends of alternating leads disposed along the periphery of the package to form an etched lead-to-lead gap in excess of the predetermined interval gap.
    Type: Grant
    Filed: February 4, 2006
    Date of Patent: May 24, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Henry D. Bathan, Il Kwon Shim, Keng Kiat Lau
  • Patent number: 7944031
    Abstract: Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages comprise a leadframe supporting a die that contains a discrete device. The chip scale semiconductor device also contains and an interconnect structure that also serves as a land for the package. The leadframe contains a topset feature adjacent a die attach pad supporting the die, a configuration which provides a connection to the interconnect structure as well as the backside of the die. This leadframe configuration provides a maximum die size to be used in the chip scale semiconductor packages while allowing them to be used in low power and ultra-portable electronic devices. Other embodiments are described.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: May 17, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Manolito Galera, Leocadio Morona Alabin
  • Patent number: 7928540
    Abstract: An integrated circuit package system is provided including forming an external interconnect having a lead body and a lead tip, forming a lead protrusion in the lead tip, connecting a device and the external interconnect, and encapsulating the device and the external interconnect.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: April 19, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Il Kwon Shim, Antonio B. Dimaano, Jr., Henry D. Bathan, Jeffrey D. Punzalan
  • Patent number: 7893523
    Abstract: A microarray package includes a leadframe having an array of contact posts, a die carried by the lead frame, and a plurality of bonding wires that electrically connect the die to the lead frame. An encapsulant is included that encapsulates the die, the bonding wire and the leadframe while leaving the distal ends of the contact posts exposed and substantially co-planar with a bottom surface of the microarray package. A plurality of pedestal members is plated to the distal end of a respective contact pad. A distal surface of each pedestal member protrudes outwardly beyond the bottom surface of the microarray package in the range of about 15 ?m to about 35 ?m.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: February 22, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Jaime A. Bayan, Nghia Thuc Tu
  • Patent number: 7880313
    Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: February 1, 2011
    Assignee: Chippac, Inc.
    Inventors: Jae Soo Lee, Geun Sik Kim, Sheila Alvarez, Robinson Quiazon, Hin Hwa Goh, Frederick Dahilig
  • Patent number: 7875965
    Abstract: A semiconductor chip package is disclosed. The semiconductor chip package comprises a lead frame having a chip carrier, wherein the chip carrier has a first surface and an opposite second surface. A semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the semiconductor chip has an area larger than that of the chip carrier. A package substrate comprises a central region attached to the second surface, having an area larger than that of the semiconductor chip, wherein some of the bonding pads of the semiconductor chip are electrically connected to a marginal region of the package substrate.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: January 25, 2011
    Assignee: Mediatek Inc.
    Inventors: Nan-Jang Chen, Hong-Chin Lin