Bent Parts Being Outer Leads (epo) Patents (Class 257/E23.048)
  • Patent number: 9012264
    Abstract: An integrated circuit package is provided with a thin-film battery electrically connected to and encapsulated with an integrated circuit die. The battery can be fabricated on a dedicated substrate, on the die pad, or on the integrated circuit die itself.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Michael J. Hundt, Haibin Du, Krishnan Kelappan, Frank Sigmund
  • Patent number: 9006869
    Abstract: A light emitting device package is provided comprising a light emitting device including at least one light emitting diode and a body including a first lead frame on which the light emitting device is mounted and a second lead frame spaced apart from the first lead frame, wherein at least one of the first and second lead frames is extending to a bending region in a first direction by a predetermined length on the basis of an outer surface of the body and is bent in a second direction intersecting the first direction.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 14, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: JaeJoon Yoon
  • Patent number: 8987054
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Darrell Truhitte
  • Patent number: 8969138
    Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: March 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshihiko Shimanuki
  • Patent number: 8866296
    Abstract: A semiconductor device includes: a semiconductor chip with a plurality of electrode pads disposed at a top surface thereof; a plurality of thin film terminals set apart from one another via respective separator portions, which are located below a bottom surface of the semiconductor chip; an insulating layer disposed between the semiconductor chip and the thin-film terminals; connecting members that connect the electrode pads at the semiconductor chip with the thin-film terminals respectively and a resin layer disposed so as to cover the semiconductor chip, the plurality of thin-film terminals exposed at the semiconductor chip, the separator portions and the connecting members.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: October 21, 2014
    Assignee: AOI Electronics Co., Ltd.
    Inventors: Takashi Yamaji, Takaaki Kato
  • Patent number: 8629540
    Abstract: Apparatus and methods are provided for integrally packaging semiconductor IC (integrated circuit) chips with antennas having one or more radiating elements and tuning elements that are formed from package lead wires that are appropriated shaped and arranged to form antenna structures for millimeter wave applications.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian P. Gaucher, Duixian Liu, Ullrich R. Pfeiffer, Thomas M. Zwick
  • Patent number: 8610254
    Abstract: Apparatuses are disclosed, such as those involving integrated circuit packaging. In one embodiment, a chip package includes: an encapsulation having a top surface and a bottom surface facing away from the top surface. The package further includes a leadframe including a plurality of leads. Each of the leads includes an exposed portion exposed through one of edges of the bottom surface of the encapsulation. The exposed portion has a length. At least one of exposed portions positioned along one of the edges of the bottom surface of the encapsulation has a length different from other exposed portions along the edge. The package can also include a dummy pad exposed through a corner of the bottom surface. The configuration can enhance solder joint reliability of the package when the package is attached to a printed circuit board.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: December 17, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Ying Zhao
  • Patent number: 8508036
    Abstract: A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: August 13, 2013
    Assignee: Tessera, Inc.
    Inventors: Kenneth Allen Honer, Philip Damberg
  • Patent number: 8502371
    Abstract: An integrated circuit package system including: forming a die pad, wherein the die pad has a tiebar at a corner; forming a lead wherein the lead is connected to the tiebar; connecting an integrated circuit die to the die pad; and forming an encapsulation, having an edge, over the integrated circuit die with the lead extending from and beyond the edge.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: August 6, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Jairus Legaspi Pisigan, Henry Descalzo Bathan
  • Patent number: 8455988
    Abstract: An integrated circuit package system includes: forming an external interconnect; forming a terminal having a cavity adjacent to and downset from a portion the external interconnect; connecting a first integrated circuit with the external interconnect; and forming an encapsulation over the first integrated circuit with cavity filled with the encapsulation, the terminal extending from the encapsulation, and the external interconnect partially exposed from the encapsulation.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: June 4, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jose Alvin Caparas, Zigmund Ramirez Camacho
  • Patent number: 8431438
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: April 30, 2013
    Assignee: Intel Corporation
    Inventors: Ravi K Nalla, Mathew J Manusharow
  • Patent number: 8395251
    Abstract: An integrated circuit package to package stacking system is provided including providing a first integrated circuit package, having a configured leadframe, providing a second integrated circuit package, having the configured leadframe, and forming an integrated circuit package pair by electrically connecting the configured leadframe of the first integrated circuit package to the configured leadframe of the second integrated circuit package.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: March 12, 2013
    Assignee: STATS ChipPac Ltd.
    Inventors: Il Kwon Shim, Seng Guan Chow, Jeffrey D. Punzalan, Byung Joon Han, Kambhampati Ramakrishna
  • Patent number: 8390103
    Abstract: Apparatuses are disclosed, such as those involving integrated circuit packaging. In one embodiment, a chip package includes: an encapsulation having a top surface and a bottom surface facing away from the top surface. The package further includes a leadframe including a plurality of leads. Each of the leads includes an exposed portion exposed through one of edges of the bottom surface of the encapsulation. The exposed portion has a length. At least one of exposed portions positioned along one of the edges of the bottom surface of the encapsulation has a length different from other exposed portions along the edge. The package can also include a dummy pad exposed through a corner of the bottom surface. The configuration can enhance solder joint reliability of the package when the package is attached to a printed circuit board.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: March 5, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Ying Zhao
  • Patent number: 8384206
    Abstract: In one embodiment, a semiconductor package is formed to include a leadframe that includes a plurality of die attach areas for attaching a semiconductor die to the leadframe. The leadframe is positioned to overlie another leadframe that forms some of the external terminals or leads of the package.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: February 26, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Stephen St. Germain, Roger M. Arbuthnot, Frank Tim Jones
  • Patent number: 8344499
    Abstract: A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: January 1, 2013
    Assignee: Alpha & Omega Semiconductor, Inc
    Inventors: Yuping Gong, Yan Xun Xue
  • Patent number: 8310041
    Abstract: A stacked semiconductor package technique applicable to semiconductor chips having pins short enough that the semiconductor chips cannot be directly bonded together is provided. A printed circuit board (PCB) is inserted into a space between pins of an upper semiconductor chip and the exterior of bodies of stacked semiconductor chips. The PCB includes a plurality of conductive patterns at locations corresponding to the respective pins. The respective conductive patterns and the corresponding respective pins of the upper and lower semiconductor chips are bonded together. The PCB includes a plurality of recess patterns on one side, the recess patterns having the same pitch as the pins of the semiconductor chips. The PCB is disposed across the pins of the lower semiconductor chip, and thereby easily arranged with the stacked semiconductor chips.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: November 13, 2012
    Assignee: Polystak, Inc.
    Inventor: Tae Seung Chung
  • Patent number: 8269343
    Abstract: A semiconductor device in accordance with one embodiment of the invention can include a substrate onto which a wiring pattern is formed. In addition, the semiconductor device can include a plurality of semiconductor packages. Each semiconductor package can include a lead frame that is coupled to an electrode of a semiconductor chip. Each lead frame can be located on a side surface and a bottom surface of the semiconductor package. In addition, the semiconductor device can include a pressure-contact section for receiving the plurality of semiconductor packages and for causing the plurality of semiconductor packages to come into contact with the wiring pattern.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: September 18, 2012
    Assignee: Spansion LLC
    Inventor: Kouichi Meguro
  • Patent number: 8235551
    Abstract: A light-emitting diode (LED) module and an LED packaging method. As the LED module is packaged under the consideration of candela distribution, each of the lead frames of the LED chips packaged in the LED module is bended for tilting the LED chips by different angles to exhibit various lighting effects. Meanwhile, in the LED packaging method, a plurality of LED chips can be loaded on board rapidly and aligned by one operation to result in less deviation in the candela distribution curve.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: August 7, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Jian-Shian Lin, Chieh-Lung Lai, Hsiu-Jen Lin, Weng-Jung Lu, Yi-Ping Huang, Ya-Chun Tu
  • Patent number: 8236613
    Abstract: A method for wafer level chip scale package comprises providing a wafer with semiconductor chips formed thereon, forming a groove alongside each chip, providing a wafer size clip array with a plurality of clip contact areas each extending to a down set connecting bar, connecting the plurality of clip contact areas to a plurality of the electrodes disposed on a top surface of the chips with down set connecting bars disposed inside the grooves, encapsulating top of wafer in molding compound, thinning the bottom portion of the wafer and dicing the thin wafer into single chip packages. The chip has source and gate electrodes on a top surface connected to a first and second clip contact areas extending to a first a second down set connecting bars respectively, with the bottom surfaces of the down set connecting bars substantially coplanar to a drain electrode located at the chip bottom surface.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: August 7, 2012
    Assignee: Alpha & Omega Semiconductor Inc.
    Inventor: Yuping Gong
  • Patent number: 8232658
    Abstract: A stackable integrated circuit package system includes: forming a first integrated circuit die having a small interconnect and a large interconnect provided thereon; forming an external interconnect, having an upper tip and a lower tip, from a lead frame; mounting the first integrated circuit die on the external interconnect with the small interconnect on the lower tip and below the upper tip; and encapsulating around the small interconnect and around the large interconnect with an exposed surface.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: July 31, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Heap Hoe Kuan, Dioscoro A. Merilo, Antonio B. Dimaano, Jr.
  • Patent number: 8212366
    Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: July 3, 2012
    Assignee: Panasonic Corporation
    Inventors: Manabu Ohnishi, Koji Takemura, Noriyuki Nagai, Hoyeun Huh, Tomoyuki Nakayama, Atsushi Doi
  • Patent number: 8212341
    Abstract: Apparatus and methods are provided for integrally packaging semiconductor IC (integrated circuit) chips with antennas having one or more radiating elements and tuning elements that are formed from package lead wires that are appropriated shaped and arranged to form antenna structures for millimeter wave applications.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: July 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brian P. Gaucher, Duixian Liu, Ullrich R. Pfeiffer, Thomas M. Zwick
  • Patent number: 8106418
    Abstract: A light emitting device includes a first lead and a second lead. The first lead has a top surface which a light emitting element is mounted thereon and a bottom surface opposed to the top surface. The second lead has a lead peripheral region where a wire connected to an electrode of the light emitting element is bonded therewith. The first lead includes a lead middle region where the semiconductor light emitting element is mounted thereon to thermally conduct therewith. A bottom surface of the lead middle region is exposed from a package. The second lead has an outer lead region that is projected outwardly from the both side surfaces of the package. The bottom surface of the first lead middle region is substantially coplanar with a bottom surface of the outer lead region.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: January 31, 2012
    Assignee: Nichia Corporation
    Inventor: Yoshitaka Bando
  • Patent number: 8097933
    Abstract: A flexible semiconductor package includes a flexible substrate. A data chip is disposed over the flexible substrate. The data chip includes a data storage unit for storing data and first bonding pads that are electrically connected to the data storage unit. A control chip is disposed over the flexible substrate. The control chip includes a data processing unit for processing the data in the data chip and second bonding pads that are electrically connected to the data processing unit. Wirings are formed in order to electrically connect the first bonding pads to the second bonding pads.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: January 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Min Suk Suh
  • Patent number: 8097934
    Abstract: A lead frame and package construction configured to attain a thin profile and low moisture sensitivity. Lead frames of this invention may include a die attach pad having a die attachment site and an elongate ground lead that extends from the die attach pad. The lead frame includes a plurality of elongate I/O leads arranged about the die attach pad and extending away from the die attach pad in at least two directions. An inventive lead frame features “up-set” bonding pads electrically connected with the die attach pad and arranged with a bonding surface for supporting a plurality of wire bonds. The bonding surfaces also constructed to define at least one mold flow aperture for each up-set bonding pad. A package incorporating the lead frame is further disclosed such that the package includes an encapsulant that surrounds the bonding support and flows through the mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: January 17, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Felix C. Li, Yee Kim Lee, Peng Soon Lim, Terh Kuen Yii, Lee Han Meng@Eugene Lee
  • Patent number: 7989932
    Abstract: A semiconductor device includes a lead frame including inner lead portion having inner leads connected to outer leads and relay inner leads not connected to the outer leads. A semiconductor element is mounted on a lower surface of the lead frame. Electrode pads of the semiconductor element are connected to the inner lead portion via metal wire. One end of the relay inner lead is connected to the electrode pad via the metal wire, and the other end is connected to the outer lead via a relay metal wire disposed to step over the inner lead.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: August 2, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Goto
  • Patent number: 7982235
    Abstract: The semiconductor device includes a semiconductor element, a lead frame electrically connected to the semiconductor element, and a package having an opening in a front surface with a part of the lead frame protruding from a bottom surface. The protruding lead frame branches into a plurality of end portions, and the end portions are bent to be positioned respectively on a side surface and one of a back surface and a bottom surface of the package.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: July 19, 2011
    Assignee: Nichia Corporation
    Inventors: Hideo Asakawa, Takeo Kurimoto
  • Patent number: 7888185
    Abstract: Semiconductor device assemblies and systems that include at least one semiconductor device assembly include two or more semiconductor devices stacked one over another. Conductive pathways that extend around at least one side of at least one of the semiconductor devices provide electrical communication between conductive elements of the semiconductor devices, and optionally, a substrate. The conductive pathways may include self-supporting conductive leads or conductive traces carried by a substrate. Methods for forming semiconductor device assemblies having more than one semiconductor device include bending or wrapping at least one conductive pathway around a side of at least one semiconductor device and providing electrical communication between semiconductor devices of the assembly through the conductive pathways.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: February 15, 2011
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Chin Hui Chong, Choon Kuan Lee
  • Patent number: 7880313
    Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: February 1, 2011
    Assignee: Chippac, Inc.
    Inventors: Jae Soo Lee, Geun Sik Kim, Sheila Alvarez, Robinson Quiazon, Hin Hwa Goh, Frederick Dahilig
  • Patent number: 7868447
    Abstract: Warpage and twist of a solid-state image sensing apparatus is controlled, thereby preventing displacement occurring to the solid-state image sensing apparatus when it is mounted on a printed circuit board. The solid-state image sensing apparatus comprises a plurality of outer leads, and the outer leads each comprises a horizontal portion protruding in the horizontal direction from a side face of a package body for encasing a solid-state image sensing chip therein, an end portion extending in a direction orthogonal to the horizontal portion, and disposed directly below the horizontal portion, a mid portion positioned between the horizontal portion, and the end portion, a first bend formed between the horizontal portion, and the mid portion, and a second bend formed between the mid portion, and the end portion.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: January 11, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hirochika Narita
  • Patent number: 7868434
    Abstract: An integrated circuit package-on-package stacking system includes a leadframe interposer including: a leadframe having a lead; a molded base on a portion of the lead for only supporting the lead; and the leadframe interposer singulated from the leadframe, wherein the lead is bent to support a stack-up height.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: January 11, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Dioscoro A. Merilo, Heap Hoe Kuan, You Yang Ong, Seng Guan Chow, Ma. Shirley Asoy
  • Patent number: 7863737
    Abstract: An integrated circuit package system including providing a plurality of substantially identical package leads formed in a single row, and attaching bond wires having an offset on adjacent locations of the package leads.
    Type: Grant
    Filed: April 1, 2006
    Date of Patent: January 4, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Byoung Wook Jang, Hun Teak Lee, Kwang Soon Hwang
  • Patent number: 7859090
    Abstract: In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure).
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: December 28, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Jaime A. Bayan, Nghia Thuc Tu, Lim Fong, Chan Peng Yeen
  • Patent number: 7847418
    Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: December 7, 2010
    Assignee: Panasonic Corporation
    Inventors: Manabu Ohnishi, Koji Takemura, Noriyuki Nagai, Hoyeun Huh, Tomoyuki Nakayama, Atsushi Doi
  • Patent number: 7737546
    Abstract: A packaged circuit element such as an LED and a method for making the same are disclosed. The packaged circuit element includes a lead frame, a molded body, and a die containing the circuit element. The lead frame has first and second leads, each lead having first and second portions. The molded body surrounds the first portion of each lead, and the die is connected electrically to the first and second leads on the first portions of the first and second leads. The second portion of each of the first and second leads is substantially parallel to opposing side surfaces of the body and include a feature that inhibits molten solder from wetting a portion of the second section of each lead between the feature and the first portion of that lead while allowing the molten solder to wet the remaining surfaces of the second portions.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: June 15, 2010
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Wai Hoong Moy, Chu Kun Tan, Keh Chin Seah, Paul Beng Hui Oh
  • Patent number: 7723828
    Abstract: A LOC leadframe-based semiconductor package includes a chip with multiple rows of bonding pads. At least a bus bar is attached to the chip and is disposed between a first row of bonding pads and the fingers of the leads. A plurality of bonding wires electrically connect the first row of bonding pads to the fingers of the leads. The portion of the bus bar attached to the active surface of the chip includes a bent section bent away from the fingers. A long bonding wire electrically connects one of a second row of bonding pads to one of the fingers of the leads by overpassing the bent section. Therefore, the distance between the long bonding wire and the bus bar is increased to avoid electrical short between the long bonding wire and the bus bar and to enhance the quality of electrical connections of the LOC semiconductor package.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: May 25, 2010
    Assignee: Powertech Technology Inc.
    Inventors: Wen-Jeng Fan, Yu-Mei Hsu
  • Patent number: 7709935
    Abstract: A semiconductor device package includes an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface disposed at the first package face and a second contact surface disposed at the second package face. The lead frame also includes a plurality of post extensions disposed at the second package face. Each of the post extensions includes a bond site formed on a surface of the post extension opposite the second package face. At least one I/O pad on the semiconductor device is electrically connected to the post extension at the bond site using wirebonding, tape automated bonding, or flip-chip methods. The package can be assembled using a lead frame having pre-formed leads, with or without taping, or using partially etched lead frames. A stack of the semiconductor device packages may be formed.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: May 4, 2010
    Assignee: Unisem (Mauritius) Holdings Limited
    Inventors: Shafidul Islam, Romarico S. San Antonio
  • Patent number: 7692208
    Abstract: The disclosed subject matter includes a semiconductor optical device with a stable optical characteristic, an excellent radiant efficiency, and a high mounting reliability. A casing can be configured with a concaved-shaped cavity that includes an opening and a bottom portion. Each of one end portions of first/second lead frame electrodes 3a, 3b can be exposed on the bottom portion. The first one end portion can include an optical chip mounted thereon, and the second one end portion can be connected to another electrode of the optical chip via a bonding wire. The first lead frame electrode extends from an outside surface substantially perpendicular to the bottom portion and is bent in a direction towards the opening. The second lead frame electrode extends from an outside surface of the casing that is opposite to the outside surface from which the first electrode extends. Various physical configurations of the electrodes are disclosed.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: April 6, 2010
    Assignee: Stanley Electric Co., Ltd.
    Inventor: Akihiko Hanya
  • Patent number: 7663223
    Abstract: A coupling substrate for semiconductor components includes a patterned metal layer on a topside of an insulating carrier. Metal tracks project beyond the insulating carrier, the metal tracks being angled away at the lateral edges of the carrier in the direction of the underside of the carrier and projecting beyond the underside of the carrier. The metal tracks have a metal coating, thereby enlarging each cross section such that the metal tracks form dimensionally stable, flat, conductor external contacts of the coupling substrate.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: February 16, 2010
    Assignee: Infineon Technologies AG
    Inventor: Jens Pohl
  • Patent number: 7619307
    Abstract: A leadframe-based semiconductor package and a leadframe for the package are revealed. The semiconductor package primarily includes parts of the leadframe including one or more first leads, one or more second leads, and a supporting bar disposed between the first leads and the second leads and further includes a chip attached to the first leads, the second leads and the supporting bar, a plurality of bonding wires and an encapsulant. The supporting bar has an extended portion projecting from the first bonding finger and the second bonding finger and connected to a non-lead side of the encapsulant wherein the extended portion has an arched bend to absorb the pulling stresses and to block stress transmission. Cracks caused by delamination of the supporting bar will not be created during trimming the supporting bar along the non-lead side of the encapsulant. Moisture penetration along the cracks of the supporting bar to the die-bonding plane under the chip is desirably prevented.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: November 17, 2009
    Assignee: Powertech Technology Inc.
    Inventors: Chin-Fa Wang, Wan-Jung Hsieh, Yu-Mei Hsu
  • Patent number: 7615851
    Abstract: An integrated circuit package system comprised by providing a leadframe including leads configured to provide electrical contact between an integrated circuit chip and an external electrical source. Configuring the leads to include outer leads, down set transitional leads, and down set inner leads. Connecting the integrated circuit chip electrically to the down set inner leads. Depositing an encapsulating material to prevent exposure of the down set inner leads.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: November 10, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Taesung Lee, Jae Soo Lee, Geun Sik Kim
  • Patent number: 7598600
    Abstract: The present invention provides a method of making a stackable power semiconductor package system comprising forming a lower lead frame, having an upward bent source lead and an upward bent gate lead, mounting a power semiconductor device on the lower lead frame utilizing interconnect structures and forming an upper lead frame wherein the upper lead frame is on the power semiconductor device.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: October 6, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Wai Kwong Tang, You Yang Ong, Kuan Ming Kan, Larry Lewellen
  • Publication number: 20090224377
    Abstract: A semiconductor device having linear zigzag(s) for wire bonding is revealed, primarily comprising a chip, a plurality of leads made of a lead frame and a plurality of bonding wires electrically connecting the chip and the leads. At least one of the leads has a linear zigzag including a first finger and a second finger connected each other in a zigzag form. One end of one of the bonding wire is bonded to a bonding pad on the chip and the other end is selectively bonded to either the first finger or the second finger but not both in a manner that the wire-bonding direction of the bonding wire is parallel to or in a sharp angle with the direction of the connected fingers for easy wire bonding processes. Therefore, the semiconductor device can assemble chips with diverse dimensions or with diverse bonding pads layouts by flexible wire-bonding angles at linear zigzag to avoid electrical short between the adjacent leads.
    Type: Application
    Filed: March 9, 2008
    Publication date: September 10, 2009
    Inventors: Wen-Jeng Fan, Yu-Mei Hsu
  • Publication number: 20090160038
    Abstract: A LOC leadframe-based semiconductor package includes a chip with multiple rows of bonding pads. At least a bus bar is attached to the chip and is disposed between a first row of bonding pads and the fingers of the leads. A plurality of bonding wires electrically connect the first row of bonding pads to the fingers of the leads. The portion of the bus bar attached to the active surface of the chip includes a bent section bent away from the fingers. A long bonding wire electrically connects one of a second row of bonding pads to one of the fingers of the leads by overpassing the bent section. Therefore, the distance between the long bonding wire and the bus bar is increased to avoid electrical short between the long bonding wire and the bus bar and to enhance the quality of electrical connections of the LOC semiconductor package.
    Type: Application
    Filed: February 8, 2008
    Publication date: June 25, 2009
    Applicant: POWERTECH TECHNOLOGY INC.
    Inventors: Wen-Jeng Fan, Yu-Mei Hsu
  • Patent number: 7541672
    Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: June 2, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yukihiro Satou, Toshiyuki Hata
  • Patent number: 7541665
    Abstract: A magnetic sensor is constituted using magnetic sensor chips mounted on stages supported by interconnecting members and a frame having leads in a lead frame. Herein, the stages are inclined upon plastic deformation of the interconnecting members. When the frame is held in a metal mold and the stages are pressed, the interconnecting members are elastically deformed, so that the magnetic sensor chips are bonded onto the stages placed substantially in the same plane and are then wired with the leads. Thereafter, the stages are released from pressure, so that the interconnecting members are restored from the elastically deformed states thereof. When the magnetic sensor chips are combined together to realize three sensing directions, it is possible to accurately measure three-dimensional bearings of magnetism, and the magnetic sensor can be reduced in dimensions and manufactured with a reduced cost therefore.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: June 2, 2009
    Assignee: Yamaha Corporation
    Inventors: Hiroshi Adachi, Hiroshi Saitoh, Kenichi Shirasaka, Hideki Sato, Masayoshi Omura
  • Patent number: 7531895
    Abstract: An integrated circuit (IC) package that comprises a lead frame. The lead frame has a downset portion and leads. The downset portion has an exterior surface that is configured to face away from a mounting board, and an interior surface that is configured to face towards the mounting board. The leads are bent away from the exterior surface, and each of the leads have a first end coupled to an IC and a second end configured to pass through one of a plurality of mounting holes extending through the mounting board. The IC is coupled to the interior surface.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: May 12, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Bernhard Lange, William David Boyd
  • Publication number: 20090115035
    Abstract: Integrated circuit (IC) packages are described. Each IC package includes a die having an exposed metallic layer deposited on its back surface. Solder joints are arranged to physically and electrically connect I/O pads on the active surface of the die with associated leads. A molding material encapsulates portions of the die, leadframe and solder joint connections while leaving the metallic layer exposed and uncovered by molding material.
    Type: Application
    Filed: November 6, 2007
    Publication date: May 7, 2009
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jaime A. BAYAN, Anindya Poddar
  • Patent number: 7528476
    Abstract: A semiconductor device includes: a semiconductor substrate having an active surface and a back surface; an integrated circuit formed on the active surface; a feedthrough electrode penetrating the semiconductor substrate, and projecting from the active surface and the back surface; a first resin layer formed on the active surface, having a thickness greater than a height of a portion of the feedthrough electrode that projects from the active surface, and having an opening portion for exposing at least a portion of the feedthrough electrode; a wiring layer which is formed on the first resin layer, and which is connected to the feedthrough electrode through the opening portion; and an external connecting terminal connected to the wiring layer.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: May 5, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Haruki Ito
  • Patent number: 7524699
    Abstract: One embodiment of the invention relates to an electronic component having stacked semiconductor chips, and to a panel for production of the component. In one case, the stack has a flat conductor structure with a chip island on which a stacked semiconductor chip is arranged, while a first semiconductor chip is located underneath it. The chip island is surrounded by flat conductors which have contact pillars. These contact pillars have pillar contact pads which, together with the active upper face of the first semiconductor chip and the upper face areas of a plastic encapsulation compound form a coplanar overall upper face.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: April 28, 2009
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Bernd Goller, Robert-Christian Hagen, Simon Jerebic, Jens Pohl, Peter Strobel, Holger Woerner