Characterized By Bent Parts (epo) Patents (Class 257/E23.047)
  • Patent number: 12131980
    Abstract: A semiconductor module includes a semiconductor device having a gate runner extending in a first direction at an upper surface of the semiconductor device, and a metal wiring plate having a first bonding portion with a bonding surface to which the upper surface of the semiconductor device is bonded via a first bonding material. The first bonding portion has a plurality of first protrusions at the bonding surface. Each first protrusion protrudes toward the semiconductor device, and is provided in a position away from the gate runner by a first distance in a plan view of the semiconductor module.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: October 29, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Toru Yamada, Takafumi Yamada
  • Patent number: 11973012
    Abstract: A power module includes a metal frame having a first and second device attach pads, first and second semiconductor packages each having an encapsulant body, a die pad exposed at a lower surface of the encapsulant body, a plurality of leads protruding out from the encapsulant body, and a potting compound that encapsulates both of the first and second semiconductor packages and partially covers the metal frame. The first semiconductor package is mounted on the metal frame such that the die pad of the first semiconductor package faces and electrically contacts the first device attach pad. The second semiconductor package is mounted on the metal frame such that the die pad of the second semiconductor package faces and electrically contacts the second device attach pad. The plurality of leads from each of the first and second semiconductor packages are electrically accessible from outside of the potting compound.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: April 30, 2024
    Assignee: Infineon Technologies Austria AG
    Inventor: Andreas Grassmann
  • Patent number: 11948855
    Abstract: An integrated circuit (IC) package comprises a substrate having an outer portion close to the perimeter of the substrate, an inner portion surrounded by the outer portion, and an upper surface incorporating a wiring layer for the bonding of a semiconducting die (e.g., via its bottom face). The IC package includes a metallic or otherwise thermally conductive heat spreader thermally bonded on an inner surface of a boss on its bottom side to the top surface of the semiconducting die, and extending on its top surface to the edges of the substrate to maximize heat dissipation from the die. The boss extends toward the semiconducting die and is thermally coupled to the top face of the semiconducting die.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: April 2, 2024
    Assignee: Rockwell Collins, Inc.
    Inventors: Bret W. Simon, Jacob R. Mauermann, Mark T. Dimke, Kaitlyn M. Fisher
  • Patent number: 11908780
    Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: February 20, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jonathan Almeria Noquil, Satyendra Singh Chauhan, Lance Cole Wright, Osvaldo Jorge Lopez
  • Patent number: 11901271
    Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: February 13, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yiqi Tang, Liang Wan, William Todd Harrison, Manu Joseph Prakuzhy, Rajen Manicon Murugan
  • Patent number: 11881413
    Abstract: A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: January 23, 2024
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventors: Michael De Cruz, Olivier Ory
  • Patent number: 11869837
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes attaching a first end of a first bond wire to a first conductive lead and a second end of the first bond wire to a first bond pad of a first semiconductor die. A conductive lead extender is affixed to the first conductive lead by way of a conductive adhesive, the lead extender overlapping the first end of the first bond wire. A first end of a second bond wire is attached to the lead extender, the first end of the second bond wire conductively connected to the first end of the first bond wire.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: January 9, 2024
    Assignee: NXP B.V.
    Inventor: Mei Yeut Lim
  • Patent number: 11862541
    Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. Each lead of the plurality of leads has a negative standoff relative to the bottom main surface of the mold compound.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: January 2, 2024
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Dirk Ahlers, Stefan Macheiner
  • Patent number: 11862540
    Abstract: A frame includes leadframe units arranged in a matrix. Each leadframe unit has a die pad and tie bars connected to and extending from the die pad. Each tie bar includes an internal tie bar portion and an external tie bar portion. The internal tie bar portion of at least one tie bar includes a cut separating a part of the internal tie bar portion from the external tie bar portion. An out-of-plane bend in that part forms a mold flow control structure.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: January 2, 2024
    Assignee: STMicroelectronics SDN BHD
    Inventor: Yh Heng
  • Patent number: 11830786
    Abstract: A flip-chip semiconductor package with improved heat dissipation capability and low package profile is provided. The package comprises a heat sink having a plurality of heat dissipation fins and a plurality of heat dissipation leads. The heat dissipation leads are connected to a plurality of thermally conductive vias of a substrate so as to provide thermal conductivity path from the heatsink to the substrate as well as support the heatsink to relieve compressive stress applied to a semiconductor die by the heatsink. The package further comprises an encapsulation layer configured to cover the heat dissipation leads of the heat sink and expose the heat dissipation fins of the heat sink.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 28, 2023
    Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
    Inventors: Jingyu Shen, Qiyue Zhao, Chunhua Zhou, Chao Yang, Weigang Yao, Baoli Wei
  • Patent number: 11830832
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure over the dielectric surface. A first protecting structure over the passivation layer. A conductive pad over the dielectric surface. A polymer layer over the first protecting structure and the conductive pad. A conductive bump electrically coupled to the conductive pad through an opening of the polymer layer. A first portion of the first protecting structure is leveled with the conductive pad and a second portion of the first protecting structure is higher than the conductive pad.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Jiun Wu, Mingni Chang, Ming-Yih Wang, Yinlung Lu
  • Patent number: 11798869
    Abstract: A semiconductor package includes: a plurality of die pads; a plurality of semiconductor chips provided on the plurality of die pads respectively; a plurality of lead terminals connected to the plurality of semiconductor chips respectively; and a package sealing the plurality of die pads, the plurality of semiconductor chips, and the plurality of lead terminals, the plurality of die pads and the plurality of lead terminals are exposed from a lower surface of the package, and on the lower surface of the package, grooves are provided among the die pads adjacent to one another and among the lead terminals adjacent to one another.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: October 24, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuki Terado, Shiori Uota, Shinji Sakai
  • Patent number: 11735546
    Abstract: A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: August 22, 2023
    Assignee: VueReal Inc.
    Inventors: Gholamreza Chaji, Ehsanollah Fathi
  • Patent number: 11699667
    Abstract: A leadframe having extensions around an outer edge of a die pad are disclosed. More specifically, leadframes are created with a flange formed at the outer edge of the die pad and extending away from the die pad. The flange is bent, such that it is positioned at an angle with respect to the die pad. Leadframes are also created with anchoring posts formed adjacent the outer edge of the die pad and extending away from the die pad. The anchoring posts have a central thickness that is less than a thickness of first and second portions opposite the central portion. When the leadframe is incorporated into a package, molding compound completely surrounds each flange or anchoring post, which increases the bond strength between the leadframe and the molding compound due to increased contact area. The net result is a reduced possibility of delamination at edges of the die pad.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: July 11, 2023
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 11688670
    Abstract: A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: June 27, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
  • Patent number: 11652084
    Abstract: A method of forming a semiconductor package includes providing a panel, providing one or more metal layers on an upper surface of the panel, forming a die pad and bond pads from the one or more metal layers, the die pad being adjacent to and spaced apart from the bond pads, attaching a die to the die pad, forming electrical connections between the die and the bond pads, encapsulating the die and the electrical connections with an electrically insulating mold compound, removing portions of the panel, and exposing the die pad and the bond pads after encapsulating the die.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 16, 2023
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Gerald Ofner, Stephan Bradl, Stefan Miethaner, Alexander Heinrich, Horst Theuss, Peter Scherl
  • Patent number: 11652032
    Abstract: Inner leads having die pads having upper surfaces to which semiconductor elements are mounted each have a stepped profile, and surfaces of portions of the inner leads are exposed from a sealing resin in plan view. Outer leads connected to the inner leads have first bends at side surfaces of the sealing resin to extend in a direction on a side of the upper surfaces of the die pads, so that a miniaturized semiconductor device can be obtained.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: May 16, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventor: Keitaro Ichikawa
  • Patent number: 11631623
    Abstract: A lead member includes a plurality of lead terminals, and the lead terminals extend from the inside to the outside of a mold resin. Each of the lead terminals has a base portion and a tip end portion on the outside of the mold resin. The base portion is disposed on a region side having a semiconductor element and extends in a direction protruding from the mold resin. The tip end portion extends in a direction different from the base portion and is disposed on the opposite side to a region having the semiconductor element as viewed from the base portion. The length by which the base portion extends differs between a pair of lead terminals adjacent to each other, among the lead terminals. At least a surface of the base portion of each of the lead terminals is covered with a coating resin.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: April 18, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takamasa Iwai, Junji Fujino, Hiroshi Kawashima
  • Patent number: 11626351
    Abstract: A semiconductor package includes a semiconductor die, an encapsulant body of electrically insulating material that encapsulates the semiconductor die, a thermal conduction plate comprising an outer surface that is exposed from the encapsulant body, a region of thermal interface material interposed between the thermal conduction plate and the semiconductor die, the region of thermal interface material being a liquid or semi-liquid, and a barrier that is configured to prevent the thermal interface material of the region from flowing laterally across the barrier.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: April 11, 2023
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Timo Bohnenberger, Andreas Grassmann, Martin Mayer, Alexander Roth, Franz Zollner
  • Patent number: 11621231
    Abstract: Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: April 4, 2023
    Assignee: NXP USA, Inc.
    Inventors: Yun Wei, Fernando A. Santos, Lakshminarayan Viswanathan, Scott Duncan Marshall
  • Patent number: 11600556
    Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, a first chip pad on a bottom surface of the semiconductor chip and adjacent to a first lateral surface in a first direction of the semiconductor chip, the first lateral surface separated from the first chip pad from a plan view in a first direction, and a first lead frame coupled to the first chip pad. The first lead frame includes a first segment on a bottom surface of the first chip pad and extending from the first chip pad in a second direction opposite to the first direction and away from the first lateral surface of the semiconductor chip, and a second segment which connects to a first end of the first segment and then extends along the first direction to extend beyond the first lateral surface of the semiconductor chip after passing one side of the first chip pad, when viewed in the plan view.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: March 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minki Kim, Duckgyu Kim, Jae-Min Jung, Jeong-Kyu Ha, Sang-Uk Han
  • Patent number: 11581195
    Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles, a first plurality of leads, and a second plurality of leads. A respective end surface of each lead of the first plurality of leads and the second plurality of leads is plated with a metal. A first respective window on a first side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A second respective window on a second side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A method for fabricating a semiconductor package comprises the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, and applying a cutting process or a punching process.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: February 14, 2023
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Long-Ching Wang, Lei Fukuda, Adrian Chee Heong Koh, Peter Wilson, Feng Ye
  • Patent number: 11519939
    Abstract: A current sensor integrated circuit (IC) includes a unitary lead frame having at least one first lead having a terminal end, at least one second lead having a terminal end, and a paddle having a first surface and a second opposing surface. A semiconductor die is supported by the first surface of the paddle, wherein the at least one first lead is electrically coupled to the semiconductor die and the at least one second lead is electrically isolated from the semiconductor die. The current sensor IC further includes a first mold material configured to enclose the semiconductor die and the paddle and a second mold material configured to enclose at least a portion of the first mold material, wherein the terminal end of the at least one first lead and the terminal end of the at least one second lead are external to the second mold material.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: December 6, 2022
    Assignee: Allegro MicroSystems, LLC
    Inventors: Shixi Louis Liu, Paul A. David, Shaun D. Milano, Rishikesh Nikam, Alexander Latham, Wade Bussing, Natasha Healey, Georges El Bacha
  • Patent number: 11424176
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: August 23, 2022
    Assignee: Kioxia Corporation
    Inventor: Isao Ozawa
  • Patent number: 11342275
    Abstract: Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: May 24, 2022
    Assignee: NXP USA, Inc.
    Inventors: Yun Wei, Fernando A. Santos, Lakshminarayan Viswanathan, Scott Duncan Marshall
  • Patent number: 9006869
    Abstract: A light emitting device package is provided comprising a light emitting device including at least one light emitting diode and a body including a first lead frame on which the light emitting device is mounted and a second lead frame spaced apart from the first lead frame, wherein at least one of the first and second lead frames is extending to a bending region in a first direction by a predetermined length on the basis of an outer surface of the body and is bent in a second direction intersecting the first direction.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 14, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: JaeJoon Yoon
  • Patent number: 8963307
    Abstract: Various embodiments related to a compact device package are disclosed herein. In some arrangements, a flexible substrate can be coupled to a carrier having walls angled relative to one another. The substrate can be shaped to include two bends. First and second integrated device dies can be mounted on opposite sides of the substrate between the two bends in various arrangements.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: February 24, 2015
    Assignee: Analog Devices, Inc.
    Inventor: David Bolognia
  • Patent number: 8872314
    Abstract: A method for producing a component and device including a component is disclosed. A basic substrate having paper as substrate material is provided, at least one integrated circuit is applied to the basic substrate, the at least one integrated circuit applied on the basic substrate is enveloped with an encapsulant, and at least parts of the basic substrate are removed from the at least one enveloped integrated circuit.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Horst Theuss, Albert Auburger, Jochen Dangelmaier, Josef Hirtreiter
  • Patent number: 8866296
    Abstract: A semiconductor device includes: a semiconductor chip with a plurality of electrode pads disposed at a top surface thereof; a plurality of thin film terminals set apart from one another via respective separator portions, which are located below a bottom surface of the semiconductor chip; an insulating layer disposed between the semiconductor chip and the thin-film terminals; connecting members that connect the electrode pads at the semiconductor chip with the thin-film terminals respectively and a resin layer disposed so as to cover the semiconductor chip, the plurality of thin-film terminals exposed at the semiconductor chip, the separator portions and the connecting members.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: October 21, 2014
    Assignee: AOI Electronics Co., Ltd.
    Inventors: Takashi Yamaji, Takaaki Kato
  • Patent number: 8823152
    Abstract: In one embodiment, a semiconductor package (e.g., a QFP package) includes a leadframe sized and configured to increase the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package includes a generally planar die pad defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions that are provided in at least one row or ring, which at least partially circumvents the die pad, with other leads including portions that protrude from respective side surfaces of a package body of the semiconductor package. At least one semiconductor die is connected to the top surface of the die pad and is electrically connected to at least some of the leads.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: September 2, 2014
    Assignee: Amkor Technology, Inc.
    Inventors: Gi Jeong Kim, Wan Jong Kim
  • Patent number: 8754510
    Abstract: A conduction path includes a first conduction path forming plate (11) made of a first metal and having a through hole (13), and a second conduction path forming plate (15) made of a second metal and having a press-fit portion (17) press-fitted into the through hole. A wall surface of the through hole and a side surface of the press-fit portion forms an inclined bonding surface (18) inclined relative to a normal line of an overlap surface of the first conduction path forming plate and the second conduction path forming plate, and a bonding portion (25) formed by metal flow is formed in a region located in a periphery of the inclined bonding surface.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: June 17, 2014
    Assignee: Panasonic Corporation
    Inventors: Masanori Minamio, Zyunya Tanaka, Ryoutarou Imura
  • Patent number: 8680658
    Abstract: A clip for a semiconductor device package may include two or more separate electrically conductive fingers electrically connected to each other by one or more electrically conductive bridges. A first end of at least finger is adapted for electrical contact with a lead frame. The bridges are adapted to provide electrical connection to a top semiconductor region of a semiconductor device and may also to provide heat dissipation path when a top surface of the fingers is exposed. A semiconductor device package may include the clip along with a semiconductor device and a lead frame. The semiconductor device may have a first and semiconductor regions on top and bottom surfaces respectively. The clip may be electrically connected to the top semiconductor region at the bridges and electrically connected to the lead frame at a first end of at least one of the fingers.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: March 25, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lei Shi, Kai Liu, Ming Sun
  • Patent number: 8586857
    Abstract: A combined diode, lead assembly incorporating two expansion joints. The combined diode, lead assembly incorporating two expansion joints includes a diode having a first diode terminal and a second diode terminal, a first conductor and a second conductor. The first conductor includes a first terminal that is electrically coupled to the diode at the first diode terminal and a second terminal that is configured as a first expansion joint, which is configured to electrically couple to a first interconnecting-conductor and is configured to reduce a stress applied to the diode by the first conductor. The second conductor includes a first terminal that is electrically coupled to the diode at the second diode terminal and a second terminal that is configured as a second expansion joint, which is configured to electrically couple to a second interconnecting-conductor and is configured to reduce a stress applied to the diode by the second conductor.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: November 19, 2013
    Assignee: Miasole
    Inventors: Shawn Everson, Steven T. Croft, Whitfield G. Halstead, Jason S. Corneille
  • Patent number: 8525208
    Abstract: A light emitting device has a package having an opening provided with a side surface and a bottom surface, and a lead frame exposed to the bottom surface. The lead frame includes a reflection portion bent on the side surface, and a portion of an inner wall surface of the reflection portion is positioned in an inner portion of the package. A light emitting device has a package having a recessed portion on a front surface, a lead frame exposed to a bottom surface of the recessed portion, a light emitting element disposed on the lead frame, and a sealing resin filled into the recessed portion. The lead frame includes a bent portion bent towards the front surface of the package in the recessed portion, and a projecting portion bent to project from the package towards an outer portion, and disposed on a face opposed to the front surface.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: September 3, 2013
    Assignee: Nichia Corporation
    Inventors: Morito Kanada, Hideo Asakawa
  • Patent number: 8399999
    Abstract: An electronic component including an electronic element, an electrode that is formed on a first surface of the electronic element, a first resin layer that is formed over the first surface of the electronic element, a wiring that is electrically connected to the electrode, a first portion of the wiring extending over the first resin layer, a second resin layer that is formed over the first resin layer and the wiring, the second resin layer having an opening, the opening overlapping the first portion of the wiring, an external terminal that is provided above the second resin layer, the external terminal being connected to the first portion of the wiring via the opening, and a third resin layer that is formed over the second resin layer, the third resin layer being provided around the external terminal.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: March 19, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 8344499
    Abstract: A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: January 1, 2013
    Assignee: Alpha & Omega Semiconductor, Inc
    Inventors: Yuping Gong, Yan Xun Xue
  • Patent number: 8299602
    Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least one row or ring which at least partially circumvents the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: October 30, 2012
    Assignee: Amkor Technology, Inc.
    Inventors: Yeon Ho Choi, GiJeong Kim, WanJong Kim
  • Patent number: 8235551
    Abstract: A light-emitting diode (LED) module and an LED packaging method. As the LED module is packaged under the consideration of candela distribution, each of the lead frames of the LED chips packaged in the LED module is bended for tilting the LED chips by different angles to exhibit various lighting effects. Meanwhile, in the LED packaging method, a plurality of LED chips can be loaded on board rapidly and aligned by one operation to result in less deviation in the candela distribution curve.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: August 7, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Jian-Shian Lin, Chieh-Lung Lai, Hsiu-Jen Lin, Weng-Jung Lu, Yi-Ping Huang, Ya-Chun Tu
  • Patent number: 8203200
    Abstract: A leadframe design for a diode or other semiconductor device that reduces stress on the device and provides increased heat dissipation is provided. According to various embodiments, the leadframe has a contoured profile including a recessed area and a raised surface within the recessed area. The surface supports the device such that the edges of the device extend past the surface. Also provided are device assemblies including the novel leadframes. In certain embodiments, the assemblies include one or more leadframes attached via a solder joint to a device. According to various embodiments, the leadframes are attached to the front side of the device, back side of the device or both. In particular embodiments, the device is a bypass diode for one or more solar cells in a solar module.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: June 19, 2012
    Assignee: Miasole
    Inventors: Whitfield G. Halstead, Steven Croft, Shawn Everson
  • Patent number: 8193041
    Abstract: The yield of a semiconductor device is improved. Inside the resin sealing body which forms a semiconductor device, the semiconductor chip is sealed in the state where it has arranged aslant to the upper and lower sides of a resin sealing body. In the suspension lead which supports the die pad carrying this semiconductor chip, the small recess is formed in the fifth surface of the opposite side with the surface on which the semiconductor chip was mounted. This recess is a portion used as the starting point when making die pad 2a slanting. The side surface of the side near a die pad between two side surfaces of this recess is formed in the state where it inclined rather than the side surface of the side near the periphery of a resin sealing body.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 5, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Shigeki Tanaka
  • Patent number: 8129227
    Abstract: A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes from the encapsulation about horizontally; the second portion forms a convex bend downwardly; the third portion is approximately straight downwardly; the fourth portion forms a concave bend upwardly; and the fifth portion is straight horizontally. Each segment has across the width a first groove in the third portion, either on the bottom surface or on the top surface. Preferably, the groove is about 2 leadframe thicknesses vertically over the bottom surface of the fifth lead portion. When stamped, the groove may have an angular outline about 5 and 50 ?m deep; when etched, the groove may have an approximately semicircular outline about 50 to 125 ?m deep. A second groove may be located in the second segment portion; a third groove may be located in the transition region from the third to the fourth segment portions.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: March 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: John P Tellkamp
  • Patent number: 8106418
    Abstract: A light emitting device includes a first lead and a second lead. The first lead has a top surface which a light emitting element is mounted thereon and a bottom surface opposed to the top surface. The second lead has a lead peripheral region where a wire connected to an electrode of the light emitting element is bonded therewith. The first lead includes a lead middle region where the semiconductor light emitting element is mounted thereon to thermally conduct therewith. A bottom surface of the lead middle region is exposed from a package. The second lead has an outer lead region that is projected outwardly from the both side surfaces of the package. The bottom surface of the first lead middle region is substantially coplanar with a bottom surface of the outer lead region.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: January 31, 2012
    Assignee: Nichia Corporation
    Inventor: Yoshitaka Bando
  • Patent number: 8097934
    Abstract: A lead frame and package construction configured to attain a thin profile and low moisture sensitivity. Lead frames of this invention may include a die attach pad having a die attachment site and an elongate ground lead that extends from the die attach pad. The lead frame includes a plurality of elongate I/O leads arranged about the die attach pad and extending away from the die attach pad in at least two directions. An inventive lead frame features “up-set” bonding pads electrically connected with the die attach pad and arranged with a bonding surface for supporting a plurality of wire bonds. The bonding surfaces also constructed to define at least one mold flow aperture for each up-set bonding pad. A package incorporating the lead frame is further disclosed such that the package includes an encapsulant that surrounds the bonding support and flows through the mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: January 17, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Felix C. Li, Yee Kim Lee, Peng Soon Lim, Terh Kuen Yii, Lee Han Meng@Eugene Lee
  • Patent number: 8089166
    Abstract: An integrated circuit package system includes a bottom pad with a bottom tie bar, attaching an integrated circuit die over the bottom pad, attaching a top pad with a top tie bar, over the integrated circuit die, and applying an encapsulant wherein the top tie bar integral to the top pad, is exposed on a side of the encapsulant.
    Type: Grant
    Filed: December 30, 2006
    Date of Patent: January 3, 2012
    Assignee: Stats Chippac Ltd.
    Inventor: OhSug Kim
  • Patent number: 8076183
    Abstract: A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: December 13, 2011
    Assignee: Alpha and Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Jun Lu, Le Shi, Liang Zhao
  • Patent number: 8072051
    Abstract: Semiconductor packages and methods for making and using the same are described. The semiconductor packages contain a lead frame that has been folded to create folded leads that form a customized array of land pads and vias. The lead frame contains both longer folded lead and shorter folded leads. The longer leads can be folded so that an upper part of the longer leads form vias, the lower part forms part of a land pad array, and a substantially flat part that is connected to a first die containing an IC. The shorter leads can be folded so that a lower part forms part of a land pad array and the short leads are connected to a second die containing in IC. The folded leads can be routed according to the requirements of each specific IC die to which they are connected and therefore can support multiple dies in the semiconductor package. Other embodiments are also described.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: December 6, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Manolito Galera, Leocadio Alabin, In Suk Kim
  • Patent number: 8008758
    Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least one row or ring which at least partially circumvents the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: August 30, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Gi Jeong Kim, Wan Jong Kim
  • Patent number: 7960815
    Abstract: A semiconductor package includes a leadframe. A first lead finger has a lower portion, a connecting portion extending vertically upward from the lower portion, and a substantially flat, top portion. The top portion forms a top terminal lead structure. A second lead finger is electrically connected to the first lead finger. A portion of the second lead finger forms a bottom terminal lead structure. A portion of the second lead finger corresponds to a bottom surface of the semiconductor package. A surface of the substantially flat, top portion corresponds to a top surface of the semiconductor package.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: June 14, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Henry D. Bathan, Jose Alvin Santos Caparas, Lionel Chien Hui Tay
  • Patent number: 7902657
    Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: March 8, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jocel P. Gomez
  • Patent number: 7867827
    Abstract: A physical quantity sensor is constituted using a lead frame having at least one stage and a plurality of leads whose bases are arranged in the same plane, wherein at least one physical quantity sensor chip having a plurality of electrode pads is mounted on the stage and is inclined so that the electrode pads are disposed in the inclination direction and are connected to the leads by use of wires whose lengths substantially match distances between the electrode pads and leads. This prevents the leads and wires from being unexpectedly broken, and it is possible to avoid the occurrence of separation of the leads from the physical quantity sensor chip. In addition, the tip ends of the leads are disposed along the surface of the inclined stage before wire bonding; hence, it is possible to easily connect the tip ends of the leads to the physical quantity sensor chip.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: January 11, 2011
    Assignee: Yamaha Corporation
    Inventors: Kenichi Shirasaka, Masayoshi Omura