Characterized By Bent Parts (epo) Patents (Class 257/E23.047)
  • Patent number: 9006869
    Abstract: A light emitting device package is provided comprising a light emitting device including at least one light emitting diode and a body including a first lead frame on which the light emitting device is mounted and a second lead frame spaced apart from the first lead frame, wherein at least one of the first and second lead frames is extending to a bending region in a first direction by a predetermined length on the basis of an outer surface of the body and is bent in a second direction intersecting the first direction.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 14, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: JaeJoon Yoon
  • Patent number: 8963307
    Abstract: Various embodiments related to a compact device package are disclosed herein. In some arrangements, a flexible substrate can be coupled to a carrier having walls angled relative to one another. The substrate can be shaped to include two bends. First and second integrated device dies can be mounted on opposite sides of the substrate between the two bends in various arrangements.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: February 24, 2015
    Assignee: Analog Devices, Inc.
    Inventor: David Bolognia
  • Patent number: 8872314
    Abstract: A method for producing a component and device including a component is disclosed. A basic substrate having paper as substrate material is provided, at least one integrated circuit is applied to the basic substrate, the at least one integrated circuit applied on the basic substrate is enveloped with an encapsulant, and at least parts of the basic substrate are removed from the at least one enveloped integrated circuit.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Horst Theuss, Albert Auburger, Jochen Dangelmaier, Josef Hirtreiter
  • Patent number: 8866296
    Abstract: A semiconductor device includes: a semiconductor chip with a plurality of electrode pads disposed at a top surface thereof; a plurality of thin film terminals set apart from one another via respective separator portions, which are located below a bottom surface of the semiconductor chip; an insulating layer disposed between the semiconductor chip and the thin-film terminals; connecting members that connect the electrode pads at the semiconductor chip with the thin-film terminals respectively and a resin layer disposed so as to cover the semiconductor chip, the plurality of thin-film terminals exposed at the semiconductor chip, the separator portions and the connecting members.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: October 21, 2014
    Assignee: AOI Electronics Co., Ltd.
    Inventors: Takashi Yamaji, Takaaki Kato
  • Patent number: 8823152
    Abstract: In one embodiment, a semiconductor package (e.g., a QFP package) includes a leadframe sized and configured to increase the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package includes a generally planar die pad defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions that are provided in at least one row or ring, which at least partially circumvents the die pad, with other leads including portions that protrude from respective side surfaces of a package body of the semiconductor package. At least one semiconductor die is connected to the top surface of the die pad and is electrically connected to at least some of the leads.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: September 2, 2014
    Assignee: Amkor Technology, Inc.
    Inventors: Gi Jeong Kim, Wan Jong Kim
  • Patent number: 8754510
    Abstract: A conduction path includes a first conduction path forming plate (11) made of a first metal and having a through hole (13), and a second conduction path forming plate (15) made of a second metal and having a press-fit portion (17) press-fitted into the through hole. A wall surface of the through hole and a side surface of the press-fit portion forms an inclined bonding surface (18) inclined relative to a normal line of an overlap surface of the first conduction path forming plate and the second conduction path forming plate, and a bonding portion (25) formed by metal flow is formed in a region located in a periphery of the inclined bonding surface.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: June 17, 2014
    Assignee: Panasonic Corporation
    Inventors: Masanori Minamio, Zyunya Tanaka, Ryoutarou Imura
  • Patent number: 8680658
    Abstract: A clip for a semiconductor device package may include two or more separate electrically conductive fingers electrically connected to each other by one or more electrically conductive bridges. A first end of at least finger is adapted for electrical contact with a lead frame. The bridges are adapted to provide electrical connection to a top semiconductor region of a semiconductor device and may also to provide heat dissipation path when a top surface of the fingers is exposed. A semiconductor device package may include the clip along with a semiconductor device and a lead frame. The semiconductor device may have a first and semiconductor regions on top and bottom surfaces respectively. The clip may be electrically connected to the top semiconductor region at the bridges and electrically connected to the lead frame at a first end of at least one of the fingers.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: March 25, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lei Shi, Kai Liu, Ming Sun
  • Patent number: 8586857
    Abstract: A combined diode, lead assembly incorporating two expansion joints. The combined diode, lead assembly incorporating two expansion joints includes a diode having a first diode terminal and a second diode terminal, a first conductor and a second conductor. The first conductor includes a first terminal that is electrically coupled to the diode at the first diode terminal and a second terminal that is configured as a first expansion joint, which is configured to electrically couple to a first interconnecting-conductor and is configured to reduce a stress applied to the diode by the first conductor. The second conductor includes a first terminal that is electrically coupled to the diode at the second diode terminal and a second terminal that is configured as a second expansion joint, which is configured to electrically couple to a second interconnecting-conductor and is configured to reduce a stress applied to the diode by the second conductor.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: November 19, 2013
    Assignee: Miasole
    Inventors: Shawn Everson, Steven T. Croft, Whitfield G. Halstead, Jason S. Corneille
  • Patent number: 8525208
    Abstract: A light emitting device has a package having an opening provided with a side surface and a bottom surface, and a lead frame exposed to the bottom surface. The lead frame includes a reflection portion bent on the side surface, and a portion of an inner wall surface of the reflection portion is positioned in an inner portion of the package. A light emitting device has a package having a recessed portion on a front surface, a lead frame exposed to a bottom surface of the recessed portion, a light emitting element disposed on the lead frame, and a sealing resin filled into the recessed portion. The lead frame includes a bent portion bent towards the front surface of the package in the recessed portion, and a projecting portion bent to project from the package towards an outer portion, and disposed on a face opposed to the front surface.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: September 3, 2013
    Assignee: Nichia Corporation
    Inventors: Morito Kanada, Hideo Asakawa
  • Patent number: 8399999
    Abstract: An electronic component including an electronic element, an electrode that is formed on a first surface of the electronic element, a first resin layer that is formed over the first surface of the electronic element, a wiring that is electrically connected to the electrode, a first portion of the wiring extending over the first resin layer, a second resin layer that is formed over the first resin layer and the wiring, the second resin layer having an opening, the opening overlapping the first portion of the wiring, an external terminal that is provided above the second resin layer, the external terminal being connected to the first portion of the wiring via the opening, and a third resin layer that is formed over the second resin layer, the third resin layer being provided around the external terminal.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: March 19, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 8344499
    Abstract: A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: January 1, 2013
    Assignee: Alpha & Omega Semiconductor, Inc
    Inventors: Yuping Gong, Yan Xun Xue
  • Patent number: 8299602
    Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least one row or ring which at least partially circumvents the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: October 30, 2012
    Assignee: Amkor Technology, Inc.
    Inventors: Yeon Ho Choi, GiJeong Kim, WanJong Kim
  • Patent number: 8235551
    Abstract: A light-emitting diode (LED) module and an LED packaging method. As the LED module is packaged under the consideration of candela distribution, each of the lead frames of the LED chips packaged in the LED module is bended for tilting the LED chips by different angles to exhibit various lighting effects. Meanwhile, in the LED packaging method, a plurality of LED chips can be loaded on board rapidly and aligned by one operation to result in less deviation in the candela distribution curve.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: August 7, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Jian-Shian Lin, Chieh-Lung Lai, Hsiu-Jen Lin, Weng-Jung Lu, Yi-Ping Huang, Ya-Chun Tu
  • Patent number: 8203200
    Abstract: A leadframe design for a diode or other semiconductor device that reduces stress on the device and provides increased heat dissipation is provided. According to various embodiments, the leadframe has a contoured profile including a recessed area and a raised surface within the recessed area. The surface supports the device such that the edges of the device extend past the surface. Also provided are device assemblies including the novel leadframes. In certain embodiments, the assemblies include one or more leadframes attached via a solder joint to a device. According to various embodiments, the leadframes are attached to the front side of the device, back side of the device or both. In particular embodiments, the device is a bypass diode for one or more solar cells in a solar module.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: June 19, 2012
    Assignee: Miasole
    Inventors: Whitfield G. Halstead, Steven Croft, Shawn Everson
  • Patent number: 8193041
    Abstract: The yield of a semiconductor device is improved. Inside the resin sealing body which forms a semiconductor device, the semiconductor chip is sealed in the state where it has arranged aslant to the upper and lower sides of a resin sealing body. In the suspension lead which supports the die pad carrying this semiconductor chip, the small recess is formed in the fifth surface of the opposite side with the surface on which the semiconductor chip was mounted. This recess is a portion used as the starting point when making die pad 2a slanting. The side surface of the side near a die pad between two side surfaces of this recess is formed in the state where it inclined rather than the side surface of the side near the periphery of a resin sealing body.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 5, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Shigeki Tanaka
  • Patent number: 8129227
    Abstract: A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes from the encapsulation about horizontally; the second portion forms a convex bend downwardly; the third portion is approximately straight downwardly; the fourth portion forms a concave bend upwardly; and the fifth portion is straight horizontally. Each segment has across the width a first groove in the third portion, either on the bottom surface or on the top surface. Preferably, the groove is about 2 leadframe thicknesses vertically over the bottom surface of the fifth lead portion. When stamped, the groove may have an angular outline about 5 and 50 ?m deep; when etched, the groove may have an approximately semicircular outline about 50 to 125 ?m deep. A second groove may be located in the second segment portion; a third groove may be located in the transition region from the third to the fourth segment portions.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: March 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: John P Tellkamp
  • Patent number: 8106418
    Abstract: A light emitting device includes a first lead and a second lead. The first lead has a top surface which a light emitting element is mounted thereon and a bottom surface opposed to the top surface. The second lead has a lead peripheral region where a wire connected to an electrode of the light emitting element is bonded therewith. The first lead includes a lead middle region where the semiconductor light emitting element is mounted thereon to thermally conduct therewith. A bottom surface of the lead middle region is exposed from a package. The second lead has an outer lead region that is projected outwardly from the both side surfaces of the package. The bottom surface of the first lead middle region is substantially coplanar with a bottom surface of the outer lead region.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: January 31, 2012
    Assignee: Nichia Corporation
    Inventor: Yoshitaka Bando
  • Patent number: 8097934
    Abstract: A lead frame and package construction configured to attain a thin profile and low moisture sensitivity. Lead frames of this invention may include a die attach pad having a die attachment site and an elongate ground lead that extends from the die attach pad. The lead frame includes a plurality of elongate I/O leads arranged about the die attach pad and extending away from the die attach pad in at least two directions. An inventive lead frame features “up-set” bonding pads electrically connected with the die attach pad and arranged with a bonding surface for supporting a plurality of wire bonds. The bonding surfaces also constructed to define at least one mold flow aperture for each up-set bonding pad. A package incorporating the lead frame is further disclosed such that the package includes an encapsulant that surrounds the bonding support and flows through the mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: January 17, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Felix C. Li, Yee Kim Lee, Peng Soon Lim, Terh Kuen Yii, Lee Han Meng@Eugene Lee
  • Patent number: 8089166
    Abstract: An integrated circuit package system includes a bottom pad with a bottom tie bar, attaching an integrated circuit die over the bottom pad, attaching a top pad with a top tie bar, over the integrated circuit die, and applying an encapsulant wherein the top tie bar integral to the top pad, is exposed on a side of the encapsulant.
    Type: Grant
    Filed: December 30, 2006
    Date of Patent: January 3, 2012
    Assignee: Stats Chippac Ltd.
    Inventor: OhSug Kim
  • Patent number: 8076183
    Abstract: A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: December 13, 2011
    Assignee: Alpha and Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Jun Lu, Le Shi, Liang Zhao
  • Patent number: 8072051
    Abstract: Semiconductor packages and methods for making and using the same are described. The semiconductor packages contain a lead frame that has been folded to create folded leads that form a customized array of land pads and vias. The lead frame contains both longer folded lead and shorter folded leads. The longer leads can be folded so that an upper part of the longer leads form vias, the lower part forms part of a land pad array, and a substantially flat part that is connected to a first die containing an IC. The shorter leads can be folded so that a lower part forms part of a land pad array and the short leads are connected to a second die containing in IC. The folded leads can be routed according to the requirements of each specific IC die to which they are connected and therefore can support multiple dies in the semiconductor package. Other embodiments are also described.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: December 6, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Manolito Galera, Leocadio Alabin, In Suk Kim
  • Patent number: 8008758
    Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least one row or ring which at least partially circumvents the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: August 30, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Gi Jeong Kim, Wan Jong Kim
  • Patent number: 7960815
    Abstract: A semiconductor package includes a leadframe. A first lead finger has a lower portion, a connecting portion extending vertically upward from the lower portion, and a substantially flat, top portion. The top portion forms a top terminal lead structure. A second lead finger is electrically connected to the first lead finger. A portion of the second lead finger forms a bottom terminal lead structure. A portion of the second lead finger corresponds to a bottom surface of the semiconductor package. A surface of the substantially flat, top portion corresponds to a top surface of the semiconductor package.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: June 14, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Henry D. Bathan, Jose Alvin Santos Caparas, Lionel Chien Hui Tay
  • Patent number: 7902657
    Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: March 8, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jocel P. Gomez
  • Patent number: 7867827
    Abstract: A physical quantity sensor is constituted using a lead frame having at least one stage and a plurality of leads whose bases are arranged in the same plane, wherein at least one physical quantity sensor chip having a plurality of electrode pads is mounted on the stage and is inclined so that the electrode pads are disposed in the inclination direction and are connected to the leads by use of wires whose lengths substantially match distances between the electrode pads and leads. This prevents the leads and wires from being unexpectedly broken, and it is possible to avoid the occurrence of separation of the leads from the physical quantity sensor chip. In addition, the tip ends of the leads are disposed along the surface of the inclined stage before wire bonding; hence, it is possible to easily connect the tip ends of the leads to the physical quantity sensor chip.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: January 11, 2011
    Assignee: Yamaha Corporation
    Inventors: Kenichi Shirasaka, Masayoshi Omura
  • Patent number: 7859121
    Abstract: A wiring board is provided with an external connection terminal to which an electrode terminal of an electronic component is to be connected. The external connection terminal is formed so that a portion thereof is electrically connected to a pad portion exposed from an outermost insulating layer on an electronic component mounting surface of a wiring board body and so that an air gap is kept between a portion of the external connection terminal, to which the electrode terminal of the electronic component is to be connected, and the insulating layer.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: December 28, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kiyoshi Oi
  • Patent number: 7855391
    Abstract: A lead frame and a light emitting device package using the same are disclosed. More particularly, a lead frame and a light emitting device package using the lead frame which can be easily manufactured and employ a multi-chip structure. The light emitting device package includes a first frame including a heat sink, a second frame coupled to an upper side of the first frame, the second frame including at least one pair of leads and a mount formed with a hole, and a molded structure for coupling the first and second frames to each other.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: December 21, 2010
    Assignees: LG Electronics Inc., LG Innotek Co., Ltd.
    Inventors: Kwang Suk Park, Yu Ho Won
  • Patent number: 7847392
    Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least one row or ring which at least partially circumvents the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: December 7, 2010
    Assignee: Amkor Technology, Inc.
    Inventors: Yeon Ho Choi, GiJeong Kim, WanJong Kim
  • Patent number: 7834432
    Abstract: A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: November 16, 2010
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd
    Inventors: Wu-Chang Tu, Geng-Shin Shen
  • Patent number: 7821124
    Abstract: Semiconductor die packages and methods of making them are disclosed. An exemplary package comprises a leadframe having a source lead and a gate lead, and a semiconductor die coupled to the source and gate leads at a first surface of the leadframe. The source lead has a protruding region at a second surface of the leadframe. A molding material is disposed around the semiconductor die, the gate lead, and the source lead such that a surface of the die and a surface of the protruding region are left exposed by the molding material. An exemplary method comprises obtaining the semiconductor die and leadframe, and forming a molding material around at least a portion of the leadframe and die such that a surface of the protruding region is exposed through the molding material.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: October 26, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Rajeev Joshi, Chung-Lin Wu
  • Patent number: 7808088
    Abstract: A semiconductor device comprises a die having a first surface and a second surface, a first leadframe connected to the first surface and the second surface, and a second leadframe connected to the first surface.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: October 5, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Bernhard P Lange
  • Patent number: 7777310
    Abstract: An integrated circuit package system is provided including forming a paddle, an outer lead, and an inner lead between the paddle and the outer lead; forming a non-vertical paddle edge of the paddle and a non-vertical lead edge of the inner lead facing the non-vertical paddle edge; and encapsulating an integrated circuit die over the paddle.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: August 17, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Henry Descalzo Bathan, Zigmund Ramirez Camacho, Arnel Trasporto
  • Patent number: 7755205
    Abstract: The present invention is a method of manufacturing a semiconductor device, by forming a wiring on or above a wafer so that the wiring is electrically connected to a first electrode disposed on a first surface of the wafer, forming a first resin layer on or above the wafer such that the wiring is disposed between the wafer and the first resin layer, forming an opening in the first resin layer such that the opening overlaps the wiring, forming a conductive member in the opening such that the conductive member being electrically connected to the wiring, forming a second electrode on the conductive member such that the second electrode is electrically connected to the wiring via the conductive member, and separating the wafer into individual elements after the forming of the first resin layer.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: July 13, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7719094
    Abstract: A semiconductor package includes a lead frame, at least one chip, and an encapsulation. The lead frame has a plurality of leads, and each of the leads includes at least one first conductive part, at least one second conductive part, and at least one third conductive part. The first conductive part is not electrically connected to the second conductive part, and the second conductive part is electrically connected to the third conductive part. The chip is electrically connected to the first conductive part. The encapsulation encapsulates the chip and at least a portion of the lead frame, and forms a first surface and a second surface opposite to the first surface. The first conductive part and the third conductive part are exposed from the first surface, and the second conductive part is exposed from the second surface.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: May 18, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chia-Fu Wu, Cheng-Yin Lee
  • Patent number: 7719027
    Abstract: The present invention provides an integrated circuit and the method of implementing the same. The integrated circuit includes a die, a base, a covering material and a plurality of pins. The die has at least a first function and a second function and includes a plurality of signal pads and at least a switching pad. The die receives and outputs signals through the signal pads, and the switching pad is utilized to switch the functions of the die. The base is utilized to support the die, and the covering material is utilized to cover the die and the base. One terminal of each pin is inside the covering material and coupled to the corresponding signal pad, and the other terminal of each pin is outside the covering material. The signal pads are connected to the circuits outside the integrate circuit through the pins.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: May 18, 2010
    Assignee: MStar Semiconductor, Inc.
    Inventor: ShouFang Chen
  • Patent number: 7675148
    Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: March 9, 2010
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Seung-won Lim, O-Seob Jeon, Joon-seo Son, Keun-hyuk Lee, Yun-hwa Choi
  • Patent number: 7652365
    Abstract: The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead frame structure may include a set of leads extending in a first direction and a dam bar. Each of the leads may have an outer length and an outer edge. The dam bar may include a plurality of dam bar elements, with each dam bar element being joined to the outer lengths of two adjacent leads. In this example, each dam bar element has an outer edge that extends farther outwardly than the outer edges of the two adjacent leads. The outer edges of the leads and the outer edges of the dam bar elements together define an irregular outer edge of the dam bar. Other lead frame structures and various microelectronic component assemblies are also shown and described.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: January 26, 2010
    Assignee: Micron Technologies, Inc.
    Inventor: Mark S. Johnson
  • Patent number: 7635613
    Abstract: A semiconductor device comprising a leadframe (903), which has first (903a) and second (903b) surfaces, a planar pad (910) of a certain size, and a plurality of non-coplanar members (913) adjoining the pad. The device further has a heat spreader (920) with first (920a) and second (920b) surfaces, a planar pad of a size matching the leadframe pad size, and contours (922), into which the leadframe members are inserted so that the first spreader pad surface touches the second leadframe pad surface across the pad size. A semiconductor chip (904) is mounted on the first leadframe pad surface. Encapsulation material (930), preferably molding compound, covers the chip, but leaves the second spreader surface uncovered.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: December 22, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Bernhard P. Lange, Steven A. Kummerl
  • Patent number: 7619307
    Abstract: A leadframe-based semiconductor package and a leadframe for the package are revealed. The semiconductor package primarily includes parts of the leadframe including one or more first leads, one or more second leads, and a supporting bar disposed between the first leads and the second leads and further includes a chip attached to the first leads, the second leads and the supporting bar, a plurality of bonding wires and an encapsulant. The supporting bar has an extended portion projecting from the first bonding finger and the second bonding finger and connected to a non-lead side of the encapsulant wherein the extended portion has an arched bend to absorb the pulling stresses and to block stress transmission. Cracks caused by delamination of the supporting bar will not be created during trimming the supporting bar along the non-lead side of the encapsulant. Moisture penetration along the cracks of the supporting bar to the die-bonding plane under the chip is desirably prevented.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: November 17, 2009
    Assignee: Powertech Technology Inc.
    Inventors: Chin-Fa Wang, Wan-Jung Hsieh, Yu-Mei Hsu
  • Patent number: 7615853
    Abstract: The present invention provides a chip-stacked package structure with leadframe having multi-piece bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips stacked together and provided on the die pad, the plurality of chips and the plurality of inner leads arranged in rows facing each other being electrically connected with each other; and an encapsulant provided to cover the chip-stacked structure and the leadframe; wherein the leadframe comprises at least a bus bar provided between the plurality of inner leads arranged in rows facing each other and the die pad, the bus bar being formed by multiple pieces.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: November 10, 2009
    Assignees: CHIPMOS Technologies Inc., CHIPMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, Wu-Chang Tu
  • Patent number: 7598600
    Abstract: The present invention provides a method of making a stackable power semiconductor package system comprising forming a lower lead frame, having an upward bent source lead and an upward bent gate lead, mounting a power semiconductor device on the lower lead frame utilizing interconnect structures and forming an upper lead frame wherein the upper lead frame is on the power semiconductor device.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: October 6, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Wai Kwong Tang, You Yang Ong, Kuan Ming Kan, Larry Lewellen
  • Publication number: 20090243056
    Abstract: A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.
    Type: Application
    Filed: June 8, 2009
    Publication date: October 1, 2009
    Applicants: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Wu-Chang Tu, Geng-Shin Shen
  • Patent number: 7595549
    Abstract: A surface mount semiconductor device using a lead frame can suppress stress applied to a package by a load in a forming process performed for the lead frame projecting from the package at a portion at which the lead frame projects the package. Concave portions can be provided in at least one lead of a pair of leads that project laterally from side faces of the package. The concave portions can be arranged at positions where the leads are bent approximately perpendicularly along the side faces of the package at respective central portions of the leads. Thus, a cross-sectional area of a bending portion of the lead can be reduced, thereby enabling the lead (or leads) to be easily bent with a smaller bending load. Therefore, a surface mount semiconductor device can be achieved which prevents disconnection without impairing a heat radiation property and which has good moisture resistance.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: September 29, 2009
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Toshimi Kamikawa, Hayato Oba, Shinichi Miyamura
  • Patent number: 7589400
    Abstract: The inverter has a plurality of arms for conducting or cutting off a current and each arm has a switching device and a first and a second wiring layer for connecting the switching device. The first and second wiring layers of each arm are respectively formed on insulating substrates, and one face of the switching device is fixed to the first wiring layer, and the second wiring layer and the other face of the switching device are electrically connected by a laminal conductor, and the laminal conductor has a first and a second connection, and the first connection of the laminal conductor is fixed to the other face of the switching device, and the second connection of the laminal conductor is fixed to the second wiring layer. Thereby, a large current of the inverter can be realized and the assembly capacity of the inverter or the vehicle drive unit will be improved.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: September 15, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Hozoji, Toshiaki Morita, Satoru Shigeta, Tokihito Suwa
  • Patent number: 7569920
    Abstract: An electronic component includes a vertical semiconductor power transistor and a further semiconductor device arranged on the transistor to form a stack. The first vertical semiconductor power transistor has a semiconductor body having a first side and a second side and device structures, at least one first electrode positioned on the first side and at least one second electrode positioned on the second side. The semiconductor body further has at least one electrically conductive via. The via extends from the first side to the second side of the semiconductor body and is galvanically isolated from the device structures of the semiconductor body and from the first electrode and the second electrode.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: August 4, 2009
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Klaus Schiess
  • Patent number: 7557454
    Abstract: A semiconductor device includes two or more semiconductor devices with bond pads that are electrically connected to the same, single surface of a plurality of leads. The two or more devices may include substantially centrally located bond pads or substantially identically arranged bond pads.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: July 7, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Todd O. Bolken
  • Publication number: 20090152710
    Abstract: Quad Flat No-Lead (QFN) packages are provided. An embodiment of a QFN package includes a semiconductor chip including an active surface and an inactive surface, a plurality of leads, a plurality of wire bonds configured to couple the plurality of leads to the semiconductor chip, and a mold material including a mounting side and having a perimeter. The active surface is oriented toward the mounting side, the plurality of wire bonds are disposed between the active surface and the mounting side within the mold material, and the plurality of leads are exposed on the mounting side and are at least partially encapsulated within the perimeter of the mold material.
    Type: Application
    Filed: January 8, 2009
    Publication date: June 18, 2009
    Applicant: Freescale Semiconductor, Inc.
    Inventors: James J. Wang, William G. McDonald
  • Patent number: 7541665
    Abstract: A magnetic sensor is constituted using magnetic sensor chips mounted on stages supported by interconnecting members and a frame having leads in a lead frame. Herein, the stages are inclined upon plastic deformation of the interconnecting members. When the frame is held in a metal mold and the stages are pressed, the interconnecting members are elastically deformed, so that the magnetic sensor chips are bonded onto the stages placed substantially in the same plane and are then wired with the leads. Thereafter, the stages are released from pressure, so that the interconnecting members are restored from the elastically deformed states thereof. When the magnetic sensor chips are combined together to realize three sensing directions, it is possible to accurately measure three-dimensional bearings of magnetism, and the magnetic sensor can be reduced in dimensions and manufactured with a reduced cost therefore.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: June 2, 2009
    Assignee: Yamaha Corporation
    Inventors: Hiroshi Adachi, Hiroshi Saitoh, Kenichi Shirasaka, Hideki Sato, Masayoshi Omura
  • Patent number: 7535087
    Abstract: By disposing a rear surface of a first island 12 and a top surface of a second island 13 so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip 20 are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: May 19, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hideyuki Inotsume, Hirokazu Fukuda
  • Patent number: 7535084
    Abstract: A multi-chip package with a single die pad is provided. The multi-chip package includes a leadframe having a die pad and a plurality of leads surrounding the die pad. Each of the leads includes an upper lead, a lower lead and an intermediate lead substantially perpendicularly connected to the upper and lower leads, wherein the upper and lower leads are substantially parallel to the die pad. The upper and lower surfaces of the die pad are attached with upper and lower chips respectively. The upper chip is electrically connected to the upper surface of one part of the upper leads by a plurality of first bonding wires and the lower chip is electrically connected to the lower surfaces of the other part of the upper leads by a plurality of second bonding wires. A sealant is used to encapsulate the chips and bonding wires to protect these elements from damage.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: May 19, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Hong Hyoun Kim