Abstract: A photosensitive resin composition comprising a photosensitive silicone compound of specified molecular weight having any of specified photosensitive substituents and a photopolymerization initiator in any of specified proportions is used. Thus, there can be obtained a resin composition containing a photosensitive silicone compound that provides a material suitable for a rewiring layer or a buffer coat material of LSI chip, less in a film loss between before and after curing and improved in the stickiness of pre-exposure stage. Further, there can be obtained a resin insulating film utilizing the resin composition.

Abstract: The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.

Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

Abstract: A semiconductor package comprises a substrate; a semiconductor die that comprises a set of one or more interconnects on one side to couple to the substrate; and a shape memory alloy layer provided on another side of the semiconductor die to compensate warpage of the semiconductor die. The shape memory alloy layer deforms with warpage of the semiconductor die and changes from the deformed shape to an original shape to flatten the semiconductor die in response to rise of a temperature during coupling of the die to the substrate.

Abstract: The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.

Abstract: A liquid epoxy resin composition comprising (A) a liquid epoxy resin; (B) an amine curing agent; (C) a nitrogen compound selected from the group consisting of organic acids salts of tertiary amines, amino acids, imino acids, and monoamine compounds having an alcoholic hydroxyl group in an amount of from 0.1 to 20 parts by weight per total 100 parts by weight of the components (A) and (B); and (D) an inorganic filler in an amount of from 50 to 900 parts by weight per 100 parts by weight of the component (A).

Abstract: In some embodiments an etchstop layer is deposited over a transistor that has been encapsulated by a high-K film, a silicon nitride is deposited over the deposited etchstop layer, the silicon nitride is removed, and the etchstop layer is removed. Other embodiments are described and claimed.

Abstract: The invention relates to a liquid resin composition for electronic components which is used in sealing of electronic components, comprising a liquid epoxy resin, a curing agent containing a liquid aromatic amine, and an inorganic filler, and further comprising at least one member selected from a hardening accelerator, silicone polymer particles, and a nonionic surfactant. There is thereby provided a liquid resin composition for electronic components, which is excellent in fluidity in narrow gaps, is free of void generation, is excellent in adhesiveness and low-stress characteristic and is excellent in fillet formation, as well as an electronic component device having high reliability (moisture resistance, thermal shock resistance), which is sealed therewith.

Abstract: A silicone resin composition is provided, which includes polysiloxane including (PSA1), (PSA2), (PSB) and (PSC), and a hydrosilylating catalyst, wherein a weight ratio between (PSA2) and (PSA1) (w2/w1) is 0.03-0.

Abstract: Disclosed are a semiconductor device wherein warping of a semiconductor chip due to a sudden temperature change can be prevented without increasing the thickness, and a semiconductor device assembly. The semiconductor device comprises a semiconductor chip, a front side resin layer formed on the front surface of the semiconductor chip by using a first resin material, and a back side resin layer formed on the back surface of the semiconductor chip by using a second resin material having a higher thermal expansion coefficient than the first resin material. The back side resin layer is formed thinner than the front side resin layer.

Abstract: A dicing die attachment film includes a die attachment layer attached to one surface of a semiconductor wafer; a dicing film layer attached to a dicing die that is used for cutting the semi-conductor wafer into die units; and an intermediate layer laminated between the die attachment layer and the dicing film layer. The intermediate layer has a modulus of 100 to 3000 MPa, which is greater than a modulus of the die attachment layer and the dicing film layer.

Abstract: A heterojunction between thin films of NCD and 4H—SiC was developed. Undoped and B-doped NCDs were deposited on both n? and p? SiC epilayers. I-V measurements on p+ NCD/n? SiC indicated Schottky rectifying behavior with a turn-on voltage of around 0.2 V. The current increased over eight orders of magnitude with an ideality factor of 1.17 at 30° C. Ideal energy-band diagrams suggested a possible conduction mechanism for electron transport from the SiC conduction band to either the valence band or acceptor level of the NCD film.

Abstract: A semiconductor package comprises a substrate; a semiconductor die that comprises a set of one or more interconnects on one side to couple to the substrate; and a shape memory alloy layer provided on another side of the semiconductor die to compensate warpage of the semiconductor die. The shape memory alloy layer deforms with warpage of the semiconductor die and changes from the deformed shape to an original shape to flatten the semiconductor die in response to rise of a temperature during coupling of the die to the substrate.

Abstract: A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, the semiconductor packages may be at least partially singulated from the panel by making one or more cuts through the panel to define one or more edges of the semiconductor package. The one or more edges may be smoothed by applying a laminate to the edges. The edges receiving the laminate may include any edge between a top and bottom surface of the package.

Abstract: A wafer level semiconductor package has a substrate and an RF module and baseband module coupled to the substrate with solder bumps. An underfill material is disposed under the RF module and baseband module. A first shielding layer is applied to a first surface of the substrate. A seed layer is deposited on the substrate and RF module and baseband module. A second shielding layer is plated over the seed layer, except over the contact pads on the substrate. The second shielding layer can be made from copper, gold, nickel, or aluminum. The first and second shielding layers substantially cover the wafer level semiconductor package to isolate the baseband module from electromagnetic interference generated by the RF module. The first and second shielding layers are grounded through the substrate.

Abstract: A method of applying encapsulant to wire bonds between a die and conductors on a supporting substrate, by forming a bead of the encapsulant on a profiling surface, positioning the profiling surface such that the bead contacts the die and, moving the profiling surface relative to the die to cover the wire bonds with the encapsulant. Wiping the encapsulant over the wire bonds with a profiling surface provides control of the encapsulant front as well as the height of the encapsulant relative to the die. The movement of the profiling surface relative to the die can closely controlled to shape the encapsulant to a desired form. Using the example of a printhead die, the encapsulant can be shaped to present an inclined face rising from the nozzle surface to a high point over the wire bonds. This can be used by the printhead maintenance facilities to maintain contact pressure on the wiping mechanism.

Abstract: A semiconductor device includes a molding resin layer and a semiconductor element encapsulated with the molding resin layer. The molding resin layer has an opening. A surface of the semiconductor element is partially exposed outside the molding resin layer through the opening. A groove is located in the surface of the semiconductor element around the opening of the molding resin layer. The groove is filled with the molding resin layer to produce anchor effect that enhances adhesive force of the molding resin layer to the surface of the semiconductor element around the opening.

Abstract: A chip package comprises a substrate, a chip, a conductive layer and a molding compound. The substrate has a carrying surface and at least a ground pad disposed on the carrying surface. The chip has an active surface and a back surface opposite thereto. The chip is bonded to the substrate with the active surface facing towards the carrying surface of the substrate, wherein the ground pad is disposed outside of the chip. The conductive layer covers the chip and a portion of the carrying surface, and electrically connects to the ground pad. The molding compound is disposed on the carrying surface of the substrate and encapsulates the chip and the conductive layer.

Abstract: A method of producing an insulator thin film, for forming a thin film on a substrate by use of the atomic layer deposition process, includes a first step of forming a silicon atomic layer on the substrate and forming an oxygen atomic layer on the silicon atomic layer, and a second step of forming a metal atomic layer on the substrate and forming an oxygen atomic layer on the metal atomic layer, wherein the concentration of the metal atoms in the insulator thin film is controlled by controlling the number of times the first step and the second step are carried out.

Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

Abstract: Disclosed is a semiconductor device having a wafer level package structure which is characterized by containing a resin layer composed of a resin composition which is curable at 250° C. or less. Such a semiconductor device having a wafer level package structure is excellent in low stress properties, solvent resistance, low water absorbency, electrical insulation properties, adhesiveness and the like.

Abstract: An aluminum nitride (AlN) thin-film is applied over thin-film metallic circuitry such as an environmental sensor, on the side edges of electrode pads, and/or over some or all of the surface area of a substrate. The thin-film acts to protect the encapsulated structures from exposure to oxidation and from reducing and vacuum environments, electrically insulates the encapsulated structures from other structures, and helps to securely adhere the structures to the substrate surface. The AlN thin-film can also enable multiple IC layers to be stacked on top of each other, with AlN thin-film interlayers employed between IC layers such that each IC layer is separated and electrically insulated from adjacent layers.

Abstract: A semiconductor product including a substrate, a semiconductor chip fitted to the substrate, and a layer, which contains coated particles, located adjacent to the semiconductor chip, wherein the coated particles have a ferromagnetic, ferrimagnetic or paramagnetic core and a coating.

Abstract: A packaged semiconductor device may include a substrate including at least one device layer and at least one connector arranged thereon, and a resin cover covering each side of the substrate, the resin cover on at least one side of the substrate including an opening exposing the connector and the resin cover on at least one other side of the substrate exposing a portion of the substrate.

Abstract: A microelectronic die and a package including the die. The die comprises a die substrate including a base and a die passivation layer disposed on the base. The die passivation layer includes a nanocomposite including a matrix and nanoparticles dispersed within the matrix.

Abstract: A semiconductor light-emitting device having a semiconductor light-emitting chip; a high refractive index lens covering around the semiconductor light-emitting chip; and a resin having fine particles mixed therein that fills a space between the semiconductor light-emitting chip and the lens is provided. In the semiconductor light emitting device, the resin having fine particles mixed therein is composed of an optically transparent resin into which a large number of high refractive fine particles having a mean diameter of 100 nm or less and composed of a dielectric material are mixed uniformly to have a distance 200 nm or less between respective particles.

Abstract: A semiconductor packaging stress relief technique with enhanced reliability. Reliability is enhanced over conventional post wirebond assembly die coating processes by forming a peripheral wall on the semiconductor die isolating the stress sensitive area from remaining area in the semiconductor die, and depositing die coat material constraining the flow of the die coat material in the stress sensitive area of the semiconductor die. The peripheral wall, by constraining flow of the die coat material, prevents stress on the package bond wires caused by mismatch in coefficient of thermal expansion between the die coat and the package bond wires which are encased in the plastic molding compound.

Abstract: A semiconductor device includes a plastic housing and a semiconductor chip, wherein the semiconductor chip includes an active top side and a rear side. An interposer is arranged on the active top side of the semiconductor chip. At least a portion of the interposer is embedded into the plastic housing, while the top side of the interposer forms the top side of the semiconductor device. A top side fitting shape is arranged on the top side of the interposer, where the top side fitting shape has a predetermined radius of curvature that is free of plastic housing composition, and the top side fitting shape has a convex or concave lens-shaped sphere segment shape.

Abstract: A routing element for use in a semiconductor device assembly includes a substrate that carries conductive traces that provide either additional electrical paths or shorter electrical paths than those provided by a carrier substrate of the semiconductor device assembly. The conductive traces may be carried upon a single surface of the routing element substrate, be carried internally by the routing element substrate, or include externally and internally carried portions. The routing element may also include a contact pad positioned at each end of each conductive trace thereof to facilitate electrical connection of each conductive trace to a corresponding terminal of the substrate or to a corresponding bond pad of a semiconductor device of the multichip module. Multichip modules are also disclosed, as are methods for designing the routing element and methods in which the routing element is used.

Abstract: A method of fabricating a titanium silicide nitride (TiSiN) layer of a semiconductor device may include forming a gate electrode on a semiconductor substrate and forming spacers on sidewalls of the gate electrode, forming a source and a drain in the semiconductor substrate, and forming TiSiN layers on the gate electrode and the source and the drain, respectively. Further, a semiconductor device may include a gate electrode, a spacer formed on sidewalls of the gate electrode, a source and a drain, wherein TiSiN layers are formed on the gate electrode, the source and the drain, respectively.

Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

Abstract: An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.

Abstract: A method of fabricating a semiconductor device includes forming a gate insulating film on an upper surface of a silicon substrate, forming a polycrystalline silicon film on the gate insulating film, and etching the polycrystalline silicon film, the gate insulating film, and the silicon substrate with a patterned coating type carbon film and a silicon nitride film so that first and second trenches are simultaneously formed. The first trench has a first width and a first depth and the second trench has a second width larger than the first width and the second depth larger than the first depth.

Abstract: Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.

Abstract: A method of fabricating a dielectric film comprising atoms of Si, C, O and H (hereinafter SiCOH) that has improved insulating properties as compared with prior art dielectric films, including prior art SiCOH dielectric films that are not subjected to the inventive deep ultra-violet (DUV) is disclosed. The improved properties include reduced current leakage which is achieved without adversely affecting (increasing) the dielectric constant of the SiCOH dielectric film. In accordance with the present invention, a SiCOH dielectric film exhibiting reduced current leakage and improved reliability is obtained by subjecting an as deposited SiCOH dielectric film to a DUV laser anneal. The DUV laser anneal step of the present invention likely removes the weakly bonded C from the film, thus improving leakage current.

Abstract: A method of manufacturing a semiconductor device sealed in a cured silicone body by placing an unsealed semiconductor device into a mold and subjecting a curable liquid silicone composition that fills the spaces between the mold and the unsealed semiconductor device to compression molding under a predetermined molding temperature, wherein the curable liquid silicone composition has viscosity of 90 Pa·s or less at room temperature, a time interval from the moment directly after measurement of a torque with a curometer at the molding temperature to the moment when the torque reached 1 kgf·cm being not less than 1 min.

Abstract: The semiconductor device has a security coating with embedded magnetic particles and magnetoresistive sensors. This renders possible a measurement of the impedance of security elements defined by magnetoresistive sensors and security coating. If initial values of the impedance are stored, actual values can be compared therewith to see if the device has not been electrically probed or modified. Such a comparison can be used to check the authenticity of the device.

Abstract: The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward, forming a second resin film for covering the electronic parts, obtaining an insulation film by curing the first and second resin films by heat treatment, forming a via hole in a predetermined portion of the insulation film on the wiring pattern and the connection terminal, and forming an upper wiring pattern connected to the wiring pattern and the connection terminal through the via hole, on the insulation film.

Abstract: An edge-sealed barrier film composite. The composite includes a substrate and at least one initial barrier stack adjacent to the substrate. The at least one initial barrier stack includes at least one decoupling layer and at least one barrier layer. One of the barrier layers has an area greater than the area of one of the decoupling layers. The decoupling layer is sealed by the first barrier layer within the area of barrier material. An edge-sealed, encapsulated environmentally sensitive device is provided. A method of making the edge-sealed barrier film composite is also provided.

Abstract: An IC device is packaged for accelerated transient particle emission by doping the underfill thereof with a transient-particle-emitting material having a predetermined, substantially constant emission rate. The emission rate may be tunable. In one aspect, a radioactive adhesive composition is provided for bonding a semiconductor device to a chip carrier. The radioactive adhesive composition is made from a cured reaction product including a resin and a filler, and may be reworkable or non-reworkable. Either the resin or the filler, individually or both together as a mix, are doped substantially uniformly with the transient-particle-emitting material, thereby putting the transient-particle-emitting in close proximity with the IC to be tested. The underfill is formulated to have a stable chemistry, and the doped particles are encapsulated, so as to contain the emissions. Accelerated transient-particle-emission testing may then be performed on the IC in situ to provide accelerated detection of soft errors.

Abstract: An apparatus including a contact point formed on a device layer of a circuit substrate or an interconnect layer on the substrate; a first dielectric material; and a different second polymerizable dielectric material on the substrate and separated from the device layer or the interconnect layer by the first dielectric material following polymerization, the second dielectric material comprising a glass transition temperature of at least 250° C. and a thermal decomposition temperature of at least 400° C. A method including depositing a dielectric material and thermally treating the dielectric material at a temperature greater than the thermal decomposition temperature.

Abstract: An article includes a substrate, a transition layer, and a diamond like carbon film. The transition layer is directly formed on a surface of the substrate. The diamond like carbon film is deposited on the transition layer, in contact therewith. The diamond like carbon film includes a nitrogen-doped diamond like carbon layer, a nitrogen-hydrogen doped diamond like carbon layer, and a hydrogen-doped diamond like carbon layer formed on the transition layer, in series. The nitrogen-doped diamond like carbon layer, in particular, is immediately adjacent the transition layer.

Abstract: The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region received about a peripheral edge of the semiconductor substrate. A layer including amorphous carbon is provided over the substrate outer surface. A masking layer is provided outwardly of the amorphous carbon-including layer. A resist layer is provided outwardly of the masking layer. At least a portion of the peripheral region of the outer surface includes the amorphous carbon-including layer and the resist layer, but is substantially void of the masking layer. The amorphous carbon-including layer is patterned using the resist layer and the masking layer effective to form a mask over the semiconductor substrate. After the patterning, the semiconductor substrate is processed inwardly of the mask through openings formed in the mask.