Device Being Completely Enclosed (epo) Patents (Class 257/E23.124)
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Patent number: 7839004Abstract: To provide a semiconductor device and a semiconductor module in which breakage of a semiconductor element due to a pressing force given from the outside is prevented. A semiconductor device according to the present invention has a configuration mainly including an island, a semiconductor element mounted on a front surface of the island, a lead that functions as an external connection terminal, and a sealing resin that covers these components in an integrated manner and mechanically supports them. Further, a through-hole is provided so as to penetrate the sealing resin. A front surface of the sealing resin around the through-hole forms a flat part. The front surface of the sealing resin that overlaps the semiconductor element is depressed inward with respect to the flat part to form a depressed part.Type: GrantFiled: July 30, 2009Date of Patent: November 23, 2010Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventor: Haruhiko Sakai
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Publication number: 20100289134Abstract: A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate having a component side and a system side; coupling stacking interconnects on the component side; and forming an integrated circuit receptacle, for receiving an integrated circuit device, by molding a reinforced encapsulant on the component side and exposing a portion of the stacking interconnects.Type: ApplicationFiled: May 11, 2010Publication date: November 18, 2010Inventors: Seng Guan Chow, Il Kwon Shim, Heap Hoe Kuan, Youngcheol Kim
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Patent number: 7821124Abstract: Semiconductor die packages and methods of making them are disclosed. An exemplary package comprises a leadframe having a source lead and a gate lead, and a semiconductor die coupled to the source and gate leads at a first surface of the leadframe. The source lead has a protruding region at a second surface of the leadframe. A molding material is disposed around the semiconductor die, the gate lead, and the source lead such that a surface of the die and a surface of the protruding region are left exposed by the molding material. An exemplary method comprises obtaining the semiconductor die and leadframe, and forming a molding material around at least a portion of the leadframe and die such that a surface of the protruding region is exposed through the molding material.Type: GrantFiled: December 20, 2007Date of Patent: October 26, 2010Assignee: Fairchild Semiconductor CorporationInventors: Rajeev Joshi, Chung-Lin Wu
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Publication number: 20100258937Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.Type: ApplicationFiled: June 23, 2010Publication date: October 14, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Il Kwon Shim, Yaojian Lin, Seng Guan Chow
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Publication number: 20100258957Abstract: A semiconductor package structure and encapsulating module for molding the same and an encapsulating mold for molding the same are provided. The encapsulating mold is used for packaging a substrate having a chip so as to mold the substrate having the chip as a package structure. The encapsulating mold has a pressing surface, a smooth surface and a cavity. The smooth surface having a curvature radius is connected with the pressing surface and disposed at a mouth of the cavity. When the encapsulating mold and an encapsulating lower mold are jointed to hold the substrate, the pressing surface contacts and presses the substrate.Type: ApplicationFiled: October 14, 2009Publication date: October 14, 2010Inventors: Cheng-Chang Shen, Chen-Tsung Chang, Chih-Yuan Lin
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Patent number: 7812431Abstract: A leadframe includes a die pad and a plurality of leads corresponding to the die pad. The die pad for supporting a die is formed with a plurality of sides, each of the sides having at least one recess portion and at least one protrusion portion. The leads are substantially coplanar to the die pad. The leads include a plurality of first leads and a plurality of second leads. The first leads extend into the recess portions respectively, and the second leads are aligned with the protrusion portions. The length of the first leads is greater than that of the second leads. The length of wires electrically connecting the die to the leads or the die pad can be adjusted by the sides of the leadframe with the recess portion and the protrusion portion having a dimension corresponding to the leads, so as to save the manufacture cost of the leadframe.Type: GrantFiled: June 5, 2008Date of Patent: October 12, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Su-Tai Yang, Kuang-Chun Chou, Wen-Chi Cheng
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Patent number: 7807505Abstract: Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other.Type: GrantFiled: August 30, 2005Date of Patent: October 5, 2010Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Alan G. Wood
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Publication number: 20100244228Abstract: The extent of a bow of a semiconductor device is suppressed in a case where the fillet width of an underfill resin is asymmetrical. The center position 12 of a chip 1 is caused to deviate from the center position 13 of a wiring substrate 2 in a direction (the direction of the arrow B) reverse to the deviation direction (the direction of the arrow A) of the center position 11 of an underfill resin 4 from the center position 12 of the chip 1. The center position 14 of a resin for encapsulation 6 is caused to deviate from the center position 13 of the wiring substrate 2 in the same direction (the direction of the arrow A) as the deviation direction (the direction of the arrow A) of the center position 11 of the underfill resin 4 from the center position 12 of the chip 1.Type: ApplicationFiled: March 19, 2010Publication date: September 30, 2010Applicant: NEC ELECTRONICS CORPORATIONInventors: Kenji Sakata, Tsuyoshi Kida
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Patent number: 7804159Abstract: A semiconductor device is disclosed which includes a tab (5) for use in supporting a semiconductor chip (8), a seal section (12) as formed by sealing the semiconductor chip (8) with a resin material, more than one tab suspension lead (4) for support of the tab (5), a plurality of electrical leads (2) which have a to-be-connected portion as exposed to outer periphery on the back surface of the seal section (12) and a thickness reduced portion as formed to be thinner than said to-be-connected portion and which are provided with an inner groove (2e) and outer groove (2f) in a wire bonding surface (2d) as disposed within the seal section (12) of said to-be-connected portion, and wires (10) for electrical connection between the leads (2) and pads (7) of the semiconductor chip (8), wherein said thickness reduced portion of the leads (2) is covered by or coated with a sealing resin material while causing the wires (10) to be contacted with said to-be-connected portion at specified part lying midway between the outerType: GrantFiled: June 30, 2004Date of Patent: September 28, 2010Assignees: Renesas Electronics Corporation, Hitachi Yonezawa Electronics Co., Ltd.Inventor: Yoshihiko Shimanuki
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Patent number: 7800237Abstract: An electronic device includes a stack of electronic components and connecting elements. The component stack includes two components stacked one on top of another by their top sides. Contact areas are arranged on the top sides of the components, and the contact areas include external contact structures as connecting elements. The external contact structures on the contact areas include rib and/or trench structures oriented in such a way that the rib and/or trench structures of the contact areas of the components stacked one on top of another cross or intersect each other.Type: GrantFiled: June 19, 2007Date of Patent: September 21, 2010Assignee: Infineon Technologies AGInventor: Jochen Reisinger
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Publication number: 20100230796Abstract: A method for making an integrated circuit package-in-package system includes: forming a first integrated circuit package including a first device and a first substrate and having a first interface; stacking a second integrated circuit package including a second device and a second substrate and having a second interface above the first integrated circuit package; and fitting the first interface directly on the second interface.Type: ApplicationFiled: April 30, 2010Publication date: September 16, 2010Inventors: Choong Bin Yim, Hyeog Chan Kwon, Jong-Woo Ha
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Patent number: 7794127Abstract: A light emitting diode (10) includes an LED chip (14) and an encapsulant (16) enclosing the LED chip. The LED chip has a light emitting surface (141), and the encapsulant has a light output surface (161) over the light emitting surface. The light output surface defines a plurality of annular, concentric grooves (163). Each groove is cooperatively enclosed by a first groove wall (165) and a second groove wall (166). The first groove wall is a portion of a circumferential side surface of a cone, and a conical tip of the cone is located on the light emitting surface of the LED chip.Type: GrantFiled: April 15, 2008Date of Patent: September 14, 2010Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.Inventors: Chung-Yuan Huang, Jer-Haur Kuo, Ye-Fei Yu, Lin Yang, Xin-Xiang Zha
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Patent number: 7791192Abstract: An integrated circuit package has a substrate; a discrete capacitor coupled to a first surface of the substrate; an integrated circuit die coupled to the first surface of the substrate over the discrete capacitor; and a lid coupled to the substrate, the lid encapsulating the integrated circuit die and the discrete capacitor.Type: GrantFiled: January 27, 2006Date of Patent: September 7, 2010Assignee: Xilinx, Inc.Inventors: Mukul Joshi, Kumar Nagarajan
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Patent number: 7786591Abstract: A cavity or die down ball grid array package includes an interposer substrate structure attached to the die. In an example, the interposer substrate reduces the interconnect length from a board to which the package mounts to power and ground pads on a top layer of the semiconductor or integrated circuit (IC) die. In this example, the interposer substrate also removes the requirement that power and ground pads be located on a periphery of the die. Power and ground pads can be located in an interior region on a top metal layer where they can be interconnected to the interposer substrate using electrically conductive bumps or wire bond(s).Type: GrantFiled: September 29, 2004Date of Patent: August 31, 2010Assignee: Broadcom CorporationInventors: Reza-ur Rahman Khan, Sam Ziqun Zhao
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Patent number: 7786576Abstract: A semiconductor device includes a substrate having a resin layer on at least a surface thereof; a thin-film circuit layer provided on the substrate, and a reinforcing section provided on the surface of the substrate so as to surround the thin-film circuit layer.Type: GrantFiled: January 31, 2008Date of Patent: August 31, 2010Assignee: Seiko Epson CorporationInventor: Taimei Kodaira
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Publication number: 20100213597Abstract: A semiconductor element mounting board includes: aboard having surfaces; a semiconductor element mounted on one of the surfaces of the board; a first layer into which the semiconductor element is embedded, the first layer being provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer. In such a semiconductor element mounting board, each of the surface layers has rigidity higher than that of each of the first and second layers. It is preferred that in the case where a Young's modulus of each surface layer at 25° C. is defined as X GPa and a Young's modulus of the first layer at 25° C.Type: ApplicationFiled: October 15, 2008Publication date: August 26, 2010Applicant: SUMITOMO BAKELITE COMPANY LIMITEDInventors: Mitsuo Sugino, Hideki Hara, Toru Meura
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Patent number: 7777327Abstract: A chip package structure including a substrate, a circuit layer, a solder mask, a chip, and an encapsulant is provided. The circuit layer is disposed on the substrate and includes two traces and a dummy trace. The dummy trace is disposed between the traces. The solder mask covers the circuit layer and the substrate. The chip is disposed on the solder mask and electrically connected to the traces. The encapsulant covers the solder mask and wraps the chip. The traces and the dummy trace extend from the inside of the area covered by the encapsulant to the outside of the area covered by the encapsulant. Because the dummy trace is used in the chip package structure, it can be avoided that the traces is pulled apart when the redundant encapsulant is removed after the encapsulant is formed.Type: GrantFiled: July 13, 2007Date of Patent: August 17, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Ching-Chun Hsieh
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Publication number: 20100200980Abstract: This semiconductor device has a frame including a bed portion on which a semiconductor chip is mounted, lead groups arranged in an outer peripheral portion, first bus bars, second bus bars and a rectifying bus bar. The first bus bars and the second bus bars are arranged between the bed portion and the lead groups. The rectifying bus bar is arranged in a region where the second bus bar is not arranged. Wire bonding is not performed on the rectifying bus bar. The rectifying bus bar includes a third bus bar having at least one end joined to a lead or a hanging pin and/or a fourth bus bar formed by extending the first bus bar in an outer peripheral direction in which the leads are arranged. The semiconductor device is provided in which deformation and damage of bonding wires when molding a resin sealed body are prevented.Type: ApplicationFiled: February 4, 2010Publication date: August 12, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Taku Tsumori
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Patent number: 7772657Abstract: The present invention provides three-dimensional force input control devices for use in sensing vector forces and converting them into electronic signals for processing in a electronic signal processing system with all components within die fabricated from the single semiconductor substrate. In some embodiments, the die has an elastic element, a frame formed around said elastic element, at least three mechanical stress sensitive IC components located in the elastic element, at rigid island element which transfers an external vector force to the elastic element and through the IC components provides electrical output signal, this rigid island has a height bigger than the thickness of the frame element, an external force-transferring element coupling the rigid island element with an external force and electronic circuit for processing output signals from the mechanical stress sensitive IC components.Type: GrantFiled: January 4, 2007Date of Patent: August 10, 2010Inventor: Vladimir Vaganov
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Publication number: 20100187672Abstract: According to an aspect of the present invention, there is provided an electronic apparatus including: a housing; a circuit board that is housed in the housing; a semiconductor package that includes a first surface on which solder balls are provided and a second surface opposite to the first surface and that is mounted on the circuit board so as to be electrically connected to the circuit board through the solder balls; a protective film that has a water repellency and that is applied on the circuit board so as to expose around the semiconductor package mounted on the circuit board; and a joint member that joins at least a part of a side surface of the semiconductor package and the circuit board.Type: ApplicationFiled: November 19, 2009Publication date: July 29, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Nobuhiro Yamamoto
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Publication number: 20100176499Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.Type: ApplicationFiled: March 19, 2010Publication date: July 15, 2010Applicant: ROHM CO., LTD.Inventor: Kazutaka Shibata
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Patent number: 7750465Abstract: A packaged integrated circuit has an integrated circuit over a support structure. A plurality of bond wires connected between active terminals of the integrated circuit and the support structure. An encapsulant overlies the support structure, the integrated circuit, and the bond wires. The encapsulant has a first open location in the encapsulant so that a first bond wire is exposed and a second open location in the encapsulant so that a second bond wire is exposed. First and second conductive structures are exposed outside the packaged integrated circuit and are located at the first and second open locations, respectively, and electrically connected to the first and second bond wires, respectively.Type: GrantFiled: February 28, 2007Date of Patent: July 6, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Kevin J. Hess, Chu-Chung Lee
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Publication number: 20100164126Abstract: The present invention provides a resin composition. The resin composition is used for a resin spacer provided in a semiconductor device. The semiconductor device comprises of a substrate, a semiconductor element mounted on an interposer so as to face the substrate, and the resin spacer provided between the substrate and the interposer or the semiconductor element for bonding them together in a state that a space is formed between the substrate and the semiconductor element. The resin composition comprises an alkali solubility resin, a photopolimerization resin, and a particulate filler. An average particle size of the particulate filler is in the range of 0.05 to 0.35 ?m. An amount of the particulate filler contained in the resin composition is in the range of 1 to 40 wt %. Further, the present invention also provides a resin spacer film. The resin spacer film is constituted of the resin composition described above.Type: ApplicationFiled: May 23, 2008Publication date: July 1, 2010Applicant: Sumitomo Bakelite Company LimitedInventors: Toyosei Takahashi, Rie Takayama
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Publication number: 20100117223Abstract: A semiconductor module includes a base plate, at least one semiconductor chip mounted on the base plate, a case fixed to the base plate and surrounding the at least one semiconductor chip, an electrically insulating gel layer covering the at least one semiconductor chip, a thermosetting resin layer formed on top of the gel layer, and a lid formed on top of the thermosetting resin layer. The lid comprises a lid-extension, which defines a lid-opening. The lid-opening extends through the thermosetting resin layer to the gel layer and allows gel of the gel layer to expand into the lid-opening.Type: ApplicationFiled: January 19, 2010Publication date: May 13, 2010Applicant: ABB Technology AGInventors: Dominik TRUESSEL, Daniel SCHNEIDER
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Publication number: 20100109148Abstract: When a second semiconductor chip is mounted onto a first semiconductor chip, collision of the first semiconductor chip with a lead frame is to be prevented. The lead frame has a die pad and suspending leads for supporting the die pad. A joining portion is provided over the lead frame. The first semiconductor chip is provided over the lead frame through the joining portion. The second semiconductor chip is provided over the first semiconductor chip. A resin member covers the die pad and the first and second semiconductor chips. The joining portion is positioned over each of the die pad and the suspending leads.Type: ApplicationFiled: October 22, 2009Publication date: May 6, 2010Inventors: Kunihiro Yamashita, Kazushi Hatauchi, Naoki Izumi, Akira Yamazaki
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Patent number: 7705444Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.Type: GrantFiled: March 9, 2004Date of Patent: April 27, 2010Assignee: Rohm Co., Ltd.Inventor: Kazutaka Shibata
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Publication number: 20100096737Abstract: Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die. The method further includes attaching a lead frame to the lateral contacts of the stacked first and second dies.Type: ApplicationFiled: October 20, 2008Publication date: April 22, 2010Applicant: Micron Technology, Inc.Inventor: Swee Kwang Chua
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Patent number: 7701043Abstract: A connecting tape made of insulating material is adhered between a stage unit 21 and a stage unit 22. The stage units 21 and 22 form united stage units by that. Therefore, edge parts 211 and 221 of the stage units 21 and 22 are bound by the connecting tape 41 and of which movements are restricted. The united stage units 21 and 22 are securely supported by support units 31 and 32 and support units 33 and 34. As a result, number of the support units is reduced and inner lead 12 consumed.Type: GrantFiled: September 21, 2007Date of Patent: April 20, 2010Assignee: Yamaha CorporationInventor: Shinya Ohkawa
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Patent number: 7692278Abstract: In some embodiments, an apparatus and a system are provided. The apparatus and the system may comprise a first integrated circuit die comprising a plurality of silicon vias and a first surface activated bonding site coupled to the plurality of silicon vias, and a second integrated circuit die comprising a second surface activated bonding site coupled to the first surface activated bonding site. The first surface activated bonding site may comprise a first clean metal and the second surface activated bonding site may comprise a second clean metal. If the first surface activated bonding site is coupled to the second surface activated bonding site respective metal atoms of the first activated surface activated bonding site are diffused into the second surface activated bonding site and respective metal atoms of the second activated surface activated bonding site are diffused into the first surface activated bonding site.Type: GrantFiled: December 20, 2006Date of Patent: April 6, 2010Assignee: Intel CorporationInventors: Shanggar Periaman, Kooi Chi Ooi, Bok Eng Cheah
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Publication number: 20100052138Abstract: This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin molded semiconductor device according to the invention includes bonding a semiconductor die on an island in a lead frame, electrically connecting the semiconductor die with the lead frame, resin-molding the lead frame on which the semiconductor die is bonded, and applying prior to the resin-molding a compressive pressure that is higher than a clamping pressure applied in the resin-molding to a region of the lead frame being clamped by molds in the resin-molding of the lead frame.Type: ApplicationFiled: August 12, 2009Publication date: March 4, 2010Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Kiyoshi Saito, Yuji Umetani, Hideaki Yoshimi
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Publication number: 20100052139Abstract: There is provided a semiconductor device which has been improved in adhesion between leads and a sealing resin (molding resin), and thus does not undergo peeling therebetween, and has high reliability.Type: ApplicationFiled: August 14, 2009Publication date: March 4, 2010Inventor: Tomio IWASAKI
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Patent number: 7663209Abstract: Provided are an inlet for an electronic tag comprising an insulating film, antennas each made of a conductor layer and formed over one surface of the insulating film, a slit formed in a portion of each of the antennas and having one end extending toward the outer edge of the antenna, a semiconductor chip electrically connected with each of the antennas via a plurality of bump electrodes, and a resin for sealing the semiconductor chip therewith; and a manufacturing process of the inlet. By the present invention, formation of a thin and highly-reliable inlet for a non-contact type electronic tag can be actualized.Type: GrantFiled: June 16, 2006Date of Patent: February 16, 2010Assignee: Renesas Technology Corp.Inventors: Michio Okamoto, Yuichi Morinaga, Yuji Ikeda, Takeshi Saito
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Patent number: 7663211Abstract: An integrated power device module having a leadframe structure with first and second spaced pads and one or more common source-drain leads located between said first and second pads, first and second transistors flip chip attached respectively to said first and second pads, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads, and a first clip attached to the drain of said first transistor and electrically connected to said one or more common source-drain leads. In another embodiment a partially encapsulated power quad flat no-lead package having an exposed top thermal drain clip which is substantially perpendicular to said with a folded stud exposed top thermal drain clip, and an exposed thermal source pad.Type: GrantFiled: July 27, 2007Date of Patent: February 16, 2010Assignee: Fairchild Semiconductor CorporationInventors: Jonathan A. Noquil, Ruben Madrid
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Patent number: 7663231Abstract: This invention provides an image sensor module with a three-dimensional die-stacking structure. By filling a conductive material into through silicon vias within at least one image sensor die, and into via holes within an insulating layer, vertical electrical connections are formed between the image sensor die and an image processor buried in the insulating layer. A plurality of solder bumps is formed on a backside of the image sensor module so that the module can be directly assembled onto a circuit board. The image sensor module of this invention is characterized by a wafer-level packaging architecture and a three-dimensional die-stacking structure, which reduces electrical connection lengths within the module and thus reduces an area and height of the whole packaged module.Type: GrantFiled: January 28, 2008Date of Patent: February 16, 2010Assignee: Industrial Technology Research InstituteInventors: Shu-Ming Chang, Tzu-Ying Kuo, Chia-Wen Chiang, Hsiang-Hung Chang
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Publication number: 20100007010Abstract: A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the sectional area of the block portion is bigger than that of the line portion. The pad is bonded to the block portion. The non-conductive adhesive material covers the pad and seals the whole block portion of the bonding wire.Type: ApplicationFiled: July 10, 2009Publication date: January 14, 2010Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsiao Chuan CHANG, Tsung Yueh TSAI, Yi Shao LAI, Ho Ming TONG, Jian Cheng CHEN, Wei Chi YIH, Chang Ying HUNG
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Patent number: 7646105Abstract: A integrated circuit package system includes: forming a package substrate with a top substrate side and a bottom substrate side; forming a corner contact in a first corner of the bottom substrate side, the corner contact extending to a substrate edge of the package substrate; mounting an integrated circuit device over the top substrate side; connecting an electrical interconnect between the integrated circuit device and the top substrate side; and forming a package encapsulation over the top substrate side, the integrated circuit device, and the electrical interconnect.Type: GrantFiled: November 16, 2007Date of Patent: January 12, 2010Assignee: Stats Chippac Ltd.Inventors: Seng Guan Chow, Tae Hoan Jang
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Publication number: 20090321948Abstract: A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process.Type: ApplicationFiled: June 27, 2008Publication date: December 31, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Dean Wang, Chien-Hsiun Lee, Chen-Shien Chen, Clinton Chao, Mirng-Ji Lii, Tjandra Winata Karta
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Patent number: 7635910Abstract: A semiconductor package is disclosed. In one embodiment, the semiconductor package includes a leadframe including a chip position and a plurality of leadfingers. Each leadfinger includes a cutout in an inner edge providing a chip recess. The semiconductor package further includes a semiconductor chip located in the chip recess. The semiconductor chip has an active surface with a plurality of chip contact pads on each of which an electrically conductive bump is disposed. The inner portions of the leadfingers protrude into the chip position and are electrically connected to the chip contact pads by electrically conductive bumps.Type: GrantFiled: January 20, 2005Date of Patent: December 22, 2009Assignee: Infineon Technologies AGInventors: Richard Mangapul Sinaga, Najib Khan Surattee, Mohamad Yazid
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Patent number: 7632708Abstract: Methods for making a microelectronic component including a plurality of conductive posts extending and projecting away from a flexible substrate, wherein at least some of the conductive posts are electrically connected to a plurality of traces exposed on the flexible substrate.Type: GrantFiled: December 27, 2005Date of Patent: December 15, 2009Assignee: Tessera, Inc.Inventors: Belgacem Haba, David B. Tuckerman
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Patent number: 7626255Abstract: Provided is a device, an assembly comprising said device, a sub-assembly and an element suitable for use in the assembly. The device comprises a body of an electrically insulating material having a first side and an opposite second side, the body being provided with conductors according to a desired pattern, said conductors being anchored in the body. The body is provided with a through-hole extending from the first side to the second side of the body and having a surfacial area which is smaller on the first side than on the second side. Such a device can very suitably be used in an assembly comprising an element which is a sensor, preferably a chemical sensor, and particularly a biosensor.Type: GrantFiled: October 14, 2004Date of Patent: December 1, 2009Assignee: Koninklijke Philips Electronics N.V.Inventors: Johannus Wilhelmus Weekamp, Menno Willem Jose Prins
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Patent number: 7618903Abstract: The patterning method includes forming a synthetic resin layer on a substrate, providing a mold in which a predetermined pattern is formed and metal particles are distributed on the surface of the mold, contacting the mold having the predetermined pattern with the synthetic resin layer, transferring the pattern of the mold onto the synthetic resin layer to form a patterned synthetic resin layer, and forming an organic layer on the patterned synthetic resin layer.Type: GrantFiled: May 26, 2006Date of Patent: November 17, 2009Assignee: LG Display Co., Ltd.Inventor: Gee Sung Chae
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Patent number: 7598605Abstract: A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while permitting signal transmission between these circuits. A second capacitive insulator on the second semiconductor substrate electrically isolates the primary and secondary side circuit while permitting signal transmission therebetween. First and second frames are provided for input and output of signals to and from the primary and secondary side circuits. External electrodes of the first and second capacitive insulators are connected together by a third lead frame via a conductive adhesive body including more than one solder ball. The first and second substrates and the lead frames are sealed by a dielectric resin.Type: GrantFiled: July 31, 2006Date of Patent: October 6, 2009Assignee: Hitachi, Ltd.Inventors: Noboru Akiyama, Minehiro Nemoto, Seigou Yukutake, Yasuyuki Kojima, Kazuyuki Kamegaki
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Publication number: 20090243056Abstract: A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.Type: ApplicationFiled: June 8, 2009Publication date: October 1, 2009Applicants: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.Inventors: Wu-Chang Tu, Geng-Shin Shen
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Publication number: 20090224385Abstract: A package structure of an integrated circuit device comprises a copper foil substrate, an integrated circuit device, a plurality of metal wires and an encapsulation material. The copper foil substrate comprises an IC bonding area, a plurality of conductive areas and an insulating dielectric material. The integrated circuit device is mounted on the surface of the IC bonding area, and is electrically connected to the plurality of conductive areas through the metal wires. The insulating dielectric material is between the IC bonding area and the conductive areas, and is also between two adjacent conductive areas. In addition, the encapsulation material covers the IC bonding area, the conductive areas and the integrated circuit device.Type: ApplicationFiled: March 3, 2009Publication date: September 10, 2009Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY INC.Inventors: SHIH HSIUNG CHAN, SHEN BO LIN, PIN CHUAN CHEN
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Patent number: 7582951Abstract: Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages is described. A die-up or die-down package includes a heat spreader cap defining a cavity, an IC die, and a leadframe. The leadframe includes a centrally located die attach pad, a plurality of leads, and a plurality of tie bars that couple the die attach pad to the leads. The IC die is mounted to the die attach pad. A planar rim portion of the cap that surrounds the cavity is coupled to the leadframe. The cap and the leadframe form an enclosure structure that substantially encloses the IC die, and shields EMI emanating from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.Type: GrantFiled: October 20, 2005Date of Patent: September 1, 2009Assignee: Broadcom CorporationInventors: Sam Ziqun Zhao, Reza-ur Rahman Khan
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Publication number: 20090212446Abstract: A semiconductor device including: a die pad, a die on the die pad, and resin encapsulating the die and forming an isolation thickness over the die pad, the resin including a mounting aperture and a major surface configured for mounting to an external device, the major surface having a non warpage compensation portion adjacent the die and a warpage compensation portion in a relatively thermally inactive zone with an approximate discontinuity and/or abrupt change in gradient between the non warpage compensation portion and the warpage compensation portion.Type: ApplicationFiled: February 25, 2008Publication date: August 27, 2009Inventors: Chai Wei Heng, Wae Chet Yong, Stanley Job Doraisamy, Khai Huat Jeffrey Low, Gerhard Deml
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Patent number: 7569920Abstract: An electronic component includes a vertical semiconductor power transistor and a further semiconductor device arranged on the transistor to form a stack. The first vertical semiconductor power transistor has a semiconductor body having a first side and a second side and device structures, at least one first electrode positioned on the first side and at least one second electrode positioned on the second side. The semiconductor body further has at least one electrically conductive via. The via extends from the first side to the second side of the semiconductor body and is galvanically isolated from the device structures of the semiconductor body and from the first electrode and the second electrode.Type: GrantFiled: May 10, 2006Date of Patent: August 4, 2009Assignee: Infineon Technologies AGInventors: Ralf Otremba, Klaus Schiess
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Publication number: 20090189260Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.Type: ApplicationFiled: March 25, 2009Publication date: July 30, 2009Applicants: RENESAS TECHNOLOGY CORP., HITACHI HOKKAI SEMICONDUCTOR, LTD.Inventors: Hajime HASEBE, Tadatoshi DANNO, Yukihiro SATOU
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Patent number: 7564142Abstract: An electronic device includes: a substrate on which an interconnect pattern is formed; a chip component having a first surface on which an electrode is formed and a second surface opposite to the first surface, the chip component being mounted in such a manner that the second surface faces the substrate; an insulating section formed of a resin and provided adjacent to the chip component; and an interconnect which is formed to extend from above the electrode, over the insulating section and to above the interconnect pattern.Type: GrantFiled: March 12, 2007Date of Patent: July 21, 2009Assignee: Seiko Epson CorporationInventor: Nobuaki Hashimoto
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Publication number: 20090176336Abstract: The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface of substrate 100; a process step in which the inner side of substrate 102 is fixed on lower die 130; a process step in which liquid resin 114 is supplied from nozzle 112 onto each of the semiconductor elements in order to cover at least a portion of each of semiconductor chips 102; a process step in which the upper die having plural cavities 144 formed in one surface is pressed onto the lower die, and liquid resin 114 is molded at a prescribed temperature by means of plural cavities 144; and a process step in which cavities 144 of upper die 140 are detached from the substrate, and plural molding resin portions are formed individually.Type: ApplicationFiled: March 9, 2009Publication date: July 9, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Yoshimi TAKAHASHI, Masazumi AMAGAI