Abstract: A semiconductor element mounting board includes: aboard having surfaces; a semiconductor element mounted on one of the surfaces of the board; a first layer into which the semiconductor element is embedded, the first layer being provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer. In such a semiconductor element mounting board, each of the surface layers has rigidity higher than that of each of the first and second layers. It is preferred that in the case where a Young's modulus of each surface layer at 25° C. is defined as X GPa and a Young's modulus of the first layer at 25° C.

Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.

Abstract: A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is molded to the substrate to provide rigidity and support to the substrate. The stiffener material can comprise a polymeric material molded to the substrate by a molding technique such as transfer molding, injection molding, and spray molding, or using an encapsulating material. One or more dies, chips, or other semiconductor or microelectronic devices can be disposed on the substrate to form a die assembly. The stiffener can be molded to a substrate comprising one or more dies, over which an encapsulating material can be applied to produce a semiconductor die package.

Abstract: A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal corner may be replaced with an orthogonal intersection between two trenches. The layout reduces the intersection area as well as the possibility of having partially etched materials left at the intersection area. The structure also includes an alternative way to fill the intersection area with either an un-etched small trapezoidal area or multiple un-etched square areas, so that the opening area at the intersection point is reduced and the possibility of having partially etched materials is reduced too.

Abstract: A semiconductor package structure and encapsulating module for molding the same and an encapsulating mold for molding the same are provided. The encapsulating mold is used for packaging a substrate having a chip so as to mold the substrate having the chip as a package structure. The encapsulating mold has a pressing surface, a smooth surface and a cavity. The smooth surface having a curvature radius is connected with the pressing surface and disposed at a mouth of the cavity. When the encapsulating mold and an encapsulating lower mold are jointed to hold the substrate, the pressing surface contacts and presses the substrate.

Abstract: A semiconductor die package is disclosed. The semiconductor die package includes a semiconductor die comprising an input at a first top semiconductor die surface and an output at a second bottom semiconductor die surface. A leadframe having a first leadframe surface and a second leadframe surface opposite the first leadframe surface is in the semiconductor die package and is coupled to the first top semiconductor die surface. A clip having a first clip surface and a second clip surface is coupled to the second bottom semiconductor die surface. A molding material having exterior molding material surfaces covers at least a portion of the leadframe, the clip, and the semiconductor die. The first leadframe surface and the first clip surface are exposed by the molding material, and the first leadframe surface, the first clip surface, and the exterior molding material surfaces of the molding material form exterior surfaces of the semiconductor die package.

Abstract: A semiconductor device includes at least bonding wires between electrode pads on a main surface of a semiconductor chip and connection pads on a wiring board. The wires form loop shapes from the electrode pads of the semiconductor chip. The semiconductor device also includes at least forming flat parts on the loop-shaped wires, and using a sealing material to seal the semiconductor chip such as to bury the flat parts.

Abstract: One aspect of the present invention involves a foil-based method for packaging integrated circuits. Initially, a metallic foil and a photoresist layer are attached with a carrier. The photoresist layer is exposed and patterned. Afterward, multiple integrated circuit dice are connected to the foil. The dice and portions of the foil are encapsulated in a molding material. The foil is then etched based on the patterned photoresist layer to define multiple device areas in the foil, where each device area supports at least one of the integrated circuit dice. Some aspects of the present invention relate to panel arrangements that are involved in the aforementioned method.

Abstract: A semiconductor package includes a semiconductor chip formed with a non-volatile semiconductor memory, a resin encapsulation that encapsulates the semiconductor chip, electrodes in a lattice (solder balls) formed and arrayed in a lattice on a bottom surface of the resin encapsulation. The solder balls include a signal electrode formed within the central region of the array and a dummy electrode formed outside the signal electrode.

Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.

Abstract: Methods and apparatus to provide die backside metallization and/or surface activated bonding for stacked die packages are described. In one embodiment, an active metal layer of a first die may be coupled to an active metal layer of a second die through silicon vias and/or a die backside metallization layer of the second die. Other embodiments are also described.

Abstract: A microelectronic chip comprises two parallel main faces and side faces. At least one of the faces comprises a recess provided with at least one electrical connection element and forming a housing for a wire element. The wire element simultaneously constitutes both an electrical connection between the chip and the outside via said connection element and a flexible mechanical support for said chip.

Abstract: A module, which in one embodiment may be a packaged millimeter waver module, includes a semiconductor lid portion; a packaging portion attached to the lid portion, wherein the packaging portion comprises a plurality of vias, a carrier portion, wherein a first semiconductor die is attached to the carrier portion, the packaging portion is attached to the carrier portion so that the packaging portion is over the carrier portion and the semiconductor die is within an opening in the packaging portion, and the lid portion and the carrier portion form an first air gap around the first semiconductor device.

Abstract: A method of implementing a capacitor in an integrated circuit package is disclosed. The method comprises coupling the capacitor to a first surface of a substrate of the integrated circuit package; positioning an integrated circuit die over the capacitor, wherein the integrated circuit die has a first plurality of solder bumps and a second plurality of solder bumps separated by a region having no solder bumps; coupling the integrated circuit die to the first surface of the substrate over the capacitor, wherein the region having no solder bumps is positioned over the capacitor; and encapsulating the integrated circuit die and the capacitor.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a paddle having an indented planar surface intersecting an outwardly extending planar surface at an angle of approximately 135 degrees plus 25 degrees or minus 5 degrees; mounting an integrated circuit over the paddle; and forming an encapsulation over the integrated circuit and under the extension void free.

Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; pressing an encapsulation onto the package carrier and with the integrated circuit therein; mounting a conductive frame, having a vertical pillar integral with a horizontal cover, through the encapsulation, over the integrated circuit, and the vertical pillar on the package carrier and the horizontal cover on the encapsulation; and forming a contact from the horizontal cover.

Abstract: A leadframe for use in fabricating a no lead semiconductor package contains connecting bars between individual electrical contact pads. For embodiments having a die pad, the leadframe further includes connecting bars between the contact pads and the die pad. The lower surfaces of the connecting bars are coplanar with the lower surfaces of the contact pads and/or the die pad, and the upper surfaces of the connecting bars are recessed with respect to the upper surfaces of the contact pads and/or the die pad. The semiconductor package is fabricated by encapsulating the die and the leadframe in a molding compound and then removing the connecting bars. The leadframe is typically formed by half etching a metal sheet to form the connecting bars. The connecting bars are removed from the encapsulated package by a selected cutting, sawing, or etching means, based on a predetermined pattern.

Abstract: A leadframe enhancing molding compound bondability includes a chip base and a pin holder. The chip bases includes a chip pad and a support, wherein the chip pad includes a side protrusion extending out of the support, and the side protrusion has a lower surface, and the support has a sidewall, and wherein the lower surface and the sidewall interconnect at an intersection line, and the lower surface is formed upwardly with a recess. Further, a pin holder includes a pin stand and a seat, wherein the pin stand has an edge portion extending out of the seat, the edge portion has a lower surface, the seat has a sidewall, and the lower surface and the sidewall interconnect at a crossing line. The lower surface of the pin stand is formed upward with a recess. As such, the bondability between the leadframe and the molding compound can be greatly enhanced.

Abstract: A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe strip system, having a stress relief slot and a leadframe unit, the stress relief slot is at a frame corner of the leadframe strip system and spans adjacent sides of the leadframe unit, the leadframe unit includes a paddle, a tie bar therefrom, and a lead finger; connecting an integrated circuit and the lead finger; forming an encapsulation covering the integrated circuit; and singulating the integrated circuit in the encapsulation from the leadframe strip system with a package corner of the encapsulation free of micro-cracks with an inspection of the package corner at least 50× view.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an interposer having an interposer first side and an interposer second side opposing the interposer first side; mounting an integrated circuit to the interposer first side, the integrated circuit having a non-active side and an active side with the non-active side facing the interposer; connecting first interconnects between the active side and the interposer first side, the first interconnects having a first density on the interposer first side; mounting the interposer over a package carrier with the interposer first side facing the package carrier; connecting second interconnects between the package carrier and the interposer second side, the second interconnects having a second density on the interposer second side, the second density that is approximately the same as the first density; and forming an encapsulation over the package carrier covering the interposer and the second interconnects.

Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.

Abstract: An integrated circuit package system including forming a leadframe having a lead with a leadfinger support of a predetermined height, and attaching an integrated circuit die with an electrical interconnect at a predetermined collapse height determined by the predetermined height of the leadfinger support.

Abstract: A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer.

Abstract: A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the sectional area of the block portion is bigger than that of the line portion. The pad is bonded to the block portion. The non-conductive adhesive material covers the pad and seals the whole block portion of the bonding wire.

Abstract: A method and device for one or more dimensional input control of different functions in electronic devices is provided. Certain versions of the Present Invention provide a one or more dimensional input force interface control device for cell phones, portable gamers, digital cameras, and other applications. Certain alternate versions of the Present Invention exhibit one or more of the qualities of smallness, low-cost, high reliability, and/or high stability. Certain still alternate versions of the Present Invention provide a three, two or one-dimensional input finger force control device that (1.) accommodates a required ratio between X, Y and Z sensitivities, (2.) has low cross-axis sensitivity, (3.) allows process integration with other sensors and CMOS, (4.) is scalable, (5.) allows convenient solutions for applying an external force, and/or (6.) allows economic manufacturability for high volume consumer markets.

Abstract: A leadless package system includes: providing a chip carrier having indentations defining a pattern for a protrusion for external contact terminals; placing an external coating layer in the indentations in the chip carrier; layering a conductive layer on top of the external coating layer; depositing an internal coating layer on the conductive layer; patterning the internal coating layer and the conductive layer to define external contact terminals with a T-shape profile; connecting an integrated circuit die to the external contact terminals; encapsulating the integrated circuit die and external contact terminals; and separating the chip carrier from the external coating layer.

Abstract: The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.

Abstract: In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including shortened electrical signal paths to optimize electrical performance. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In certain embodiments, a semiconductor package and one or more semiconductor dies are vertically stacked upon the substrate, and placed into electrical communication with the conductive pattern thereof. One or more of the semiconductor dies may include through-silicon vias formed therein for facilitating the electrical connection thereof to the conductive pattern of the substrate or to other electronic components within the vertical stack. Similarly, the semiconductor package may be provided with through-mold vias to facilitate the electrical connection thereof to other electronic components within the vertical stack.

Abstract: An integrated circuit package system is provided including forming an integrated circuit die, forming an interference-fit feature in the integrated circuit die, fitting a support element within the interference-fit feature, connecting an external interconnect and the integrated circuit die, and encapsulating the integrated circuit die.

Abstract: A wafer level chip size package (WLCSP) and a method of manufacturing the same are disclosed. Lands are formed at the ends of redistribution layers. The redistribution layers excluding the lands and a first dielectric layer are covered with a second dielectric layer. After forming a first under bump metallurgy (UBM) layer on the land, a solder ball is reflowed to the first UBM layer. A second UBM layer is widely formed on the entire second dielectric layer that is the outer circumference of the first UBM layer and is connected to the redistribution layer through a via-hole. Therefore, the second UBM layer having a large area can be used as a ground plane or a power plane. In addition, the second UBM layer can electrically connect the redistribution layers physically separated from each other. Therefore, the plurality of redistribution layers can cross each other without being electrically shorted with each other.

Abstract: A region divided substrate includes a substrate, a plurality of trenches, a conductive layer, and an insulating member. The substrate has a first surface and a second surface opposed to each other. The trenches penetrate the substrate from the first surface to the second surface and divide the substrate into a plurality of partial regions. The conductive layer is disposed on a sidewall of each of the trenches from a portion adjacent to the first surface to a portion adjacent to the second surface. The conductive layer has an electric conductivity higher than an electric conductivity of the substrate. The insulating member fills each of the trenches through the conductive layer.

Abstract: A system and method is disclosed for providing an integrated circuit that has increased radiation hardness and reliability. A device active area of an integrated circuit is provided and a layer of radiation resistant material is applied to the device active area of the integrated circuit. In one advantageous embodiment the radiation resistant material is silicon carbide. In another advantageous embodiment a passivation layer is placed between the device active area and the layer of radiation resistant material. The integrated circuit of the present invention exhibits minimal sensitivity to (1) enhanced low dose rate sensitivity (ELDRS) effects of radiation, and (2) pre-irradiation elevated temperature stress (PETS) effects of radiation.

Abstract: A semiconductor device with a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads (103) in pad locations has an encapsulated region on the top surface of the substrate, extending to the edge of the substrate, enclosing the chip, and having contact apertures (703) at the pad locations for external communication with the pad metal surfaces. The apertures may have not-smooth sidewall surfaces and may be filled with solder material (704) to contact the pads. Metal-filled surface grooves (710) in the encapsulated region, with smooth groove bottom and sidewalls, are selected to serve as customized routing interconnections, or redistribution lines, between selected apertures and thus to facilitate the coupling with another semiconductor device to form a package-on-package assembly.

Abstract: This invention discloses a method for packaging a semiconductor device with leads extending outside its encapsulation.

Abstract: A semiconductor device has a wiring substrate provided with an external connecting terminal on a lower surface, a semiconductor chip mounted onto an upper surface of the wiring substrate, a cap-shaped heat dissipation member arranged on the upper surface of the wiring substrate so as to cover the semiconductor chip, a fixing pin for fixing the heat dissipation member onto the upper surface of the wiring substrate, and a heat transfer material sandwiched between a lower surface of the heat dissipation member just above the semiconductor chip and the upper surface of the semiconductor chip.

Abstract: The size and thickness of a semiconductor device are reduced. A semiconductor package with a flip chip bonding structure includes: a semiconductor chip having a main surface with multiple electrode pads formed therein and a back surface located on the opposite side thereto; four lead terminals each having an upper surface with the semiconductor chip placed thereover and a lower surface located on the opposite side thereto; and a sealing body having a main surface and a back surface located on the opposite side thereto. In this semiconductor package, the distance between adjacent first lower surfaces of the four lead terminals exposed in the back surface of the sealing body is made longer than the distance between adjacent upper surfaces thereof.

Abstract: A semiconductor package with a support structure and a fabrication method thereof are provided. With a chip being electrically connected to electrical contacts formed on a carrier, a molding process is performed. A plurality of recessed portions formed on the carrier are filled with an encapsulant for encapsulating the chip during the molding process. After the carrier is removed, the part of the encapsulant filling the recessed portions forms outwardly protruded portions on a surface of the encapsulant, such that the semiconductor package can be attached to an external device via the protruded portions.

Abstract: Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the second substrate. At least one of the substrates may include a raised feature formed under at least one of the metal layers. One of the metal layer may have a diffusion barrier layer and a “keeper” layer formed thereover, wherein the keeper layers keeps the metal confined to a particular area. By using such a “keeper” layer, the substrate components may be heated to clean their surfaces, without activating or spending the bonding mechanism.

Abstract: A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, the semiconductor packages may be at least partially singulated from the panel by making one or more cuts through the panel to define one or more edges of the semiconductor package. The one or more edges may be smoothed by applying a laminate to the edges. The edges receiving the laminate may include any edge between a top and bottom surface of the package.

Abstract: A force input control device suitable for high-volume applications such as cell phones, portable gaming devices and other handheld electronic devices along with other applications like medical equipment, robotics, security systems and wireless sensor networks is disclosed. The device can be one-axis or two-axis or three-axis sensitive broadening the range of applications. The device comprises a force sensor die formed within semiconductor substrate and containing a force sensor providing electrical output signal in response to applied external force, and electrical connection elements for mounting and/or wire bonding. Signal conditioning and processing integrated circuit can be integrated within some devices. A package enclosing at least a portion of the force sensor die and comprising a force-transferring element cooperated with the sensor die for transferring an external force to the force sensor die.

Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.

Abstract: An electronic circuit having at least one electronic component comprised of an organic material, and arranged between at least two layers forming a barrier, wherein the layers protect the at least one component against an influence of light, air or liquid.

Abstract: A semiconductor device is disclosed that includes a wiring board having a via formed therein; a semiconductor element provided on the wiring board; a resist layer covering a surface of the wiring board, the resist layer having an opening in a part thereof positioned on the via; and a sealing resin covering the surface of the via in the opening and the resist layer, and sealing the semiconductor device.

Abstract: A leadframe with a structure made of a base metal (105), wherein the structure has a plurality of surfaces. On each of these surfaces are metal layers in a stack adherent to the base metal. The stack comprises a nickel layer (201) in contact with the base metal, a palladium layer (202) in contact with the nickel layer, and an outermost tin layer (203) in contact with the palladium layer. In terms of preferred layer thicknesses, the nickel layer is between about 0.5 and 2.0 ?m thick, the palladium layer between about 5 and 150 nm thick, and the tin layer less than about 5 nm thick, preferably about 3 nm. At this thinness, the tin has no capability of forming whiskers, but offers superb adhesion to polymeric encapsulation materials, improved characteristics for reliable stitch bonding as well as affinity to reflow metals (solders).

Abstract: A method of manufacture of an integrated circuit package system includes: forming a package substrate with a top substrate side and a bottom substrate side; forming a corner contact in a first corner of the bottom substrate side, the corner contact extending to a substrate edge of the package substrate; mounting an integrated circuit device over the top substrate side; connecting an electrical interconnect between the integrated circuit device and the top substrate side; and forming a package encapsulation over the top substrate side, the integrated circuit device, and the electrical interconnect.

Abstract: A protective structure is provided on a substrate to which a semiconductor die is attached. The protective structure surrounds the die and reduces the thermo-mechanical stresses to which the die is subject. The die is protected against cracking, warping, and delamination.

Abstract: A semiconductor device includes a wiring layer, a semiconductor chip which is arranged on the wiring layer with a gap there between, the semiconductor chip being electrically connected to the wiring layer through a connecting portion, a first sealing member which is filled in a space between the wiring layer and the semiconductor chip, and a second sealing member which coats the semiconductor chip. The first sealing member and the second sealing member include same organic resin, the organic resin including inorganic filler. The second sealing member has larger content of inorganic filler than the first sealing member.

Abstract: A package and a package assembly for a power device having a high operation voltage and impulse voltage are provided. The package assembly for a power device comprises an assembly wherein the power device is encapsulated and electrically connected to a lead protruding outside the package, and an isolation spacer filling a clearance distance between the package and a heat sink attached to the package.

Abstract: Embodiments of the present disclosure provide an apparatus comprising a semiconductor die, a bond pad formed on the semiconductor die, the bond pad comprising aluminum (Al), a bonding material comprising gold (Au) coupled to the bond pad, the bonding material covering at least a portion of the bond pad, and a wire coupled to the bonding material, the wire comprising copper (Cu). Other embodiments may be described and/or claimed.