Aluminum Alloys (epo) Patents (Class 257/E23.159)
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Patent number: 8963325Abstract: According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.Type: GrantFiled: January 11, 2013Date of Patent: February 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Baik-woo Lee, Young-hun Byun, Seong-woon Booh, Chang-mo Jeong
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Patent number: 8546923Abstract: Method for manufacturing a rigid power module with a layer that is electrically insulating and conducts well thermally and has been deposited as a coating, the structure having sprayed-on particles that are fused to each other, of at least one material that is electrically insulating and conducts well thermally, having the following steps: manufacturing a one-piece lead frame; populating the lead frame with semiconductor devices, possible passive components, and bonding corresponding connections, inserting the thus populated lead frame into a compression mold so that accessibility of part areas of the lead frame is ensured, pressing a thermosetting compression molding compound into the mold while enclosing the populated lead frame, coating the underside of the thus populated lead frame by thermal spraying in at least the electrically conducting areas and overlapping also the predominant areas of the spaces, filled with mold compound.Type: GrantFiled: June 27, 2011Date of Patent: October 1, 2013Assignee: Danfoss Silicon Power GmbHInventors: Ronald Eisele, Mathias Kock, Teoman Senyildiz
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Patent number: 8519513Abstract: A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.Type: GrantFiled: January 4, 2012Date of Patent: August 27, 2013Assignee: Freescale Semiconductor, Inc.Inventor: Trent S. Uehling
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Patent number: 8399313Abstract: A gate electrode is formed by forming a first conductive layer containing aluminum as its main component over a substrate, forming a second conductive layer made from a material different from that used for forming the first conductive layer over the first conductive layer; and patterning the first conductive layer and the second conductive layer. Further, the first conductive layer includes one or more selected from carbon, chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel. And the second conductive layer includes one or more selected from chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel, or nitride of these materials.Type: GrantFiled: July 19, 2011Date of Patent: March 19, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kengo Akimoto, Hotaka Maruyama
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Patent number: 8384222Abstract: A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.Type: GrantFiled: February 18, 2011Date of Patent: February 26, 2013Inventors: Chia-Lun Tsai, Ching-Yu Ni, Jack Chen, Wen-Cheng Chien
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Patent number: 8003449Abstract: A gate electrode is formed by forming a first conductive layer containing aluminum as its main component over a substrate, forming a second conductive layer made from a material different from that used for forming the first conductive layer over the first conductive layer; and patterning the first conductive layer and the second conductive layer. Further, the first conductive layer includes one or more selected from carbon, chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel. And the second conductive layer includes one or more selected from chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel, or nitride of these materials.Type: GrantFiled: November 22, 2005Date of Patent: August 23, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kengo Akimoto, Hotaka Maruyama
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Patent number: 7943518Abstract: A semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI is provided. A semiconductor substrate is provided with an element electrode having at least its surface constituted of an aluminum electrode. The surface of the aluminum electrode is roughened. An oxide film is provided on the aluminum electrode. A conductive film is provided on the oxide film. The aluminum electrode, oxide film and conductive film form a capacitor.Type: GrantFiled: August 24, 2007Date of Patent: May 17, 2011Assignee: Panasonic CorporationInventors: Koichi Hirano, Tetsuyoshi Ogura, Seiichi Nakatani
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Patent number: 7928575Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.Type: GrantFiled: May 14, 2009Date of Patent: April 19, 2011Assignee: Kobe Steel, Ltd.Inventors: Hiroshi Gotoh, Toshihiro Kugimiya, Junichi Nakai, Katsufumi Tomihisa
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Publication number: 20100117235Abstract: A metal line in a semiconductor device includes an insulation layer having trenches formed therein, a barrier metal layer formed over the insulation layer and the trenches, a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches, and an anti-galvanic corrosion layer formed on an interface between the metal layer and the barrier metal layer.Type: ApplicationFiled: January 15, 2010Publication date: May 13, 2010Applicant: Hynix Semiconductor Inc.Inventors: Young-Soo CHOI, Gyu-Hyun KIM
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Patent number: 7553754Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.Type: GrantFiled: June 21, 2006Date of Patent: June 30, 2009Assignee: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)Inventors: Hiroshi Gotoh, Toshihiro Kugimiya, Junichi Nakai, Katsufumi Tomihisa
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Publication number: 20090160057Abstract: A semiconductor device is provided in which penetration of a metal into a high impurity-doped active region from a side wall portion of a contact hole is prevented by reducing an aspect ratio to improve coverage of a titanium nitride film for the side wall portion of the contact hole, and in which increase in current consumption is eliminated. In a semiconductor device including an interlayer insulating film formed on a silicon substrate, and a interconnection formed of a barrier metal film and an aluminum alloy film and connected to the silicon substrate through a contact hole of the interlayer insulating film, a low-concentration impurity layer is epitaxially grown on a bottom surface of the contact hole, whereby the aspect ratio is reduced to improve coverage of the titanium nitride film for the side wall portion of the contact hole, and penetration of the metal into the high impurity-doped active region from the side wall portion of the contact hole is prevented.Type: ApplicationFiled: December 4, 2008Publication date: June 25, 2009Inventor: Yukimasa Minami
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Patent number: 7323783Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.Type: GrantFiled: December 6, 2004Date of Patent: January 29, 2008Assignee: NEC CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Takashi Inoue, Yasuhiro Okamoto, Masaaki Kuzuhara
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Patent number: 7224065Abstract: An improved method of forming a semiconductor device structure is disclosed, comprising insertion of a semiconductor wafer into a high-pressure heated chamber and the deposition of a low melting-point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The wafer is heated up to the melting point of the aluminum material and the chamber is pressurized to force the aluminum material into the contact holes or vias and eliminate voids present therein. A second layer of material, comprising a different metal or alloy, which is used as a dopant source, is deposited over an outer surface of the deposited aluminum material layer and allowed to diffuse into the aluminum material layer in order to form a homogenous aluminum alloy within the contact hole or via. A semiconductor device structure made according to the method is also disclosed.Type: GrantFiled: September 2, 2004Date of Patent: May 29, 2007Assignee: Micron Technology, Inc.Inventor: Trung T. Doan
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Patent number: 7193326Abstract: A mold type semiconductor device includes a semiconductor chip including a semiconductor part; a metallic layer; a solder layer; and a metallic member connecting to the semiconductor chip through the metallic layer and the solder layer. The solder layer is made of solder having yield stress smaller than that of the metallic layer. Even when the semiconductor chip is sealed with a resin mold, the metallic layer is prevented from cracking.Type: GrantFiled: June 3, 2004Date of Patent: March 20, 2007Assignee: DENSO CorporationInventors: Naohiko Hirano, Nobuyuki Kato, Takanori Teshima, Yoshitsugu Sakamoto, Shoji Miura, Akihiro Niimi