Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. A layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. Two first vias are formed over and in contact with the metal segment in the layout. EM rule is kept on the metal segment when a distance between the two first vias is greater than a threshold distance. The EM rule is relaxed on the metal segment when the distance between the two first vias is less than or equal to the threshold distance.

Abstract: This invention relates to a MOS device for making the source/drain region closer to the channel region and a method of manufacturing the same, comprising: providing an initial structure, which includes a substrate, an active region, and a gate stack; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer; with the first spacer as a mask, performing dry etching, thereby forming a recess, with the amorphous material layer below the first spacer kept; performing wet etching using an etchant solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or substantially equal to the etch rate to the {100} and {110} surfaces of the substrate material but is far greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first space

Abstract: A method for forming a raised silicide contact, the method including depositing a layer of silicon using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° and holding the temperature for about 0.1 miliseconds to about 600 seconds in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.

Abstract: A method of producing reduced corrosion interconnect structures and structures thereby formed. A method of producing microelectronic interconnects having reduced corrosion begins with a damascene structure having a first dielectric and a first interconnect. A metal oxide layer is deposited selectively to metal or nonselective over the damascene structure and then thermally treated. The treatment converts the metal oxide over the first dielectric to a metal silicate while the metal oxide over the first interconnect remains as a self-aligned protective layer. When a subsequent dielectric stack is formed and patterned, the protective layer acts as an etch stop, oxidation barrier and ion bombardment protector. The protective layer is then removed from the patterned opening and a second interconnect formed. In a preferred embodiment the metal oxide is a manganese oxide and the metal silicate is a MnSiCOH, the interconnects are substantially copper and the dielectric contains ultra low-k.

Abstract: A semiconductor structure includes a substrate, a bond pad over the substrate, and a passivation layer over the substrate and a peripheral region of the bond pad. The bond pad has a bonding region and the peripheral region surrounding the bonding region. The passivation layer has an opening defined therein, and the opening exposes the bonding region of the bond pad. A first vertical distance between an upper surface of the passivation layer and a surface of the bonding region ranges from 30% to 40% of a second vertical distance between a lower surface of the passivation layer and an upper surface of the peripheral region.

Abstract: Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO3 in an SWC tool. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer by applying HNO3 to the annealed Ni/Pt layer in an SWC tool, annealing the Ni removed Ni/Pt layer, and removing unreacted Pt from the annealed Ni removed Ni/Pt layer. Embodiments include forming first and second gate electrodes on a substrate, spacers on opposite sides of each gate electrode, and Pt-containing NiSi on the substrate adjacent each spacer, etching back the spacers, forming a tensile strain layer over the first gate electrode, applying a first HNO3 in an SWC tool, forming a compressive strain layer over the second gate electrode, and applying a second HNO3 in an SWC tool.

Abstract: A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type silicide layer on the gate conductor and the source and drain regions of the second-type field effect transistor. The second-type silicide layer that is formed is different than the first-type silicide layer. For example, the first-type silicide layer and the second-type silicide layer can comprise different materials, different thicknesses, different crystal orientations, and/or different chemical phases, etc.

Abstract: A method of fabricating an electrical contact comprises the following steps. A substrate having at least a silicon region is provided. At least an insulation layer is formed on the substrate, wherein the insulation layer comprises at least a contact hole which exposes the silicon region. A metal layer is formed on sidewalls and bottom of the contact hole. An annealing process is performed to form a first metal silicide layer in the silicon region nearby the bottom of the contact hole. A conductive layer covering the metal layer and filling up the contact hole is then formed, wherein the first metal silicide layer is transformed into a second metal silicide layer when the conductive layer is formed.

Abstract: A packaged electronic device including an electronic device, a conductive structure, and an encapsulant. The encapsulant has chlorides and a negatively-charged corrosion inhibitor for preventing corrosion of the conductive structure.

Abstract: The present disclosure relates to an improved method of providing a Ni silicide metal contact on a silicon surface by electrodepositing a Ni film on a silicon substrate. The improved method results in a controllable silicide formation wherein the silicide has a uniform thickness. The metal contacts may be incorporated in, for example, CMOS devices, MEM (micro-electro-mechanical) devices, and photovoltaic cells.

Abstract: A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type silicide layer on the gate conductor and the source and drain regions of the second-type field effect transistor. The second-type silicide layer that is formed is different than the first-type silicide layer. For example, the first-type silicide layer and the second-type silicide layer can comprise different materials, different thicknesses, different crystal orientations, and/or different chemical phases, etc.

Abstract: A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.

Abstract: A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias.

Abstract: A semiconductor device includes: a semiconductor substrate; an underlying wiring on the semiconductor substrate; a resin film extending to the semiconductor substrate and the underlying wiring, and having a first opening on the underlying wiring; a first SiN film on the underlying wiring and the resin film, and having a second opening in the first opening; an upper layer wiring on the underlying wiring and part of the resin film; and a second SiN film on the upper layer wiring and the resin film, and joined to the first SiN film on the resin film. The upper layer wiring includes a Ti film, connected to the underlying wiring via the first and second openings, and an Au film on the Ti film. The first and second SiN films circumferentially protect the Ti film.

Abstract: A display device includes a metal conductive layer formed on a substrate, a transparent electrode film formed on the substrate and joined to the metal conductive layer and an interlayer insulating film isolating the metal conductive layer and the transparent conductive film. The metal conductive layer has a lower aluminum layer made of aluminum or aluminum alloy, an intermediate impurity containing layer made of aluminum or aluminum alloy containing impurities and formed on a substantially entire upper surface of the lower aluminum layer and an upper aluminum layer made of aluminum or aluminum alloy and formed on the intermediate impurity containing layer. In the interlayer insulating film and the upper aluminum layer, a contact hole penetrates therethrough and locally exposes the intermediate impurity containing layer, and the transparent electrode film is joined to the metal conductive layer in the intermediate impurity containing layer exposed from the contact hole.

Abstract: Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to form an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A suicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.

Abstract: A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.

Abstract: Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.

Abstract: This method for making complementary p and n MOSFET transistors with Schottky source and drain electrodes controlled by a gate electrode, comprising: making source and drain electrodes from a single silicide for both p and n transistors; segregating first impurities from groups II and III of the periodic table at the interface between the silicide and the channel of the p transistor, the complementary n transistor being masked; and segregating second impurities from groups V and VI of the periodic table, at the interface between the silicide and the channel of the n transistor, and the complementary p transistor being masked.

Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.

Abstract: To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti (titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to forma barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film.

Abstract: A pixel of an image sensor includes a polysilicon layer, and an active region which needs to be electrically coupled with the polysilicon layer, wherein the polysilicon layer extends over a portion of the active region, such that the polysilicon layer and the active region are partially overlapped, and the polysilicon layer and the active region are coupled through a buried contact structure.

Abstract: A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.

Abstract: A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and methods to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the line resistance and increases the mechanical strength of a metal interconnect. In another embodiment, a Group II element alloy is used to form a barrier layer, which, in addition to decreasing the line resistance and increasing the mechanical integrity, also increases the chemical integrity of a metal interconnect.

Abstract: An electronic component is described that includes a metallic layer on a substrate that is made of a semiconductor material and a diffusion barrier layer that is made of a material that has a small diffusion coefficient for the metal of the metallic layer which is formed between the metallic layer and the substrate.

Abstract: A method includes providing a mixture of molten indium and molten aluminum, and agitating the mixture while reducing its temperature until the aluminum changes from liquid phase to solid phase, forming particles distributed within the molten indium. Agitation of the mixture sufficiently to maintain the aluminum substantially suspended in the molten aluminum continues while further reducing the temperature of the mixture until the indium changes from a liquid phase to a solid phase. A metallic composition is formed, including indium and particles of aluminum suspended within the indium, the aluminum particles being substantially free from oxidation. The metallic (solder) composition can be used to form an assembly, including an integrated circuit (IC) device, at least a first thermal component disposed adjacent to the IC device, and a solder TIM interposed between and thermally coupled with each of the IC device and the first thermal component.

Abstract: A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.

Abstract: A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.

Abstract: A through substrate via (TSV) die includes a substrate including a topside semiconductor surface having active circuitry. The die includes a plurality of TSVs that each include an inner metal core that extend from the topside semiconductor surface to protruding TSV tips that extend out from the bottomside surface. A metal cap is on the protruding TSV tips that includes at least one metal layer that has a metal that is not in the inner metal core. A plurality of protruding warpage control features are on the bottomside surface lateral to the protruding TSV tips, wherein the plurality of protruding warpage control features do not have the protruding TSV tips thereunder. The plurality of protruding warpage control features can include the same metal layer(s) used for the metal cap.

Abstract: A contact plug 40 electrically connected to an impurity diffusion region between sidewalls of an adjacent pair of memory cells 1 is provided to pass through an interlayer dielectric film 18. A side wall of a contact hole 41 is covered with a sealing film 42 denser than the interlayer dielectric film 18. The contact plug 40 includes a barrier metal film 43 formed to cover a surface of the sealing film 42 and a bottom surface portion of the contact hole 41 and a metal plug 44 embedded in the contact hole 41 in a state surrounded by the barrier metal film 43.

Abstract: A method is disclosed for depositing multiple seed layers for metallic interconnects over a substrate, the substrate includes a patterned insulating layer which comprises an opening surrounded by a field, said opening has sidewalls and top corners, and the method including: depositing a continuous seed layer over the sidewalls, using a first set of deposition parameters; and depositing another seed layer over the substrate, including inside the at least one opening and over a portion of said field, using a second set of deposition parameters, wherein: the second set of deposition parameters includes one deposition parameter which is different from any parameters in the first set, or whose value is different in the first and second sets; the continuous seed layer has a thickness in a range from about 20 ? to not more than 250 ? over the field; and the combined seed layers leave sufficient room for electroplating inside the opening.

Abstract: A semiconductor device manufacturing method which prevents the resistance of a Ni silicide layer from increasing due to an additive element. First, a reaction control layer which contains a metallic element with an atomic number greater than Ni and does not contain Ni is formed over a silicon layer. Then, Ni is deposited over the reaction control layer and the silicon layer, reaction control layer and Ni are heat-treated to form a Ni silicide layer in the silicon layer. It is preferable that the reaction control layer be comprised of a metallic element with an atomic number greater than Ni.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A dummy pattern is formed between a fuse pattern and a semiconductor substrate so as to prevent the semiconductor substrate from being damaged, and a buffer pattern is formed between the dummy pattern and the semiconductor substrate, so that a dummy metal pattern primarily absorbs or reflects laser energy transferred to the semiconductor substrate during the blowing of the fuse pattern, and the buffer pattern secondarily reduces stress generated between the dummy pattern and the semiconductor substrate, resulting in the prevention of a defect such as a crack.

Abstract: Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of trenches are formed in the semiconductor body to define semiconductor lines comprising silicon between adjacent trenches, the semiconductor lines having sidewalls. A silicide precursor is deposited within the trenches to contact the sidewalls of the semiconductor lines, and a portion of the silicide precursor is removed to expose upper portions of the sidewalls and leave remaining strips of silicide precursor along the sidewalls. Silicide conductors are then formed by inducing reaction of the strips of silicide with the silicon of the semiconductor lines.

Abstract: A nickel alloy sputtering target and a nickel silicide film formed with such a target are provided and enable the formation of a thermally stable silicide (NiSi) film, scarcely causing the aggregation of films or excessive formation of silicides, having low generation of particles upon forming the sputtered film, having favorable uniformity and superior plastic workability to the target, and which is particularly effective for the manufacture of a gate electrode material (thin film). The nickel alloy sputtering target contains 22 to 46 wt % of platinum and 5 to 100 wtppm of one or more components selected from iridium, palladium, and ruthenium, and remainder is nickel and inevitable impurities.

Abstract: The present disclosure relates to an improved method of providing a Ni silicide metal contact on a silicon surface by electrodepositing a Ni film on a silicon substrate. The improved method results in a controllable silicide formation wherein the silicide has a uniform thickness. The metal contacts may be incorporated in, for example, CMOS devices, MEM (micro-electro-mechanical) devices, and photovoltaic cells.

Abstract: Electronic devices and design structures of electronic devices containing metal silicide layers. The devices include: a thin silicide layer between two dielectric layers, at least one metal wire abutting a less than whole region of the silicide layer and in electrical contact with the silicide layer.

Abstract: A method of forming nickel monosilicide is provided that includes providing a silicon-containing surface, and ion implanting carbon into the silicon-containing surface. A nickel-containing layer is formed on the silicon-containing surface. Alloying the nickel-containing surface and the silicon-containing surface layer to provide a nickel monosilicide. The present disclosure also provides a non-agglomerated Ni monosilicide contact that includes a carbon interstitial dopant present in a concentration ranging from 1×1019 atoms/cm3 to 1×1021 atoms/cm3.

Abstract: Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided.

Abstract: The present invention discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a local interconnect structure connected to the semiconductor substrate, and at least one via stack structure electrically connected to the local interconnect structure, wherein the at least one via stack structure comprises a via having an upper via and a lower via, the width of the upper via being greater than that of the lower via; a via spacer formed closely adjacent to the inner walls of the lower via; an insulation layer covering the surfaces of the via and the via spacer; a conductive plug formed within the space surrounded by the insulation layer, and electrically connected to the local interconnect structure. The present invention is applicable to manufacture of a via stack in the filed of manufacturing semiconductor.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern.

Abstract: A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines.

Abstract: A method of forming a low resistance contact structure in a semiconductor device includes forming a doped semiconductor region in a semiconductor substrate; forming a deep level impurity region at an upper portion of the doped semiconductor region; activating dopants in both the doped semiconductor region and the deep level impurity region by annealing; and forming a metal contact over the deep level impurity region so as to create a metal-semiconductor interface therebetween.

Abstract: In one embodiment, a lower interlayer dielectric layer, and first and second landing pads penetrating the lower interlayer dielectric layer are formed on a substrate. Interconnection patterns covering the second landing pads are formed on the lower interlayer dielectric layer. An etch stop layer is formed over the interconnection patterns. An upper interlayer dielectric layer filling a gap region between the interconnection patterns is formed on the etch stop layer. The upper interlayer dielectric layer is patterned to form a preliminary contact hole between the interconnection patterns, where the etch stop layer is exposed at the bottom of the preliminary contact hole. The preliminary contact hole is extended and the etch stop layer exposed by the extended preliminary contact hole is removed to form a first contact hole exposing the first landing pad. A buried contact plug is then formed within the first contact hole.

Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

Abstract: An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures.

Abstract: According to one embodiment, a semiconductor device includes an interlayer insulation film provided on a substrate including a Cu wiring, a via hole formed in the interlayer insulation film on the Cu wiring, a first metal film selectively formed on the Cu wiring in the via hole, functioning as a barrier to the Cu wiring, and functioning as a promoter of carbon nanotube growth, a second metal film formed at least on the first metal film in the via hole, and functioning as a catalyst of the carbon nanotube growth, and carbon nanotubes buried in the via hole in which the first metal film and the second metal film are formed.

Abstract: In an embodiment, a substrate arrangement is provided. The substrate arrangement may include a semiconductor substrate including a first contact portion and a second contact portion on a first surface of the semiconductor substrate, wherein the semiconductor substrate is arranged such that the first contact portion and the second contact portion face each other. The substrate arrangement may further include an electrical connector configured to connect the first contact portion and the second contact portion.

Abstract: A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.

Abstract: A semiconductor device includes a first interlayer insulating film formed on a semiconductor substrate; a second interlayer insulating film formed on the first interlayer film and including a plurality of grooves; a first barrier metal formed on inner surfaces of the grooves; a first interconnect part and a first bonding electrode part including a copper film formed on the first barrier metal; a second barrier metal formed on the first interconnect part and the first bonding electrode part; a second interconnect part including a metal film formed on the first interconnect part via the second barrier metal; a second bonding electrode part including a metal film formed on the first bonding electrode part via the second barrier metal; and a third interlayer insulating film formed on the second interlayer insulating film, the second interconnect part, and the second bonding electrode part, and including an opening that allows exposure of the surface of the second bonding electrode part.