Additional Layers Associated With Aluminum Layers, E.g., Adhesion, Barrier, Cladding Layers (epo) Patents (Class 257/E23.16)
  • Patent number: 9450037
    Abstract: There is provided a light emitting display apparatus including at least a light emitting element and a thin film transistor (TFT) for driving the light emitting element, characterized in that a mechanism is provided in which a semiconductor constituting the TFT is irradiated with at least a part of light whose wavelength is longer than a predetermined wavelength among the light emitted by the light emitting element.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: September 20, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yoshinori Tateishi, Masato Ofuji, Hideya Kumomi, Ryo Hayashi
  • Patent number: 9006866
    Abstract: A semiconductor device and a method for fabricating the same are disclosed, which can prevent migration of copper (Cu) ion when forming a Through Silicon Via (TSV). The semiconductor device includes a through silicon via (TSV) formed to pass through a semiconductor substrate; an oxide film located at a lower sidewall of the TSV; and a first prevention film formed to cover an upper portion of the TSV, an upper sidewall of the TSV, and an upper surface of the oxide film.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: April 14, 2015
    Assignee: SK Hynix Inc.
    Inventor: Dong Ryeol Lee
  • Patent number: 8993435
    Abstract: In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor and a carbon-source gas including carbon as precursors. The carbon-source gas is free from carbon dioxide (CO2). The precursor is selected from the group consisting essentially of 1-methylsilane (1MS), 2-methylsilane (2MS), 3-methylsilane (3MS), 4-methylsilane (4MS), and combinations thereof.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Chen Wang, Po-Cheng Shih, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
  • Patent number: 8975749
    Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8962473
    Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Shiang Kuo, Ken-Yu Chang, Ya-Lien Lee, Hung-Wen Su
  • Patent number: 8941239
    Abstract: A copper interconnect structure in a semiconductor device including an opening formed in a dielectric layer of the semiconductor device, the opening having sidewalls and a bottom. A first barrier layer is conformally deposited on the sidewalls and the bottom of the opening. A first seed layer is conformally deposited on the first barrier layer. A second barrier layer is conformally deposited on the first seed layer. A second seed layer is conformally deposited on the second barrier layer and a conductive plug is deposited in the opening of the dielectric layer.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shau-Lin Shue, Hsiang-Huan Lee, Ching-Fu Yeh
  • Patent number: 8916871
    Abstract: An embodiment of a semiconductor device includes a gallium nitride (GaN) substrate having a first surface and a second surface. The second surface is substantially opposite the first surface, at least one device layer is coupled to the first surface, and a backside metal is coupled to the second surface. A top metal stack is coupled to the at least one device layer. The top metal stack includes a contact metal coupled to a surface of the at least one device layer, a protection layer coupled to the contact metal, a diffusion barrier coupled to the protection layer, and a pad metal coupled to the diffusion barrier. The semiconductor device is configured to conduct electricity between the top metal stack and the backside metal.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: December 23, 2014
    Assignee: Avogy, Inc.
    Inventors: Brian Joel Alvarez, Donald R. Disney, Hui Nie, Patrick James Lazlo Hyland
  • Patent number: 8866313
    Abstract: A substrate includes a die-bonding zone and a glue spreading pattern. The die-bonding zone is set to bond a die. The glue spreading pattern is placed in the die-bonding zone and includes a containing space. The die is placed on the glue spreading pattern, an area of a bottom of the die is greater than an area of an opening of the glue spreading pattern, the containing room of the glue spreading pattern is filled with a glue, and the die is bonded to the substrate by means of the glue.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 21, 2014
    Assignee: Unistars Corporation
    Inventors: Tien-Hao Huang, Hsin-Hsie Lee, Yi-Chun Wu, Shang-Yi Wu
  • Patent number: 8841770
    Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Geraud J. M. Dubois, Daniel C. Edelstein, Takeshi Nogami, Daniel P. Sanders
  • Patent number: 8841769
    Abstract: A semiconductor device includes a first insulating layer on a substrate; a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate; a first barrier metal layer disposed on a sidewall and at a bottom of the first contact hole and a first metal plug disposed on the first barrier metal layer and in the first contact hole. A recess region is between the first insulating layer and the first metal plug. A gap-fill layer fills the recess region; and a second insulating layer is on the gap-fill layer. A second contact hole passes through the second insulating layer and exposes the upper surface of the first metal plug. A second barrier metal layer is on a sidewall and at the bottom of the second contact hole; and a second metal plug is on the second barrier metal layer.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: September 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangjine Park, Boun Yoon, Jeongnam Han, Kee-Sang Kwon, Wonsang Choi
  • Patent number: 8779569
    Abstract: A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating material 112 attached to side surfaces of the semiconductor chip 106, the first insulating material 110 and an island 102. The semiconductor chip 106 is fixed to the island 102 via the first insulating material 110 and the second insulating material 112. The first insulating material 110 ensures a high dielectric strength between the semiconductor chip 106 and the island 102. Though the second insulating material 112 having a modulus of elasticity greater than that of the first insulating material 110, the semiconductor chip 106 is firmly attached to the island 102.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: July 15, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Akihiro Kimura, Tsunemori Yamaguchi
  • Patent number: 8779589
    Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Harsono S. Simka, Daniel J. Zierath, Michael G. Haverty, Sadasivan Shankar
  • Patent number: 8753924
    Abstract: An article of manufacture includes a semiconductor die (110) having an integrated circuit (105) on a first side of the die (110), a diffusion barrier (125) on a second side of the die (110) opposite the first side, a mat of carbon nanotubes (112) rooted to the diffusion barrier (125), a die attach adhesive (115) forming an integral mass with the mat (112) of the carbon nanotubes, and a die pad (120) adhering to the die attach adhesive and (115) and the mat (112) of carbon nanotubes for at least some thermal transfer between the die (110) and the die pad (120) via the carbon nanotubes (112). Other articles, integrated circuit devices, structures, and processes of manufacture, and assembly processes are also disclosed.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: James Cooper Wainerdi, Luigi Colombo, John Paul Tellkamp, Robert Reid Doering
  • Patent number: 8735218
    Abstract: A method of producing an electronic module with at least one electronic component and one carrier. A structure is provided on the carrier so that the electronic component can take a desired target position relative to the structure. The structure is coated with a liquid meniscus suitable for receiving the electronic component. Multiple electronic components are provided at a delivery point for the electronic components. The carrier, with the structure, is moved nearby and opposite to the delivery point, where the delivery point delivers one of the electronic components without contact, while the structure on the carrier is moving near the delivery point, so that after a phase of free movement the electronic component at least partly touches the material, and the carrier, with the structure, is moved to a downstream processing point, while the electronic component aligns itself to the structure on the liquid meniscus.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: May 27, 2014
    Assignee: Muehlbauer AG
    Inventors: Michael Max Mueller, Helfried Zabel, Hans-Peter Monser
  • Patent number: 8685851
    Abstract: A manufacturing method of a MOS device with memory function is provided, which includes: providing a semiconductor substrate, a surface of the semiconductor substrate being covered by a first dielectric layer, a metal interconnect structure being formed in the first dielectric layer; forming a second dielectric layer overlying a surface of the first dielectric layer and the metal interconnect structure; forming an opening in the second dielectric layer, a bottom of the opening revealing the metal interconnect structure; forming an alloy layer at the bottom of the opening, material of the alloy layer containing copper and other metal; and performing a thermal treatment to the alloy layer and the metal interconnect structure to form, on the surface of the metal interconnect structure, a compound layer containing oxygen element. The compound layer containing oxygen element and the MOS device formed in the semiconductor substrate constitute a MOS device with memory function.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: April 1, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Chao Zhao, Wenwu Wang
  • Publication number: 20140084469
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool.
    Type: Application
    Filed: September 21, 2012
    Publication date: March 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming Han Lee, Tz-Jun Kuo, Chien-Hsin Ho, Hsiang-Huan Lee
  • Publication number: 20140084471
    Abstract: A structure includes a substrate, a low-k dielectric layer over the substrate, and a conductive barrier layer extending into the low-k dielectric layer. The conductive barrier layer includes a sidewall portion. A metal line in the low-k dielectric layer adjoins the conductive barrier layer. An organic buffer layer is between the sidewall portion of the conductive barrier layer and the low-k dielectric layer.
    Type: Application
    Filed: September 21, 2012
    Publication date: March 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Hsien Peng, Hsin-Yen Huang, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 8680599
    Abstract: To provide a more reliable semiconductor device including a lower-cost and more reliable capacitor and a method of manufacturing the same. This manufacturing method comprises the steps of: preparing a semiconductor substrate; and forming, over one of the major surfaces of the semiconductor substrate, a first metal electrode including an aluminum layer, a dielectric layer over the first metal electrode, and a second metal electrode over the dielectric layer. In the step of forming the first metal electrode, the aluminum layer is formed so that the surface thereof satisfies a relationship of Rmax<80 nm, Rms<10 nm, and Ra<9 nm. The step of forming the first metal electrode comprises the steps of: forming at least one first barrier layer; forming the aluminum layer over the first barrier layer; and recrystallizing a crystal constituting the aluminum layer.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: March 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Mitsuyama, Yasuhisa Fujii, Keiichi Yamada
  • Patent number: 8653664
    Abstract: A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: February 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su, Dian-Hau Chen, Yuh-Jier Mii
  • Publication number: 20140008799
    Abstract: A metal line fabricating method includes the following steps. Firstly, a substrate is provided. Then, a first barrier layer is formed over the substrate. A first dielectric layer is formed over the first barrier layer. An opening is formed in the first dielectric layer, wherein the opening runs through the first dielectric layer, so that the first barrier layer is exposed to the opening. A metal deposition process is performed to form a metal line over the exposed first barrier layer at a bottom of the opening. The first dielectric layer and the first barrier layer underlying the first dielectric layer are removed, but the metal line and the first barrier layer underlying the metal line are remained. Afterwards, a second dielectric layer is formed over the substrate which is provided with the metal line and the first barrier layer.
    Type: Application
    Filed: July 4, 2012
    Publication date: January 9, 2014
    Inventors: Chao-An Jong, Fu-Liang Yang
  • Publication number: 20140001635
    Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Li-Hsien Huang
  • Patent number: 8558381
    Abstract: The present teachings provides a semiconductor device which has a semiconductor substrate, and a lower electrode including a first layer in contact with a lower surface of the semiconductor substrate, a second layer in contact with a lower surface of the first layer, and a third layer stacked at a position farther from the semiconductor substrate than the second layer, wherein the first layer is an aluminum layer containing silicon, the second layer is a layer including silicon as a primary component, and the third layer is a solder joint layer.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: October 15, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Yoshihito Mizuno
  • Publication number: 20130249096
    Abstract: A method for forming a through silicon via (TSV) in a substrate comprising: depositing a seed layer in a TSV hole; and annealing the seed layer.
    Type: Application
    Filed: August 21, 2012
    Publication date: September 26, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mona Eissa, Nicholas S. Dellas, Brian E. Goodlin
  • Patent number: 8524512
    Abstract: Method for repairing copper diffusion barrier layers on a semiconductor solid substrate and repair kit for implementing this method. One subject of the present invention is a method for repairing a surface of a substrate coated with a discontinuous copper diffusion barrier layer of a titanium-based material. According to the invention, this method comprises: a) the contacting of the surface with a suspension containing copper or copper alloy nanoparticles for a time of between 1 s and 15 min; and b) the contacting of the thus treated surface with a liquid solution having a pH of between 8.5 and 12 and containing: at least one metal salt, at least one reducing agent, at least one stabilizer at a temperature of between 50° C. and 90° C., preferably between 60° C. and 80° C., for a time of between 30 s and 10 min, preferably between 1 min and 5 min, in order to thus form a metallic film having a thickness of at least 50 nanometers re-establishing the continuity of the copper diffusion barrier layer.
    Type: Grant
    Filed: September 7, 2009
    Date of Patent: September 3, 2013
    Assignee: Alchimer
    Inventor: Vincent Mevellec
  • Publication number: 20130161818
    Abstract: A three-dimensional (3-D) nonvolatile memory device includes channel layers protruding perpendicular to a surface of a substrate, interlayer insulating layers and conductive layer patterns alternately formed to surround each of the channel layers, a slit formed between the channel layers, the slit penetrating the interlayer insulating layers and the conductive layer patterns, and an etch-stop layer formed on the surface of the substrate at the bottom of the slit.
    Type: Application
    Filed: August 29, 2012
    Publication date: June 27, 2013
    Inventor: Joo Hee HAN
  • Patent number: 8461682
    Abstract: A method for use in the fabrication of integrated circuits includes providing a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The diffusion barrier layer is formed of RuSix, where x is in the range of about 0.01 to about 10. The barrier layer may be formed by depositing RuSix by chemical vapor deposition or the barrier layer may be formed by forming a layer of ruthenium relative to a silicon containing region and performing an anneal to form RuSix from the layer of ruthenium and the silicon containing region. Capacitor electrodes, interconnects or other structures may be formed with such a diffusion barrier layer.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: June 11, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Brian A. Vaartstra, Eugene P. Marsh
  • Publication number: 20130134494
    Abstract: A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.
    Type: Application
    Filed: August 17, 2012
    Publication date: May 30, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Won HONG, Hei-Seung KIM, Kyoung-hee NAM, In-sun PARK, Jong-Myeong LEE
  • Patent number: 8441112
    Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. The first and second terminals are formed by using electrodes of the first and second layer portions. The layered chip package is manufactured by fabricating a layered substructure by stacking two substructures each of which includes an array of a plurality of preliminary layer portions, and then cutting the layered substructure. The layered substructure includes a plurality of preliminary wires that are disposed between two adjacent pre-separation main bodies and are to become the plurality of wires.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: May 14, 2013
    Assignees: Headway Technologies, Inc., Sae Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Hiroshi Ikejima, Atsushi Iijima
  • Publication number: 20130082341
    Abstract: It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.
    Type: Application
    Filed: August 16, 2012
    Publication date: April 4, 2013
    Applicant: SONY CORPORATION
    Inventors: Kan SHIMIZU, Keishi INOUE
  • Publication number: 20130082385
    Abstract: A semiconductor die includes a substrate including a topside including circuit elements configured to provide a circuit function. The die includes at least one multi-layer structure including a first material having a first CTE, a second material including a metal having a second CTE, wherein the second CTE is higher than the first CTE. A coefficient of thermal expansion (CTE) graded layer includes at least a dielectric portion that is between the first material and the second material having a first side facing the first material and a second side facing the second material. The CTE graded layer includes a non-constant composition profile across its thickness that provides a graded CTE which increases in CTE from the first side to the second side. The multi-layer structure can be a through-substrate-vias (TSV) that extends through the thickness of the substrate.
    Type: Application
    Filed: October 3, 2011
    Publication date: April 4, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: BRIAN K. KIRKPATRICK, RAJESH TIWARI
  • Publication number: 20130075905
    Abstract: A semiconductor device includes a substrate and a through via penetrating the substrate. The through via has a protruding portion at a first end thereof extending out from a first surface of the substrate and a second end of the via contacting an interconnection line proximate a second, opposite, end of the substrate. A wetting layer is positioned between the via and the substrate and extends over the protruding portion of the via. The wetting layer includes a material selected to improve an adhesive strength between the wetting layer and a solder ball contacting the wetting layer extending over the protruding portion of the via when a solder ball is coupled to the wetting layer.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 28, 2013
    Inventors: Ju-il Choi, Jeong-Woo Park, Jeonggi Jin, Hyungseok Kim
  • Publication number: 20130049201
    Abstract: A power module includes a substrate having a surface on which a plurality of wiring patterns are formed, a semiconductor device mounted on the substrate and electrically connected to a part of the plurality of wiring patterns, and a terminal portion with a lead electrically connected to the other part of the plurality of wiring patterns, and is configured that the lead of the terminal portion is formed by laminating a plurality of metal members which contain a material substantially the same as or softer than the material for forming the other part of wiring patterns, and the material of the plurality of metal members, which is the same as or softer than the material for forming the other part of wiring patterns is electrically connected to the other part of wiring patterns through ultrasonic bonding.
    Type: Application
    Filed: June 29, 2012
    Publication date: February 28, 2013
    Applicant: Hitachi, Ltd.
    Inventors: Isamu YOSHIDA, Michiaki Hiyoshi, Takehide Yokozuka, Akihiro Muramoto
  • Patent number: 8384221
    Abstract: A semiconductor device includes a substrate, and a semiconductor thin film bonded to the substrate, wherein the semiconductor thin film includes a plurality of discrete operating regions and an element isolating region which isolates the plurality of discrete operating regions, and the element isolating region is etched to a shallower depth than a thickness of the semiconductor thin film, and is a thinner region than the plurality of discrete operating regions.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: February 26, 2013
    Assignee: Oki Data Corporation
    Inventors: Takahito Suzuki, Hiroyuki Fujiwara
  • Patent number: 8368218
    Abstract: An adhesive flexible barrier film comprises a substrate and a barrier layer disposed on the substrate. The barrier layer is formed from a barrier composition comprising an organosilicon compound. The adhesive flexible barrier film also comprises an adhesive layer disposed on the barrier layer and formed from an adhesive composition. A method of forming the adhesive flexible barrier film comprises the steps of disposing the barrier composition on the substrate to form the barrier layer, disposing the adhesive composition on the barrier layer to form the adhesive layer, and curing the barrier layer and the adhesive layer. The adhesive flexible barrier film may be utilized in organic electronic devices.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: February 5, 2013
    Assignee: Dow Corning Corporation
    Inventors: John Donald Blizzard, William Kenneth Weidner
  • Publication number: 20120280394
    Abstract: A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. Then, a SEG film is grown to form an active region whose area is increased. As a result, a current driving power of a transistor located at a cell region and peripheral circuit regions is improved.
    Type: Application
    Filed: July 17, 2012
    Publication date: November 8, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Young Bog KIM
  • Patent number: 8159069
    Abstract: A metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is formed on the semiconductor substrate having the lower metal line, and a metal line forming region exposing at least a portion of the lower metal line is defined in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and includes a WNx layer, a W—N—B ternary layer, and a Ti—N—B ternary layer. A wetting layer is formed on the diffusion barrier and is made of one of a Ti layer or a TiN layer. An upper metal line is formed on the wetting layer to fill the metal line forming region of the insulation layer.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: April 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Baek Mann Kim, Seung Jin Yeom, Dong Ha Jung, Jeong Tae Kim
  • Publication number: 20120049369
    Abstract: To provide a more reliable semiconductor device including a lower-cost and more reliable capacitor and a method of manufacturing the same. This manufacturing method comprises the steps of: preparing a semiconductor substrate; and forming, over one of the major surfaces of the semiconductor substrate, a first metal electrode including an aluminum layer, a dielectric layer over the first metal electrode, and a second metal electrode over the dielectric layer. In the step of forming the first metal electrode, the aluminum layer is formed so that the surface thereof satisfies a relationship of Rmax<80 nm, Rms<10 nm, and Ra<9 nm. The step of forming the first metal electrode comprises the steps of: forming at least one first barrier layer; forming the aluminum layer over the first barrier layer; and recrystallizing a crystal constituting the aluminum layer.
    Type: Application
    Filed: August 10, 2011
    Publication date: March 1, 2012
    Inventors: Hiroshi MITSUYAMA, Yasuhisa Fujii, Keiichi Yamada
  • Publication number: 20120043659
    Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.
    Type: Application
    Filed: November 1, 2011
    Publication date: February 23, 2012
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Jing Hui LI, Wu Ping LIU, Lawrence A. CLEVENGER
  • Publication number: 20120038050
    Abstract: A sputtering target consists of high purity Nb of which Ta content is 3000 ppm or less and oxygen content is 200 ppm or less. Dispersion of the Ta content in all the sputtering target is within ±30% as a whole target. Dispersion of the oxygen content is within ±80% as a whole target. According to such sputtering target, an interconnection film of low resistivity can be realized. In addition, each grain of Nb in the sputtering target has a grain diameter in the range of 0.1 to 10 times an average grain diameter and ratios of grain sizes of adjacent grains are in the range of 0.1 to 10. According to such sputtering target, giant dust can be largely suppressed from occurring. The sputtering target is suitable for forming a Nb film as liner material of an Al interconnection.
    Type: Application
    Filed: October 25, 2011
    Publication date: February 16, 2012
    Inventors: Koichi WATANABE, Yasuo Kohsaka, Takashi Watanabe, Takashi Ishigami, Yukinobu Suzuki, Naomi Fujioka
  • Patent number: 8106512
    Abstract: The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: January 31, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiang-Huan Lee, Ming Han Lee, Ming-Shih Yeh, Chen-Hua Yu, Shau-Lin Shue
  • Patent number: 7964967
    Abstract: A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: June 21, 2011
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Richard J. Rassel, Edmund J. Sprogis
  • Patent number: 7944053
    Abstract: A first insulating film is formed on a semiconductor substrate. A first interconnection is formed in a trench formed in the first insulating film. A first barrier film is formed between the first interconnection and first insulating film. A second insulating film is formed on the upper surface of the first interconnection, and in a first hollow portion between the side surface of the first barrier film and the first insulating film. The second insulating film is formed from the upper surface of the first interconnection to a depth higher than the bottom surface of the first interconnection. The first hollow portion is formed below the bottom surface of the second insulating film.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: May 17, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takamasa Usui, Tadayoshi Watanabe
  • Patent number: 7928570
    Abstract: An interconnect structure is disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the dielectric barrier layer; a via extending between the inter-level dielectric layer, the dielectric barrier layer, and the first metal layer, the via including a second liner layer and a second metal layer thereover; and a diffusion barrier layer located between the second liner layer and the first metal layer, wherein a portion of the diffusion barrier layer is located under the dielectric barrier layer.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, David V. Horak, Takeshi Nogami, Chih-Chao Yang
  • Publication number: 20110057330
    Abstract: It is desired to provide an electronic device which can be easily taken out of a mold after a resin sealing processing. The electronic device include: an insulating layer; a wiring formed on the insulating layer; and a solder resist layer formed to cover the insulation layer and the wiring and including particles of an elastomer. An asperity is formed on a surface of the solder resist layer.
    Type: Application
    Filed: September 7, 2010
    Publication date: March 10, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshitaka USHIYAMA
  • Patent number: 7902682
    Abstract: There is provided a UV energy curable tape comprising an adhesive material including a UV energy curable oligomer, a UV energy initiator, and a material which emits optical light when the tape composition is substantially fully cured. A semiconductor chip made using the tape is also provided.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Timothy C. Krywanczyk, Donald W. Brouillette, Steven A. Martel, Matthew R. Whalen
  • Patent number: 7875976
    Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a silicide layer provided on the semiconductor substrate, a dielectric layer provided on the semiconductor substrate, a contact layer provided on the silicide layer, a metal layer provided in the dielectric layer and electrically connected to the silicide layer via the contact layer, a diffusion barrier layer provided between the dielectric layer and the metal layer, wherein the contact layer includes a first metal element provided in the metal layer, a second metal element provided in the diffusion barrier layer and at least one of a third metal provided in the silicide layer and Si element.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: January 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Takamasa Usui, Kazuya Ohuchi
  • Patent number: 7872351
    Abstract: A multi-layered metal line of a semiconductor device includes a semiconductor substrate; a lower metal line formed on the semiconductor substrate and recessed on a surface thereof; an insulation layer formed on the semiconductor substrate including the lower metal line and having a damascene pattern for exposing a recessed portion of the lower metal line and for delimiting an upper metal line forming region; a glue layer formed on a surface of the recessed portion of the lower metal line; a first diffusion barrier formed on the glue layer to fill the recessed portion of the lower metal line; a second diffusion barrier formed on the glue layer and the first diffusion barrier; a third diffusion barrier formed on the second diffusion barrier and a surface of the damascene pattern; and an upper metal line formed on the third diffusion barrier to fill the damascene pattern.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: January 18, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jeong Tae Kim, Baek Mann Kim, Soo Hyun Kim, Young Jin Lee, Dong Ha Jung
  • Patent number: 7867917
    Abstract: By providing a barrier layer stack including a thin SiCN layer for enhanced adhesion, a silicon nitride layer for confining a copper-based metal region (thereby also effectively avoiding any diffusion of oxygen and moisture into the copper region), and a SiCN layer, the total relative permittivity may still be maintained at a low level, since the thickness of the first SiCN layer and of the silicon nitride layer may be moderately thin, while the relatively thick silicon carbide nitride layer provides the required high etch selectivity during a subsequent patterning process of the low-k dielectric layer.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: January 11, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joerg Hohage, Matthias Lehr, Volker Kahlert
  • Patent number: 7855456
    Abstract: A metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is formed on the semiconductor substrate having the lower metal line, and a metal line forming region exposing at least a portion of the lower metal line is defined in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and includes a WNx layer, a W—N—B ternary layer, and a Ti—N—B ternary layer. A wetting layer is formed on the diffusion barrier and is made of one of a Ti layer or a TiN layer. An upper metal line is formed on the wetting layer to fill the metal line forming region of the insulation layer.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: December 21, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Baek Mann Kim, Seung Jin Yeom, Dong Ha Jung, Jeong Tae Kim
  • Patent number: 7820490
    Abstract: An LTCC (low temperature cofired ceramic) structure which has conductors to which leads are to be bonded for connection to external circuitry. The conductors include additives to promote adhesion to the ceramic layer. The presence of these additives degrade bonding performance. For better bondability of the leads, a pure conductor metal layer, devoid of the additives is placed on the conductors in areas where leads are to be bonded. This pure conductor metal layer may be cofired with the stack of ceramic layers or may be post fired after stack firing.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: October 26, 2010
    Assignee: Northrop Grumman Corporation
    Inventors: Cynthia W. Berry, Alex E. Bailey