Abstract: Method of forming a semiconductor device which includes the steps of obtaining a semiconductor substrate having a logic region and an STI region; sequentially depositing layers of high K material, metal gate, first silicon and hardmask; removing the hardmask and first silicon layers from the logic region; applying a second layer of silicon on the semiconductor substrate such that the logic region has layers of high K material, metal gate and second silicon and the STI region has layers of high K material, metal gate, first silicon, hardmask and second silicon. There may also be a second hardmask layer between the metal gate layer and the first silicon layer in the STI region. There may also be a hardmask layer between the metal gate layer and the first silicon layer in the STI region but no hardmask layer between the first and second layers of silicon in the STI region.

Abstract: A semiconductor structure including a substrate, at least one power MOSFET, a floating diode or a body diode, and at least one Schottky diode is provided. The substrate has a first area, a second area and a third area. The second area is between the first area and the third area. The at least one power MOSFET is in the first area. The floating diode or the body diode is in the second area. The at least one Schottky diode is in the third area. Further, the contact plugs of the power MOSFET and the Schottky diode include tungsten and are electronically connected to each other.

Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

Abstract: A printed circuit board including a conductor portion, an insulating layer formed over the conductor portion, a thin-film capacitor formed over the insulating layer and including a first electrode, a second electrode and a high-dielectric layer interposed between the first electrode and the second electrode, and a via-hole conductor structure formed through the second electrode and insulating layer and electrically connecting the second electrode and the conductor portion. The via-hole conductor structure has a first portion in the second electrode and a second portion in the insulating layer. The first portion of the via-hole conductor structure has a truncated-cone shape tapering toward the conductor portion.

Abstract: A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first insulating layer and a polysilicon pattern on the active region of the peripheral circuit region, forming a second insulating layer, a charge storage layer, and a third insulating layer on the active region of the cell region, farming a conductive layer on the semiconductor substrate, and patterning the conductive layer to form conductive patterns on the third insulating layer of the cell region, the polysilicon pattern of the active region of peripheral circuit region, and the semiconductor substrate of the resistor region, respectively.

Abstract: An object is to provide a semiconductor device in which characteristics of a driver circuit portion are improved while the aperture ratio of a pixel portion is increased. Alternatively, it is an object to provide a semiconductor device with low power consumption or to provide a semiconductor device in which the threshold voltage of a transistor can be controlled. The semiconductor device includes a substrate having an insulating surface, a pixel portion provided over the substrate, and at least some of driver circuits for driving the pixel portion. A transistor included in the pixel portion and a transistor included in the driver circuit are top-gate bottom-contact transistors. Electrodes and a semiconductor layer of the transistor in the pixel portion have light-transmitting properties. The resistance of electrodes in the driver circuit is lower than the electrodes included in the transistor in the pixel portion.

Abstract: A method of manufacturing a semiconductor device, includes: forming a gate insulating film on a semiconductor substrate; forming a first metal film on the gate insulating film; forming a second metal film on the first metal film; and patterning a stacked film of the first and second metal films such that the stacked film is left in a gate electrode formation region and a resistive element formation region. The method further includes: removing the second metal film in the resistive element formation region with protecting a contact hole formation region. The method further includes: forming an interlayer insulating film so as to cover the stacked film; and removing the interlayer insulating film formed in the contact hole formation region to form a contact hole leading to the second metal film.

Abstract: A method for forming a semiconductor device is disclosed. The method for forming the semiconductor device includes forming a pad insulating layer on a semiconductor substrate, forming a recess by etching the pad insulating layer and the semiconductor substrate, forming a buried gate buried in the recess, forming an insulating layer for defining a bit line contact hole over the buried gate and the pad insulating layer, forming a bit line over a bit line contact for filling the bit line contact hole, and forming a storage electrode contact hole by etching the insulating layer and the pad insulating layer to expose the semiconductor substrate. As a result, the method increases the size of an overlap area between a storage electrode contact and an active region without an additional mask process, resulting in a reduction in cell resistance.

Abstract: A thin film transistor (TFT) substrate includes first and second TFTs on the same substrate. The first TFT has a feature that a lower conductive layer or a bottom gate electrode layer is provided between the substrate and a first insulating layer while an upper conductive layer or a top gate electrode layer is disposed on a second insulating layer formed on a semiconductor layer which is formed on the first insulating layer. The first conductive layer has first and second areas such that the first area overlaps with the first conductive layer without overlapping with the semiconductor layer while the second area overlaps with the semiconductor layer, and the first area is larger than the second area while the second insulating layer is thinner than the first insulating layer. The second TFT has the same configuration as the first TFT except that the gate electrode layer is eliminated.

Abstract: A method for fabricating a semiconductor apparatus including a buried gate removes factors deteriorating the operational reliability of the semiconductor device such as the electrical connection between a contact and a word line, and increases a processing margin when forming the contact disposed on a source/drain region. The method includes forming a recess in a semiconductor substrate, forming a gate in a lower portion of the recess, forming a first insulation layer over the gate, growing silicon over the first insulation layer in the recess, and depositing a second insulation layer over the semiconductor substrate and in the remaining portion of the recess.

Abstract: A trench is formed so as to reach a p?-type epitaxial layer from an upper surface of a source region. A gate electrode is formed so as to bury the trench. Each of body contact trenches is formed away from the gate electrode. A body contact region is formed at the bottom of the body contact trench. An n-type semiconductor region that is a feature of the present invention is formed in a layer below each body contact region. The impurity concentration of the n-type semiconductor region is higher than a channel forming area and lower than the body contact region.

Abstract: A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes: a) Fabricate numerous trench MOSFETs on a wafer. b) Add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer. c) Add numerous ESD protection modules atop the Si3N4 isolation layer. d) Remove those portions of the Si3N4 isolation layer that are not beneath the ESD protection modules. In one embodiment, hydrofluoric acid is used as a first etchant for patterning the LTO while hot phosphoric acid is used as a second etchant for removing portions of the Si3N4 isolation layer.

Abstract: In one embodiment, a semiconductor structure comprises a multi-portioned guard ring that includes a first portion and a second portion formed in a region of semiconductor material. A conductive contact layer forms a first Schottky barrier with the region of semiconductor material. The conductive contact layer overlaps the second portion and forms a second Schottky barrier that has an opposite polarity to the first Schottky barrier. The conductive contact layer does not overlap the first portion, which forms a pn junction with the region of semiconductor material.

Abstract: An aperture ratio of a semiconductor device is improved. A driver circuit and a pixel are provided over one substrate, and a first thin film transistor in the driver circuit and a second thin film transistor in the pixel each include a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide semiconductor layer over the gate insulating layer, source and drain electrode layers over the oxide semiconductor layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer, and the source and drain electrode layers. The gate electrode layer, the gate insulating layer, the oxide semiconductor layer, the source and drain electrode layers, and the oxide insulating layer of the second thin film transistor each have a light-transmitting property.

Abstract: An ID tag capable of communicating data wirelessly, the size of which is reduced, and where the size of an IC chip is reduced, a limited area of the chip is effectively used, current consumption is reduced, and communication distance is prevented from decreasing. The ID tag of the invention includes an IC chip having an integrated circuit, a resonance capacitor portion and a storage capacitor portion, and an antenna formed over the IC chip so as to overlap at least partially with an insulating film interposed therebetween. The antenna, the insulating film and wirings or semiconductor films forming the integrated circuit are stacked, and one or both of capacitors in the resonance capacitor portion and the storage capacitor portion are formed by this stacked structure.

Abstract: A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and second doping zone are formed on the surface of the first insulating layer for the definition of a channel zone, wherein there is formed at the surface of the channel zone a gate dielectric and thereon a control electrode for the realization of a field effect transistor. In the active semiconductor region, a diode doping zone is formed on the surface of the first insulating layer, which zone realizes a measuring diode via a diode side area with the first or second doping zone and is delimited by the second insulating layer at its further side areas.

Abstract: A DC-DC buck converter in multi-die package is proposed having an output inductor, a low-side Schottky diode and a high-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a first die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the first die pad via an insulating die bond. Alternatively, the first die pad is grounded. The vertical MOSFET is a top drain N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the first die pad. The PRC is attached atop the first die pad via a conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration.

Abstract: Effective area of a capacitor is to be increased while suppressing increase in number of manufacturing steps. In a semiconductor device, a silicon substrate includes a plurality of first recessed portions having a first depth from the main surface thereof, a second recessed portion provided in a region other than the first recessed portion and having a second depth from the main surface, and a third recessed portion provided in at least one of the plurality of first recessed portions and having a third depth from the bottom portion of the first recessed portion. The second recessed portion and the third recessed portion have the same depth, and a decoupling condenser is provided so as to fill the at least one of the first recessed portion and the third recessed portion provided therein, and an isolation insulating layer is provided so as to fill the remaining first recessed portions, and the second recessed portion is filled with a gate electrode.

Abstract: A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region.

Abstract: A multimodal integrated circuit (IC) is provided, comprising, first (74) and second (76) semiconductor (SC) devices, and first (78) and second (80) integrated passive devices (IPDs) coupled, respectively, to the first (74) and second (76) SC devices, wherein the first IPD (78) overlies the second SC device (76) and the second IPD (80) overlies the first SC device (74) chosen such that the underlying SC device (74, 76) is not active at the same time as its overlying IPD (80, 78). By placing the IPDs (78, 80) over the SC devices (76, 74) a compact IC layout is obtained. Since the overlying IPD (78, 80) and underlying SC (76, 74) are not active at the same time, undesirable cross-talk (68, 69) between the IPDs (78, 80) and the SC devices (76, 74) is avoided. This arrangement applies to any IC having multiple signal paths (RF1, RF2) where the IPDs (78, 80) of a first path (RF1, RF2) may be placed over the SC devices (76, 74) of a second path (RF2, RF1) not active at the same time.

Abstract: The present invention relates to a highly integrated semiconductor device in which a capacitor is formed between adjacent gate patterns by using a nanotube process. A semiconductor memory device according to an example embodiment of the present invention includes a capacitor formed on a first side of a source/drain region positioned between gate patterns of adjacent cell transistors; a plate layer connected to an upper portion of the capacitor, the plate layer being formed in a direction intersecting the gate pattern; and a bit line connected to a second side of the source/drain region of the cell transistor, the bit line being formed in the direction intersecting the gate pattern.

Abstract: A semiconductor device may include a semiconductor chip including a signal terminating resistor coupled between a signal input pad and a first ground voltage pad, a semiconductor package including a signal input terminal and a first ground voltage terminal, the signal input terminal being electrically coupled to the signal input pad of the semiconductor chip and the first ground voltage terminal being electrically coupled to the first ground voltage pad of the semiconductor chip, a capacitor and a resistor that are coupled between the signal input terminal and the first ground voltage terminal, and a first inductor realized by coupling the signal input terminal and the signal input pad.

Abstract: An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers (112, 113) in a first well region (104) that is disposed between anode and cathode regions (105, 106) in response to one or more bias voltages (G1, G2) that are close to Vdd in order to reduce leakage current and capacitance during normal operation (non-ESD) condition. During an electrostatic discharge event, the bias voltages can be removed (e.g., decoupled or set to 0V) to eliminate the inversion layers, thereby forming a semiconductor resistor for shunting the ESD current.

Abstract: In a lateral-type power MOSFET, high breakdown voltage is achieved with suppressing to increase a cell pitch, and a feedback capacity and an ON resistance are decreased. An n? type silicon region having a high resistance to be a region of maintaining a breakdown voltage is vertically provided with respect to a main surface of an n+ type silicon substrate, and the n? type silicon region having the high resistance is connected to the n+ type silicon substrate. Also, a conductive substance is filled through an insulating substance inside a trench formed to reach the n+ type silicon substrate from the main surface of the n+ type silicon substrate so as to contact with the n? type silicon region having the high resistance, and the conductive substance is electrically connected to a source electrode.

Abstract: A semiconductor memory device has an asymmetric buried gate structure with a stepped top surface and a method for fabricating the same. The method for fabricating the semiconductor memory device includes: etching a predetermined region of a semiconductor substrate to form an isolation layer defining an active region; forming a recess within the active region; forming a metal layer filling the recess; asymmetrically etching the metal layer to form an asymmetric gate having a stepped top surface at a predetermined portion of the recess; and forming a capping oxide layer filling a remaining portion of the recess where the asymmetric gate is not formed, thereby obtaining an asymmetric buried gate including the asymmetric gate and the capping oxide layer.

Abstract: Electrical device structures constructed in an isolated p-well that is wholly contained within a core n-well. Methods of forming electrical devices within an isolated p-well that is wholly contained within a core n-well using a baseline CMOS process flow.

Abstract: A semiconductor device is provided with Zener diodes which are formed by using a polysilicon gate layer(s) so as to be connected to each other in parallel. Parallel-connected rectangular Zener diodes are formed outside an active region or parallel-connected striped Zener diodes are formed inside the active region. The Zener diodes increase the ESD capability of the semiconductor device.

Abstract: The semiconductor device according to the present invention includes an SJMOSFET having a plurality of base regions formed at an interval from each other and an SBD (Schottky Barrier Diode) having a Schottky junction between the plurality of base regions. The SBD is provided in parallel with a parasitic diode of the SJMOSFET.

Abstract: An IGBT is disclosed which separated into two groups (first and second IGBT portioZenerns). First and second Zener diodes each composed of series-connected Zener diode parts are disposed so as to correspond to the groups respectively. Each of the first and second Zener diodes has an anode side connected to a corresponding one of first and second polysilicon gate wirings, and a cathode side connected to an emitter electrode. Temperature dependence of a forward voltage drop of each of first and second Zener diodes is used for reducing a gate voltage of a group rising in temperature to throttle a current flowing in the group and reduce the temperature of the group to thereby attain equalization of the temperature distribution in a surface of a chip. In this manner, it is possible to provide an MOS type semiconductor device in which equalization of the temperature distribution in a surface of a chip or among chips can be attained.

Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.

Abstract: To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1?x):x where 0.01?x?0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a transistor including: a source, a drain and a gate; first and second plugs on the source and the drain; a third plug on the gate to have a top face higher than that of the first plug; an interlayer insulating film covering the transistor and the first to the third plugs; a ferroelectric capacitor on the interlayer insulating film, one electrode thereof being connected to the first plug; a barrier film covering surfaces of the ferroelectric capacitor and the interlayer insulating film to prevent a substance affecting the ferroelectric capacitor from entering therethrough; and fourth and fifth plugs disposed on the second and the third plugs and connected thereto through connection holes formed in the barrier film.

Abstract: A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.

Abstract: A structure of power semiconductor device integrated with clamp diodes sharing same gate metal pad is disclosed. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon.

Abstract: Disclosed are a power semiconductor device and a method for manufacturing the same. The power semiconductor device has a PIP capacitor and an LDMOS transistor, the LDMOS transistor having second and third gate electrodes separate from a first gate electrode, which may be formed in the process of forming the upper electrode of the PIP capacitor, so it is possible to realize an LDMOS having a higher breakdown voltage and lower Ron and Rsp without additional processing. A drain voltage, which may be different from a voltage applied to the first gate electrode, may be applied to the third gate electrode, so it is possible to realize an LDMOS having a high breakdown voltage and low Ron and Rsp.

Abstract: Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.

Abstract: Methods of manufacturing resistors, methods of manufacturing semiconductor devices, and structures thereof are disclosed. In one embodiment, a method of fabricating a resistor includes forming a transistor material stack over a workpiece and patterning the transistor material stack, forming a gate of a transistor in a first region of the workpiece and leaving a portion of the transistor material stack in a second region of the workpiece. A top portion of the transistor material stack is removed in the second region, and a top portion of the workpiece is removed in the first region proximate the gate of the transistor, forming recessed regions in the workpiece in the first region. A semiconductive material is formed in the recessed regions of the workpiece in the first region and over a portion of the transistor material stack in the second region, forming a resistor in the second region.

Abstract: A capacitor electrode is composed of an SrRuO3 film including first and second surfaces opposed to each other. The capacitor electrode contains a 10 atom % or less trivalent element in a region ranging from a position a predetermined distance away from the first surface in the thickness direction thereof up to the second surface side.

Abstract: Disclosed is an electrostatic discharge protection device that overcomes problems of an LVTNR device by serially connecting a diode to the LVTNR device and coupling a gate of a MOSFET structure thereto. The electrostatic discharge protection device of the present invention includes a diode comprising N well/P+ diffusion regions; a resistor connected in parallel to the diode; a MOS transistor having a drain connected to the diode and the resistor and constituting a cathode along with a source and a gate; and at least one diode connected in series to the cathode.

Abstract: A device is provided that in one embodiment includes a substrate having a first region and a second region, in which a semiconductor device is present on a dielectric layer in the first region of the substrate and a resistive structure is present on the dielectric layer in the second region of the substrate. The semiconductor device may include a semiconductor body and a gate structure, in which the gate structure includes a gate dielectric material present on the semiconducting body and a metal gate material present on the gate dielectric material. The resistive structure may include semiconductor material having a lower surface is in direct contact with the dielectric layer in the second region of the substrate. The resistive structure may be a semiconductor containing fuse or a polysilicon resistor. A method of forming the aforementioned device is also provided.

Abstract: An array substrate and method for manufacturing the same is provided, wherein a data line is composed of first and second segments connected by a contact pad. First and second insulation layers are disposed between the first segment of the data line and a shielding electrode. In addition, the first insulation layer is disposed between the second segment of the data line and a gate line in their overlapping area. Accordingly, the coupling effect between the conductive layers can be reduced. For example, the RC delay problem due to parasitic capacitance between the shielding electrode and the data line is solved. As a result of the design of the two insulator layers between the first segment of the data line and the shielding electrode, the shorting between the conductive layers can also be simultaneously solved and the product yield can be increased.

Abstract: Test structures for in-line voltage contrast detection of PFET silicide encroachment defects are disclosed. Embodiments of the present invention provide for improved PFET test structures for detecting encroachment defects using VC imaging techniques. The test structures use body contacts, and the PFET components (source, drain, body, and gate) are either grounded, or floating, depending on the configuration. Some embodiments of the present invention also enable the use of positive mode conditions with PFET test structures, which provides for improved contrast in the VC images, improving the effectiveness of the defect detection achieved with VC imaging.

Abstract: A semiconductor device includes: an isolation region formed in a semiconductor substrate; active regions surrounded by the isolation region and including p-type and n-type regions, respectively; an NMOS transistor formed in the active region including the p-type region and including an n-type gate electrode; a PMOS transistor formed in the active region including the n-type region and including a p-type gate electrode; and a p-type resistor formed on the isolation region. The p-type resistor has an internal stress greater than that of the p-type gate electrode.

Abstract: The present invention discloses an integrated junction field effect transistor (JFET) and Schottky diode, comprising a depletion mode JFET which includes a source, a drain and a gate, wherein the drain is not provided with an ohmic contact such that it forms a Schottky diode.

Abstract: Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p? substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p? substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse.

Abstract: The present invention discloses an integrated PMOS transistor and Schottky diode, comprising a PMOS transistor which includes a gate, a source, a drain and a channel region between the source and drain, wherein the source, drain and channel region are formed in a substrate, and a parasitic diode is formed between the drain and the channel region; and a Schottky diode formed in the substrate and connected in reverse series with the parasitic diode, the Schottky diode having one end connected with the parasitic diode and the other end connected with the source.

Abstract: In a semiconductor device in which a diode and a high electron mobility transistor are incorporated in the same semiconductor chip, a compound semiconductor layer of the high electron mobility transistor is formed on a main surface (first main surface) of a semiconductor substrate of the diode, and an anode electrode of the diode is electrically connected to an anode region via a conductive material embedded in a via hole (hole) reaching a p+ region which is the anode region of the main surface of the semiconductor substrate from a main surface of the compound semiconductor layer.

Abstract: A structure of power semiconductor device integrated with clamp diodes having separated gate metal pad is disclosed. The separated gate metal pads are wire bonded together on the gate lead frame. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon.

Abstract: A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.

Abstract: A semiconductor substrate with an active element formed in the semiconductor substrate, an element isolating insulating film formed around the active element and semiconductor substrate, a polysilicon resistance element formed over the element isolating insulating film with terminal areas and a resistance portion formed between the terminal areas, the polysilicon resistance element having plural reticulations which have the same shapes and the same size.