Abstract: A semiconductor structure includes a substrate having a doped silicon substrate, a buried oxide layer, and a silicon device layer. A capacitor having an inner electrode and a node dielectric layer is formed in the substrate. The inner electrode and the node dielectric layer extend into the doped silicon substrate. A select transistor is disposed in the silicon device layer. An embedded contact is disposed atop the capacitor to electrically couple a doped region of the select transistor with the inner electrode. A first dielectric layer is disposed around the select transistor. A second dielectric layer is deposited on the first dielectric layer. A contact plug is formed in the second dielectric layer and the first dielectric layer and is in direct contact with the embedded contact. A memory stack with a MTJ element is disposed on the contact plug.

Abstract: A semiconductor structure for a memory device includes a substrate including a memory cell region and a peripheral circuit region defined thereon, at least an active region formed in the peripheral circuit region, a buried gate structure formed in the active region in the peripheral circuit region, a conductive line structure formed on the buried gate structure, and at least a bit line contact plug formed in the memory cell region.

Abstract: A semiconductor structure for a memory device includes a substrate including a memory cell region and a peripheral circuit region defined thereon, at least an active region formed in the peripheral circuit region, a buried gate structure formed in the active region in the peripheral circuit region, a conductive line structure formed on the buried gate structure, and at least a bit line contact plug formed in the memory cell region.

Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

Abstract: A method of fabricating an LFCC device includes forming a first trench in a substrate that extends vertically from an upper surface to a depth within the substrate, the first trench having first sidewalls, a first bottom, and a pattern formed on the first sidewalls near the first bottom of the trench, and forming an oxide layer on the first sidewalls and first bottom of the first trench that leaves a second trench located within the first trench and is separated from the first trench by the oxide layer. The second trench has second sidewalls that are substantially vertical without showing the pattern and a second bottom that is substantially flat. The pattern compensates for the difference in oxidation rates between the bottom of the first trench and the first sidewalls. The LFCC structure includes a first trench with the pattern.

Abstract: Semiconductor devices, capacitors, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a capacitor includes forming a first material over a workpiece, and patterning the first material, forming a first capacitor plate in a first region of the workpiece and forming a first element in a second region of the workpiece. A second material is formed over the workpiece and over the patterned first material. The second material is patterned, forming a capacitor dielectric and a second capacitor plate in the first region of the workpiece over the first capacitor plate and forming a second element in a third region of the workpiece.

Abstract: Provided are a method of fabricating a semiconductor device having different kinds of capacitors, and a semiconductor device formed using the same. In a fabrication process, after preparing a substrate including a storage capacitor region and a higher voltage resistance capacitor region, a lower electrode layer may be formed on the storage capacitor region and the higher voltage resistance capacitor region. A first dielectric film may be formed on the lower electrode layer, and the first dielectric film of the storage capacitor region may be selectively removed to expose the lower electrode layer of the storage capacitor region. After forming a second dielectric film on the first dielectric film and the exposed lower electrode layer of the storage capacitor region, an upper electrode layer may be formed on the second dielectric film.

Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.

Abstract: A manufacturing method of DRAM is provided. A substrate having a deep trench is provided, and then a deep trench capacitor including a bottom electrode, an upper electrode and a capacitor dielectric layer is formed in the deep trench. A part of the upper electrode of the deep trench capacitor is removed to form a first trench. A buried strap is formed in the substrate on one side of the upper electrode. An isolation structure is formed in the first trench to define an active region. A part of the substrate adjacent to the isolation structure is removed to form a second trench. A first heavily doped region is formed on the bottom of the second trench, and the first heavily doped region is electrically connected to the buried strap. A dielectric layer is formed on the bottom of the second trench.

Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.

Abstract: A thin film transistor substrate includes: a substrate; a thin film transistor and a capacitor formed on the substrate; and a protective film for protecting an electrode on a back surface side of the capacitor when an electrode on a front surface side of the capacitor is cut by irradiation with laser light, the protective film being disposed at such a position as to enclose a corner part of the electrode on the front surface side between the electrode on the front surface side and the electrode on the back surface side of the capacitor.

Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

Abstract: An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the semiconducting substrate, and a capacitor (130) at least partially embedded in the semiconducting substrate. The capacitor includes a first electrode (131) and a second electrode (132) that are electrically isolated from each other by a first electrically insulating material (133). The first electrode is electrically connected to the semiconducting substrate and the second electrode is electrically connected to the source/drain region of the transistor.

Abstract: A semiconductor device including a metallic compound Hfx1Moy1Nz1 as an electrode. The work function of the electrode can be modulated by doping the metallic compound with dopants including nitrogen, silicon or germanium. The metallic compound of the present invention is applicable to PMOS, NMOS, CMOS transistors and capacitors.

Abstract: A trench structure and a memory cell using the trench structure. The trench structure includes: a substrate; a trench having contiguous upper, middle and lower regions, the trench extending from a top surface of said substrate into said substrate; the upper region of the trench having a vertical sidewall profile; and the middle region of the trench having a tapered sidewall profile.

Abstract: According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; an element isolation region formed in the semiconductor substrate so as to extend in a first direction; a gate electrode formed in the semiconductor substrate so as to extend in a second direction crossing the first direction and to penetrate through the element isolation region; a gate insulating film interposed between the gate electrode and the semiconductor substrate; an interlayer dielectric film formed on the gate electrode; a ferroelectric capacitor including: first and second electrodes disposed on the interlayer dielectric film and a ferroelectric between the first and second electrodes; and first and second semiconductor pillars being in contact respectively with the first and second electrodes.

Abstract: An array substrate includes a substrate, a thin film transistor, a passivation layer, a pixel electrode and a storage capacitor. The thin film transistor includes a gate electrode formed on the substrate, a gate insulation layer formed on the substrate having the gate electrode, a semiconductor layer formed on the gate insulation layer and a data electrode formed on the semiconductor layer. The passivation layer is formed on the substrate having the data electrode and the pixel electrode is electrically connected to the data electrode through a contact hole formed through the passivation layer. The storage capacitor includes a first storage capacitor electrode that is spaced apart from the gate electrode of the thin film transistor and a second storage capacitor electrode that is formed on the gate insulation and including a same material as the pixel electrode.

Abstract: A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.

Abstract: To provide a semiconductor integrated circuit device capable of increasing a capacitor capacitance. A semiconductor integrated circuit device according to an embodiment of the present invention includes: a circuit element formed on a semiconductor substrate; and capacitors formed on the semiconductor substrate and including: a lower capacitance electrode formed of a lower wiring line connected to the circuit element; a capacitance insulating film covering an upper surface and a side surface of the lower wiring line; and an upper capacitance electrode formed on the capacitance insulating film, the lower capacitance electrode including at least one of a power supply line and a ground line formed of the lower wiring line.

Abstract: A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.

Abstract: The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET), and a design structure including the semiconductor device embodied in a machine readable medium. The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap.

Abstract: A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semiconductor region wrapping around the first portion, but electrically insulated from the first portion by a capacitor dielectric layer; (d) a second doped semiconductor region wrapping around the second portion, but electrically insulated from the second portion by a collar dielectric layer. The second portion is on top of and electrically coupled to the first portion, and the third portion is on top of and electrically coupled to the second portion. The collar dielectric layer is in direct physical contact with the capacitor dielectric layer. When going away from the collar dielectric layer, a doping concentration of the second doped semiconductor region decreases.

Abstract: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.

Abstract: A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.

Abstract: A nonvolatile memory cell that can be mounted in a CMOS manufacturing process, and is capable of implementing high level of programming, reading and erasing ability. The memory cell is configured by a MOS transistor including two N-type first impurity diffusion layers formed separately on a P-type semiconductor substrate, and a first gate electrode formed above a first cannel region sandwiched by both diffusion layers through a first gate insulation film, a first capacitor comprising P-type second impurity diffusion layers formed on a well, and a second gate electrode formed above the diffusion layer through a second gate insulation film, and a second capacitor comprising the well adjacent to the second impurity diffusion layer, and a third gate electrode formed above the well through a third gate insulation film, wherein a different voltage can be applied to each of the capacitors.

Abstract: The present invention provides a raw material carbon composition that is converted to a carbon material for an electrode in an electric double layer capacitor that can develop a high level of electrostatic capacity with good reproducibility without producing any synthetic pitch. The raw material carbon composition is converted to a carbon material for an electrode in an electric double layer capacitor upon activation treatment and is characterized in that, when the raw material carbon composition is carbonized in an inert gas atmosphere at a temperature of 1000 to 1500° C., the true relative density (RD) and the total hydrogen content (TH %) in the carbonized material obtained after the burning satisfy the following formula (1): RD=?0.75TH %+intercept??(1) wherein the intercept is 2.160 or greater.

Abstract: A method for fabricating a semiconductor memory device. A pair of neighboring trench capacitors is formed in a substrate. An insulating layer having a pair of connecting structures therein is formed on the substrate, in which the pair of connecting structures is electrically connected to the pair of neighboring trench capacitors. An active layer is formed on the insulating layer between the pair of connecting structures so as to cover the pair of connecting structures. A pair of gate structures is formed on the active layer to electrically connect to the pair of trench capacitors. A semiconductor memory device is also disclosed.

Abstract: A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.

Abstract: The layout density of the through electrodes in the horizontal plane of the substrate is enhanced. Through holes 103 extending through the silicon substrate 101 is provided. An insulating film 105 is buried within the through hole 103. A plurality of columnar through plugs 107 are provided in the insulating film 105.

Abstract: The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.

Abstract: The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon.

Abstract: The present invention provides a method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, in particular for a semiconductor memory cell with a planar selection transistor that is provided in the substrate and connected via the buried contact The invention likewise provides a corresponding trench capacitor.

Abstract: A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.

Abstract: A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used to define the required pattern on the photoresist. The hard mask layer and the STI are used as an etching mask to etch a plurality of deep trenches. Then diffusion regions, capacitor dielectric layer, and polysilicon filled to form the capacitor bottom electrode are sequentially formed to complete the forming for trench capacitors. After removing the hard mask layer and performing a logic process, the memory cells are completed.

Abstract: A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.

Abstract: A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the first and second plane capacitors share a common ploysilicon floating gate configured to retain charge as a result of programming the memory cell. The memory cell is configured to be erased by tunneling between the first doped region and the common ploysilicon floating gate without causing junction breakdown within the memory cell. The first and second doped regions are formed in the substrate before forming the common ploysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within an operating voltage range.

Abstract: A semiconductor device has a capacitive element including a first conductive film formed on the bottom and wall surfaces of an opening formed in an insulating film on a substrate, a dielectric film formed on the first conductive film, and a second conductive film formed on the dielectric film. The dielectric film of the capacitive element is crystallized. The first and second conductive films are made of a polycrystal of an oxide, a nitride or an oxynitride of a noble metal.

Abstract: A storage cell field has a plurality of storage cells formed in a substrate of a first doping type, said storage cells comprising a trench capacitor arranged in said substrate and a selection transistor associated with said trench capacitor and provided with a transistor body which is arranged in said substrate. An implantation having an increased dopant concentration of the first doping type is provided in said substrate. This implantation prevents space-charge zones, which are located at the trench capacitors and which are caused in predetermined storage states of said trench capacitors, from constricting a substrate region, which is available for applying a predetermined potential to the transistor bodies, in such a way that said predetermined potential cannot be applied.