Dynamic Random Access Memory, Dram, Structure (epo) Patents (Class 257/E27.084)
  • Patent number: 10497709
    Abstract: A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: December 3, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mikiko Mori, Ryota Suzuki, Tatsuya Kato, Wataru Sakamoto, Fumie Kikushima
  • Patent number: 10417947
    Abstract: Fail-operational display devices and methods for controlling such fail-operational display devices are disclosed. More specifically, emissive displays having independently addressable (controllable) light emitting elements fitted with redundant control circuits may be utilized. In the event of a failure, one set of redundant control circuits may be disabled while another set of redundant control circuits may be enabled to keep the display device fail-operational.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: September 17, 2019
    Assignee: Rockwell Collins, Inc.
    Inventors: Donald E. Mosier, Tracy J. Barnidge, Jon J. Freesmeier
  • Patent number: 10396082
    Abstract: Some embodiments include a memory cell having a transistor with a channel region between a first source/drain region and a second source/drain region. A controlled-conductivity region is adjacent the first source/drain region. The controlled-conductivity region has a low-conductivity mode and a high-conductivity mode. The high-conductivity mode has a conductivity at least 106 greater than a conductivity of the low-conductivity mode. The channel region includes a first material having a first bandgap, and the controlled-conductivity region includes a second material having a second bandgap which is greater than the first bandgap. A charge-storage device is electrically coupled to the first source/drain region through the controlled-conductivity region. A bitline is electrically coupled to the second source/drain region.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Kamal M. Karda
  • Patent number: 10186311
    Abstract: A semiconductor device includes a memory cell, a buffer circuit, a switch, first to p-th switch circuits, and first to p-th capacitors (p is an integer of 2 or more). The first to p-th switch circuits each include first to third terminals. The memory cell is electrically connected to a first electrode of the first capacitor and an input terminal of the buffer circuit through the switch. A second electrode of an i-th capacitor is electrically connected to a first terminal of an i-th switch circuit and a first electrode of an (i+1)th capacitor (i is an integer of 1 to (p?1)). A second electrode of the p-th capacitor is electrically connected to a first terminal of the p-th switch circuit. An output terminal of the buffer circuit is electrically connected to a second terminal of each of the first to p-th switch circuits. A third terminal of each of the first to p-th switch circuits is electrically connected to a wiring supplying a low-level potential.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: January 22, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yutaka Shionoiri
  • Patent number: 10050524
    Abstract: A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 14, 2018
    Assignee: STMicroelectronics International N.V.
    Inventor: Vikas Rana
  • Patent number: 9917146
    Abstract: An integrated capacitor includes a substrate with a first main surface area and an opposing second main surface area. A capacitor structure with a dielectric layer is integrated in the first main surface area. A compensation structure with a compensation layer is integrated in the second main surface area. The ratio between a surface enlargement of the second main surface area effected by the compensation structure corresponds to at least 30% of the surface enlargement of the first main surface area effected by the capacitor structure.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 13, 2018
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Anton Bauer, Tobias Erlbacher, Holger Schwarzmann
  • Patent number: 9735781
    Abstract: An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 15, 2017
    Assignee: SYPHERMEDIA INTERNATIONAL, INC.
    Inventors: Ronald P. Cocchi, Lap Wai Chow, James P. Baukus, Bryan J. Wang
  • Patent number: 9543306
    Abstract: A sub word line driver of a semiconductor memory device including a sub word line driver is disclosed. The sub word line driver of a semiconductor memory device comprising: a semiconductor substrate including an active region extended in a first direction; a plurality of gate electrodes extended in a second direction perpendicular to the active region; first and second metal contacts formed over the active region between the gate electrodes; a plurality of metal pads coupled to the first metal contacts; and a plurality of metal signal lines coupled to the second metal contacts, extended in the second direction, and bent at specific parts adjacent to the metal pads.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: January 10, 2017
    Assignee: SK Hynix Inc.
    Inventor: Han Kyu Lee
  • Patent number: 9455151
    Abstract: An integrated capacitor includes a substrate with a first main surface area and an opposing second main surface area. A capacitor structure with a dielectric layer is integrated in the first main surface area. A compensation structure with a compensation layer is integrated in the second main surface area. The ratio between a surface enlargement of the second main surface area effected by the compensation structure corresponds to at least 30% of the surface enlargement of the first main surface area effected by the capacitor structure.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: September 27, 2016
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Anton Bauer, Tobias Erlbacher, Holger Schwarzmann
  • Patent number: 9041086
    Abstract: A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Larson Lindholm, David Hwang
  • Patent number: 9041154
    Abstract: A semiconductor memory device includes a substrate having thereon a memory array region and a periphery circuit region. A first dielectric layer covers the memory array region and the periphery circuit region on the substrate. A second dielectric layer covers the memory array region and the periphery circuit region on the first dielectric layer. At least a capacitor structure is provided in the memory array region. The capacitor structure includes an electrode material layer embedded in the second dielectric layer. The semiconductor memory device further includes a contact structure comprising the electrode material layer.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 26, 2015
    Assignee: NANYA TECHNOLOGY CORP.
    Inventors: Chien-An Yu, Chih-Huang Wu
  • Patent number: 9029863
    Abstract: A variation in electrical characteristics, such as a negative shift of the threshold voltage or an increase in S value, of a fin-type transistor including an oxide semiconductor material is prevented. An oxide semiconductor film is sandwiched between a plurality of gate electrodes with an insulating film provided between the oxide semiconductor film and each of the gate electrodes. Specifically, a first gate insulating film is provided to cover a first gate electrode, an oxide semiconductor film is provided to be in contact with the first gate insulating film and extend beyond the first gate electrode, a second gate insulating film is provided to cover at least the oxide semiconductor film, and a second gate electrode is provided to be in contact with part of the second gate insulating film and extend beyond the first gate electrode.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: May 12, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsuo Isobe
  • Patent number: 9012969
    Abstract: A device isolation film has a first height in a first area and a second height higher than the first height in a second area. The first area includes a first end of a dummy memory transistor facing a memory string and a part of a device isolation film adjacent thereof. The second area includes a second end of the dummy memory transistor facing a select transistor and a part of the device isolation film adjacent thereof.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kamigaichi
  • Patent number: 8994086
    Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroko Abe, Yukie Nemoto, Ryoji Nomura, Mikio Yukawa
  • Patent number: 8975680
    Abstract: A highly integrated gain cell-type semiconductor memory is provided. A first insulator, a read bit line, a second insulator, a third insulator, a first semiconductor film, first conductive layers, and the like are formed. A projecting insulator is formed thereover. Then, second semiconductor films and a second gate insulating film are formed to cover the projecting insulator. After that, a conductive film is formed and subjected to anisotropic etching, so that write word lines are formed on side surfaces of the projecting insulator. A third contact plug for connection to a write bit line is formed over a top of the projecting insulator. With such a structure, the area of the memory cell can be 4 F2 at a minimum.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: March 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 8969935
    Abstract: Disclosed herein is a device that includes a semiconductor substrate having a first area, a plurality of cell transistors arranged on the first area of the semiconductor substrate, and a plurality of cell capacitors each coupled to an associated one of the cell transistors, the cell capacitors being provided so as to overlap with one another on the first area.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: March 3, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Hiroyuki Uchiyama
  • Patent number: 8970039
    Abstract: A semiconductor device includes a plurality of electrode structures perpendicularly extending on a substrate, and at least one support unit extending between the plurality of electrode structures. The support unit includes at least one support layer including a noncrystalline metal oxide contacting a part of the plurality of electrode structures. Related devices and fabrication methods are also discussed.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-jin Kuh, Sang-ryol Yang, Soon-wook Jung, Young-sub You, Byung-hong Chung, Han-mei Choi, Jong-sung Lim
  • Patent number: 8952435
    Abstract: A method for forming a memory cell transistor is disclosed which includes providing a substrate, forming a trench structure in the substrate, depositing a conductive substance on the surface of the substrate to form a conductive member inside the trench structure, forming one or more dielectric layers on the surface of the substrate, forming one or more first conductive layers on top of the dielectric layers, and etching the first conductive layers and the dielectric layers to form a hole structure extending through the first conductive and the dielectric layers, reaching to the substrate surface. The formed memory cell transistor thus comprises a hole structure which is formed from the surface of the top first conductive layer, extending downwards through the first conductive layers and the dielectric layers, and reaching the substrate surface. One or more second conductive layers may be formed on top of the first conductive layers, with the second conductive layer material filling the hole structure.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: February 10, 2015
    Assignee: Hermes Microvision, Inc.
    Inventor: Hong Xiao
  • Patent number: 8952436
    Abstract: A DRAM memory device includes at least one memory cell including a transistor having a first electrode, a second electrode and a control electrode. A capacitor is coupled to the first electrode. At least one electrically conductive line is coupled to the second electrode and at least one second electrically conductive line is coupled to the control electrode. The electrically conductive lines are located between the transistor and the capacitor. The capacitor can be provided above a fifth metal level.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: February 10, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sébastien Cremer, Frédérìc Lalanne, Marc Vernet
  • Patent number: 8946019
    Abstract: In a semiconductor device, capacitors may be formed so as to be in direct contact with a transistor by using a shared transistor region, such as a drain region or a source region of closely spaced transistors, as one capacitor electrode, while the other capacitor electrode is provided in the form of a buried electrode in the dielectric material of the contact level. To this end, dielectric material may be deposited so as to reliably form a void, wherein, at any appropriate manufacturing stage, a capacitor dielectric material may be provided so as to separate the capacitor electrodes.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: February 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dmytro Chumakov, Tino Hertzsch
  • Patent number: 8946855
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes adjacent storage node contact plugs having different heights, and lower-electrode bowing profiles having different heights, such that a spatial margin between the lower electrodes is assured and a bridge fail is prevented, resulting in improved device operation characteristics. The semiconductor device includes a first storage node contact plug and a second storage node contact plug formed over a semiconductor substrate, wherein the second storage node contact plug is arranged at a height different from that of the first storage node contact plug, and a lower electrode formed over the first storage node contact plug and the second storage node contact plug.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: February 3, 2015
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Ho Sohn
  • Patent number: 8947932
    Abstract: Provided is a one-transistor (1T) floating-body DRAM cell device including a substrate; a gate stack which is formed on the substrate; a control electrode which is disposed on the substrate and of which some or entire portion is surrounded by the gate stack; a semiconductor layer which is formed on the gate stack; a source and a drain which are formed in the surface of the semiconductor layer and of which lower surfaces are not in contact with the gate stack; a gate insulating layer which is formed on the semiconductor layer; and a gate electrode which is formed on the gate insulating layer, wherein the remaining portion of the semiconductor layer excluding the source and the drain is configured as a floating body. The miniaturization characteristic and performance of a MOS-based DRAM cell device can be improved, and a memory capacity can be increased.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: February 3, 2015
    Assignee: SNU R&DB Foundation
    Inventor: Jong-Ho Lee
  • Patent number: 8937345
    Abstract: An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Kangguo Cheng, Michael Sperling, Geng Wang
  • Patent number: 8937344
    Abstract: The semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein, semiconductor memory elements formed over the semiconductor substrate in the cell region, an interlayer insulating layer formed over the semiconductor substrate in the peripheral circuit region, first conductive layers substantially vertically passing through the interlayer insulating layer, and arranged in a matrix, and second conductive layers coupling the first conductive layers in rows or columns, each pair of the second conductive layers and the first conductive layers coupled to the each pair of the second conductive layers, respectively, forming electrodes of a capacitor.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: January 20, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jung Ryul Ahn, Jum Soo Kim
  • Patent number: 8928062
    Abstract: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately formed on a surface portion of the substrate, buried insulating films formed in portions of the substrate that lie under the source and drain regions and each having a dielectric constant smaller than that of the substrate, a tunnel insulating film formed on a channel region formed between the source and drain regions, a charge storage layer formed of a dielectric body on the tunnel insulating film, a block insulating film formed on the charge storage layer, and a control gate electrode formed on the block insulating film.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoki Yasuda
  • Patent number: 8921171
    Abstract: A method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on the substrate; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming a first work function adjustment layer on the oxygen scavenging element layer; etching the first work function adjustment layer above the nMOSFET area; forming a second work function adjustment layer on the surface of the substrate; metal layer depositing and annealing to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: December 30, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Hong Yang, Xueli Ma, Wenwu Wang, Kai Han, Xiaolei Wang, Huaxiang Yin, Jiang Yan
  • Patent number: 8921906
    Abstract: Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: December 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Byron Neville Burgess, John K. Zahurak
  • Patent number: 8916470
    Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: December 23, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Durga Panda, Jaydip Guha, Robert Kerr
  • Patent number: 8912588
    Abstract: A semiconductor memory device includes a bit line, an active region formed in a semiconductor substrate, a plug formed on the active region and connecting the bit line to the active region, a memory cell which includes a first gate insulating film on the active region, a charge storage layer on the first gate insulating film, a first insulating film on the charge storage layer, and a control gate electrode on the first insulating film, a select transistor formed between the plug and the memory cell on the active region and including a second gate insulating film on the active region, a first electrode layer on the second gate insulating film, a second insulating film on the first electrode layer, and a second electrode layer on the second insulating film, and a wiring formed above the active region between the plug and the second electrode layer of the select transistor.
    Type: Grant
    Filed: September 2, 2013
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazushige Kanda
  • Patent number: 8901629
    Abstract: A semiconductor device includes a semiconductor substrate divided into a cell region and a peripheral circuit region defined in a first direction, wherein the peripheral circuit region is divided into a first region and a second region defined in a second direction substantially orthogonal to the first direction; gate lines formed over the semiconductor substrate in the cell region and arranged in the second direction; and a capacitor including lower electrodes over the semiconductor substrate, a dielectric layer and an upper electrode, wherein the lower electrodes in the first and second regions, separated from each other in the first direction and coupled to each other in the first region, the dielectric layer is formed along surfaces of the lower electrodes in the second region, and the upper electrode is formed over the dielectric layer.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: December 2, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jung Ryul Ahn, Yun Kyoung Lee
  • Patent number: 8890225
    Abstract: The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chuan Liao, Chien-Kao Yang, Ying-Kit Tsui, Shih-Hsien Chen, Liang-Tai Kuo, Chun-Yao Ko
  • Patent number: 8872247
    Abstract: Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Shigeki Tomishima
  • Patent number: 8866204
    Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: October 21, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Qing Liu, Junli Wang
  • Patent number: 8860108
    Abstract: It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Patent number: 8860112
    Abstract: A method of forming a strap connection structure for connecting an embedded dynamic random access memory (eDRAM) to a transistor comprises forming a buried oxide layer in a substrate, the buried oxide layer defining an SOI layer on a surface of the substrate; forming a deep trench through the SOI layer and the buried oxide layer in the substrate; forming a storage capacitor in a lower portion of the deep trench; conformally doping a sidewall of an upper portion of the deep trench; depositing a metal strap on the conformally doped sidewall and on the storage capacitor; forming at least one fin in the SOI layer, the fin being in communication with the metal strap; forming a spacer over the metal strap and over a juncture of the fin and the metal strap; and depositing a passive word line on the spacer.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Effendi Leobandung, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8853760
    Abstract: An integrated circuit may include an element placed in an insulating region adjacent to a copper metallization level and including a barrier layer in contact with a metallization level. The element may be electrically connected to and spaced away from a copper line of the metallization level by way of an electrical link passing through the barrier layer and including an electrically conductive material different from copper in direct contact with the copper line.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sébastien Cremer, Sébastien Gaillard
  • Patent number: 8841195
    Abstract: A method for fabricating a semiconductor device includes forming a first dielectric structure over a second region of a substrate to expose a first region of the substrate, forming a barrier layer over an entire surface including the first dielectric structure, forming a second dielectric structure over the barrier layer in the first region, forming first open parts and second open parts in the first region and the second region, respectively, by etching the second dielectric structure, the barrier layer and the first dielectric structure, forming first conductive patterns filled in the first open parts and second conductive patterns filled in the second open parts, forming a protective layer to cover the second region, and removing the second dielectric structure.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: September 23, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jun-Hyeub Sun, Sang-Oh Lee, Su-Young Kim
  • Patent number: 8841717
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first groove; and a plurality of first pillars over the substrate. The plurality of first pillars is disposed beside the first groove. A first insulator is disposed in the first groove. A bit contact is disposed in the first groove and over the first insulator. The bit contact is coupled to side surfaces of the plurality of first pillars.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: September 23, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Noriaki Mikasa
  • Patent number: 8822996
    Abstract: A semiconductor device including a memory cell is provided. The memory cell comprises a transistor, a memory element and a capacitor. One of first and second electrodes of the memory element and one of first and second electrodes of the capacitor are formed by a same metal film. The metal film functioning as the one of first and second electrodes of the memory element and the one of first and second electrodes of the capacitor is overlapped with a film functioning as the other of first and second electrodes of the capacitor.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Abe, Yasuyuki Takahashi
  • Patent number: 8817534
    Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: August 26, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Serguei Okhonin, Viktor I Koldiaev, Mikhail Nagoga, Yogesh Luthra
  • Patent number: 8803213
    Abstract: Some embodiments include apparatus and methods having a base; a memory cell including a body, a source, and a drain; and an insulation material electrically isolating the body, the source, and the drain from the base, where the body is configured to store information. The base and the body include bulk semiconductor material. Additional apparatus and methods are described.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Paul Grisham
  • Patent number: 8792284
    Abstract: In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: July 29, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Ohnuki
  • Patent number: 8779432
    Abstract: A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo
  • Patent number: 8779488
    Abstract: In the semiconductor memory device, one of a source and a drain of a first transistor is connected to one of a source and a drain of a second transistor, a gate of the first transistor is connected to one of a source and a drain of a third transistor and one of a pair of capacitor electrodes included in a capacitor, the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor are connected to a bit line, the other of the pair of capacitor electrodes included in the capacitor is connected to a common wiring, and the common wiring is grounded (GND). The common wiring has a net shape when seen from the above, and the third transistor is provided in a mesh formed by the common wiring.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Toshihiko Saito
  • Patent number: 8779487
    Abstract: A Dynamic Random Access Memory (DRAM) device can include a semiconductor substrate that includes an active region including a source region therein. A gate line can cross the active region and a first contact plug can be on the active region adjacent to the gate line and can be connected to the source region. A conductive layer can be on the first contact plug to expose a portion of the first contact plug and a capacitor storage node electrode can be on the conductive layer.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-il Kim, Makoto Yoshida
  • Patent number: 8772849
    Abstract: A semiconductor memory device includes a semiconductor film; a first gate insulating film covering the semiconductor film; a first gate electrode provided over the semiconductor film with the first gate insulating film interposed therebetween; a first conductive film which is provided over the first gate insulating film; an insulating film which is provided over the first gate insulating film, exposes top surfaces of the first gate electrode and the first conductive film, and has a groove portion between the first gate electrode and the first conductive film; an oxide semiconductor film which is provided over the insulating film and is in contact with the first gate electrode, the first conductive film, and the groove portion; a second gate insulating film covering the oxide semiconductor film; and a second gate electrode provided over the oxide semiconductor film and the groove portion with the second gate insulating film interposed therebetween.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kosei Noda
  • Patent number: 8772105
    Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: July 8, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae Su Jang, Min Soo Yoo
  • Patent number: 8772848
    Abstract: A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: John K. Zahurak, Sanh D. Tang, Lars P. Heineck, Martin C. Roberts, Wolfgang Mueller, Haitao Liu
  • Patent number: 8766399
    Abstract: To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: July 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Maeda, Yasushi Sekine, Tetsuya Watanabe
  • Patent number: 8766342
    Abstract: Methods and an apparatus are described for an integrated circuit within which an electroless Cu plated layer having an oxygen content is formed on the top of a seed layer comprising Cu and Mn. The integrated circuit is then exposed to a sufficient high temperature to cause the self-formation of a MnSiOx barrier layer.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: July 1, 2014
    Assignee: Intel Corporation
    Inventor: Rohan N. Akolkar