Abstract: A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.

Abstract: In a semiconductor device, a polysilicon layer of a lower electrode contact plug is removed by a strip process such that the deposition area of a dielectric film is increased and capacitance of a capacitor is assured. A method for manufacturing the semiconductor device is also disclosed.

Abstract: A method for manufacturing a semiconductor device is disclosed. In the method for manufacturing the semiconductor device, a capacitor structure is modified to ensure capacitance of the capacitor, and the height of the capacitor is reduced to prevent defects such as a leaning capacitor or a poor bridge from being generated, such that the fabrication process of semiconductor devices is simplified and therefore the semiconductor devices can be stably manufactured.

Abstract: A stacked semiconductor package provides an enhanced data storage capacity along with an improved data processing speed. The stacked semiconductor package includes a substrate having chip selection pads and a connection pad; a semiconductor chip module including a plurality of semiconductor chips including data bonding pads, a chip selection bonding pad, and data redistributions electrically connected with the data bonding pads and a data through electrode passing through the data bonding pad and connected with the data redistribution, the semiconductor chips being stacked so as to expose the chip selection bonding pad; and a conductive wire for connecting electrically the chip selection pad and the chip selection bonding pads.

Abstract: Embodiments according to the inventive concept can provide semiconductor devices including a substrate and a plurality of active pillars arranged in a matrix on the substrate. Each of the pillars includes a channel part that includes a channel dopant region disposed in a surface of the channel part. A gate electrode surrounds an outer surface of the channel part. The plurality of active pillars may be arranged in rows in a first direction and columns in a second direction crossing the first direction.

Abstract: A method for fabricating a capacitor in a semiconductor device includes forming an insulation layer over a substrate, forming a storage node contact plug passing through the insulation layer and coupled to the substrate, recessing the storage node contact plug to a certain depth to obtain a sloped profile, forming a barrier metal over the surface profile of the recessed storage node contact plug, forming a sacrificial layer over the substrate structure, etching the sacrificial layer to form an opening exposing the barrier metal, forming a bottom electrode over the surface profile of the opening, and removing the etched sacrificial layer.

Abstract: A semiconductor package 100 is constructed of a semiconductor chip 110, a sealing resin 106 for sealing this semiconductor chip 110, and wiring 105 formed inside the sealing resin 106. And, the wiring 105 is constructed of pattern wiring 105b connected to the semiconductor chip 110 and also formed so as to be exposed to a lower surface 106b of the sealing resin 106, and a post part 105a formed so as to extend in a thickness direction of the sealing resin 106, the post part in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to an upper surface 106a of the sealing resin 106.

Abstract: A semiconductor capacitor that includes a plurality of overlapping conductive layers and a field-effect transistor. The plurality of conductive layers include a first and second conductive layers that are spaced apart to creating a capacitance between the plurality of layers. In the semiconductor capacitor, the FET has a source, a drain and a gate. When the FET is in conduction mode, a capacitance is created between the gate and the conductive path in the semiconductor substrate between the source and the drain. The semiconductor capacitor's total capacitance is increased by coupling the drain and the source to the first conductive layer and coupling the gate to the second conductive layer.

Abstract: Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is formed within the recess. The sacrificial layer is removed to create a space to allow access to the sides of the structural layer. The structural layer is removed, creating an isolated lower electrode. The lower electrode can be covered with a capacitor dielectric and upper electrode to form a double-sided container capacitor.

Abstract: A method for forming double-sided capacitors for a semiconductor device includes forming a dielectric structure which supports capacitor bottom plates during wafer processing. The structure is particularly useful for supporting the bottom plates during removal of a base dielectric layer to expose the outside of the bottom plates to form a double-sided capacitor. The support structure further supports the bottom plates during formation of a cell dielectric layer, a capacitor top plate, and final supporting dielectric. An inventive structure is also described.

Abstract: Methods, devices, and systems for a memory cell are provided. One embodiment includes a memory cell with a storage node separated from a body region by a first dielectric, wherein the body region includes a channel separating a source and a drain region, and wherein a length of the storage node is less than a length of the channel. The embodiment further includes a memory cell with a gate separated from the storage node by a second dielectric, wherein a length of the gate is greater than a length of the storage node.

Abstract: A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.

Abstract: In one embodiment, a method includes selectively depositing a collar material between a number of memory containers. The collar material along a side of a first memory container of the number of memory containers is in contact with the collar material along a side of a second memory container. An opening exists between the collar material along a corner of the memory container and the collar material along a corner of a third memory container.

Abstract: As an oxygen diffusion prevention layer, a multilayer film formed by a metal nitride and a noble metal element. As an interlayer insulation film on the oxygen diffusion prevention layer, a plasma CVD oxide film is used. Moreover, as an interlayer insulation film on a capacitor, an ozone TEOS film is used.

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).

Abstract: A semiconductor device may include a semiconductor substrate that includes first and second regions; first, second, and third insulating layers; a capacitor dielectric layer that includes first and second dielectric layers; a gate insulating layer formed on the first and second regions; a gate formed on the gate insulating layer of the second region; a first capacitor electrode formed on the capacitor dielectric layer; and junction regions formed in the semiconductor substrate on sides of the gate. The first and second regions may include first and second trenches, respectively. The third insulating layer may be formed on the second insulating layer, which may be formed on the first insulating layer, which may be formed on an inner surface of the second trench. The second dielectric layer may be formed on the first dielectric layer, which may be formed on an inner surface of the first trench.

Abstract: As an oxygen diffusion prevention layer, a multilayer film formed by a metal nitride and a noble metal element. As an interlayer insulation film on the oxygen diffusion prevention layer, a plasma CVD oxide film is used. Moreover, as an interlayer insulation film on a capacitor, an ozone TEOS film is used.

Abstract: Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.

Abstract: A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is greater within the capacitor electrode-forming material than is a second set of the openings. Conductive first capacitor electrode material is formed therein. A sacrificial retaining structure is formed elevationally over both the first capacitor electrode material and the capacitor electrode-forming material, leaving some of the capacitor electrode-forming material exposed. With the retaining structure in place, at least some of the capacitor electrode-forming material is etched from the substrate effective to expose outer sidewall surfaces of the first capacitor electrode material.

Abstract: A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used to define the required pattern on the photoresist. The hard mask layer and the STI are used as an etching mask to etch a plurality of deep trenches. Then diffusion regions, capacitor dielectric layer, and polysilicon filled to form the capacitor bottom electrode are sequentially formed to complete the forming for trench capacitors. After removing the hard mask layer and performing a logic process, the memory cells are completed.

Abstract: An array of multi-level non-volatile memory transistors features a transistor construction with a conductive polysilicon control gate having opposed sidewalls insulatively spaced just above the substrate. Conductive polysilicon spacers are separated from the opposed sidewalls by thin tunnel oxide. Source and drain implants are beneath or slightly outboard of the spacers. Insulative material is placed over the structure with a hole cut above the control gate for contact by a gate electrode connected to, or part of, a conductive word line. The array has auxiliary low voltage transistors which may be made at the same time as the formation of the memory transistors. The auxiliary transistors apply opposite phase clock pulses to source and drain electrodes of transistors in the array so that first one side of each memory transistor may be written to, or read, then the other side.

Abstract: A manufacturing method of a semiconductor device having a highly reliable capacitor, and the semiconductor device are provided.

Abstract: The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 ? (or alternatively comprising a thickness resulting from no more than 70 ALD cycles) is formed between conductively-doped silicon and a dielectric layer. The conductively-doped silicon can be n-type silicon and the dielectric layer can be a high-k dielectric material. The metal-containing material can be formed directly on the dielectric layer, and the conductively-doped silicon can be formed directly on the metal-containing material. The circuit device can be a capacitor construction or a transistor construction. If the circuit device is a transistor construction, such can be incorporated into a CMOS assembly. Various devices of the present invention can be incorporated into memory constructions, and can be incorporated into electronic systems.

Abstract: The present device relates to memory devices for storing electric charge having memory cells and transistors arranged spatially next to them, and relates in particular to memory devices having memory cells with a high capacitance. In the memory cells which form a memory device to which the invention relates, there is a substrate and at least one memory cell which is arranged on the substrate and includes a first electrode element, which is electrically connected to the substrate, an insulation layer, which has been applied to the first electrode element, and a second electrode element, which has been applied to the insulation layer and is electrically insulated from the first electrode element.