Abstract: Disclosed are systems, methods, and apparatus directed to the fabrication of vertical field effect transistors (VFETs) and VFETs with self-aligned wordlines. In one embodiment, the source and/or drain of the VFETs can include n-doped silicon. In one embodiment, the VFETs can include a channel that can be made of intrinsic silicon. In one embodiment, the source, drain, and/or channel can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam chemical vapor deposition (MOCVD), and/or atomic layer deposition (ALD), and the like. In one embodiment, an STI process can be used to fabricate one or more recesses, which can reach the drains of the VFETs. In one embodiment, the systems, methods, and apparatus can permit the self-alignment of one or more wordlines of the VFETs with the one or more fins, and/or gate metals and gate materials of the VFETs.

Abstract: A high-voltage metal-oxide-semiconductor field-effect transistor applied to a high-voltage range includes a substrate, an epitaxial layer, a plurality of first doped regions, a plurality of first trenches, a plurality of second trenches, a plurality of second doped regions, and a metal layer. The epitaxial layer is disposed on the substrate and used as a drain electrode. The plurality of first doped regions are disposed in the epitaxial layer. The plurality of first trenches are disposed on the plurality of doped regions in a spaced manner. Each of the first trenches has a first trench oxide layer and a first semiconductor layer which is connected to a source electrode. The plurality of second trenches are disposed between each of the first trenches in a spaced manner. Each of the second trenches has a second trench oxide layer and a second semiconductor layer which is connected to a gate electrode.

Abstract: Various methods and structures for fabricating a contact for a semiconductor FET or FinFET device. A semiconductor FET structure includes a substrate, a source/drain region layer and source/drain contact. First and second gate spacers are adjacent respective first and second opposing sides of the source/drain contact. The source/drain contact is disposed directly on and contacting the entire source/drain region layer, and at a vertical level thereabove, the source/drain contact being recessed to a limited horizontal area continuing vertically upwards from the vertical level. The limited horizontal area horizontally extending along less than a full horizontal length of a vertical sidewall of the first and second gate spacers, and less than fully covering the source/drain region layer. A method uses a reverse contact mask to form a shape of the source/drain contact into an inverted “T” shape.

Abstract: A semiconductor device includes a substrate including a plurality of active regions divided by a plurality of trenches, a plurality of tunnel insulating layer patterns formed over the active regions, a plurality of conductive film patterns formed over the tunnel insulating film patterns, a plurality of first isolation layers formed on sidewalls and bottom surfaces of the trenches, and a plurality of second isolation layers formed between the conductive film patterns.

Abstract: In one implementation, a method for fabricating a trench FET includes providing a semiconductor substrate including a drain region and a drift zone over the drain region, forming a plurality of depletion trenches over the drain region, each of the plurality of depletion trenches having a depletion trench dielectric and a depletion electrode, and forming a respective bordering gate trench alongside each of the plurality of depletion trenches, each bordering gate trench having a gate electrode and a gate dielectric.

Abstract: A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode.

Abstract: A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.

Abstract: According to one embodiment, a device includes a first fin structure having first to n-th semiconductor layers (n is a natural number equal to or more than 2) stacked in a first direction perpendicular to a surface of a semiconductor substrate, and extending in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory cells provided on surfaces of the first to n-th semiconductor layers in a third direction perpendicular to the first and second directions respectively, and first to n-th select transistors connected in series to the first to n-th memory cells respectively.

Abstract: Representative implementations of devices and techniques provide a termination arrangement for a transistor structure. The periphery of a transistor structure may include a recessed area having features arranged to improve performance of the transistor at or near breakdown.

Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

Abstract: A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor includes: a semiconductor substrate and a drain layer formed in the semiconductor substrate, in which the drain layer is first type heavily doped; an epitaxial layer formed on the drain layer, with an isolation region formed in the epitaxial layer; a buried layer formed in the epitaxial layer, in which the buried layer is second type lightly doped; a source formed in the buried layer, in which the source is second type heavily doped; a gate dielectric layer formed on the epitaxial layer, and a gate formed on the gate dielectric layer; and a source metal contact layer formed on the source, and a drain metal contact layer formed under the drain layer.

Abstract: A non-volatile memory device includes a substrate; a first conductive layer over the substrate, a second conductive layer over the first conductive layer, a stacked structure disposed over the second conductive layer, wherein the stacked structure includes a plurality of first inter-layer dielectric layers and a plurality of third conductive layers alternately stacked, a pair of first channels that penetrate the stacked structure and the second conductive layer, a second channel which is buried in the first conductive layer, covered by the second conductive layer, and coupled to lower ends of the pair of the first channels; and a memory layer formed along internal walls of the first and second channels.

Abstract: Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.

Abstract: Embodiments of the invention relate to field effect transistors. The field effect transistor includes a gate electrode for providing a gate field, a first electrode including a conductive material having a low carrier density and a low density of electronic states, a second electrode, and a semiconductor. Contact barrier modulation includes barrier height lowering of a Schottky contact between the first electrode and the semiconductor. In some embodiments of the invention, a vertical field effect transistor employs an electrode comprising a conductive material with a low density of states such that the transistors contact barrier modulation comprises barrier height lowering of the Schottky contact between the electrode with a low density of states and the adjacent semiconductor by a Fermi level shift.

Abstract: An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed.

Abstract: A vertical transistor comprises a semiconductor region, a pillar region formed on the semiconductor region, a gate insulating film formed so as to cover a side surface of the pillar region, a gate electrode formed on the gate insulating film, a first impurity diffusion region formed in an upper portion of the pillar region, and a second impurity diffusion region formed in the semiconductor region so as to surround the pillar region. The first impurity diffusion region is formed so as to be spaced from the side surface of the pillar region.

Abstract: DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

Abstract: A transistor includes a first fin structure and at least a second fin structure formed on a substrate. A deep trench area is formed between the first and second fin structures. The deep trench area extends through an insulator layer of the substrate and a semiconductor layer of the substrate. A high-k metal gate is formed within the deep trench area. A polysilicon layer is formed within the deep trench area adjacent to the metal layer. The polysilicon layer and the high-k metal layer are recessed below a top surface of the insulator layer. A poly strap in the deep trench area is formed on top of the high-k metal gate and the polysilicon material. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first fin structure and the second fin structure are electrically coupled to the poly strap.

Abstract: Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.

Abstract: A semiconductor device includes a semiconductor substrate; a well of a first conductivity type in the semiconductor substrate; a first element; and a first vertical transistor. The first element supplies potential to the well, the first element being in the well. The first element may include, but is not limited to, a first pillar body of the first conductivity type. The first pillar body has an upper portion that includes a first diffusion layer of the first conductivity type. The first diffusion layer is greater in impurity concentration than the well. The first vertical transistor is in the well. The first vertical transistor may include a second pillar body of the first conductivity type. The second pillar body has an upper portion that includes a second diffusion layer of a second conductivity type.

Abstract: A method of forming a semiconductor device includes the following processes. A first pillar and a second pillar are formed on a semiconductor substrate. A semiconductor film is formed which includes first and second portions. The first portion is disposed over a side surface of the first pillar. The second portion is disposed over a side surface of the second pillar. The first and second portions are different from each other in at least one of impurity conductivity type and impurity concentration. A part of the semiconductor film is removed by etching back. The first and second portions are etched at first and second etching rates that are different from each other.

Abstract: The present technology is related generally to vertical discrete devices with a trench at the topside of the vertical discrete devices. The trench is filled with a conducting material. In this approach, a drain or cathode of the vertical discrete devices is electrically connected to the topside to result in a small area with low RON*AREA.

Abstract: A vertical thin film transistor and a method for manufacturing the same and a display device including the vertical thin film transistor and a method for manufacturing the same are disclosed. The vertical thin film transistor is applied to a substrate. In the present invention, a gate layer of the vertical thin film transistor is formed to have a plurality of concentric annular structures and the adjacent concentric annular structures are linked. By the concentric annular structures of the gate electrode layer, resistance to stress and an on-state current of the vertical thin film transistor can be increased.

Abstract: DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

Abstract: A nonvolatile semiconductor memory device includes: a substrate; a stacked body with a plurality of dielectric films and electrode films alternately stacked therein, the stacked body being provided on the substrate and having a step in its end portion for each of the electrode films; an interlayer dielectric film burying the end portion of the stacked body; a plurality of semiconductor pillars extending in the stacking direction of the stacked body and penetrating through a center portion of the stacked body; a charge storage layer provided between one of the electrode films and one of the semiconductor pillars; and a plug buried in the interlayer dielectric film and connected to a portion of each of the electrode films constituting the step, a portion of each of the dielectric films in the center portion having a larger thickness than a portion of each of the dielectric films in the end portion.

Abstract: According to one embodiment, a semiconductor device having a Ge- or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si1-xGex (0<x<1) formed on the active area, and a fin structure of Si1-yGey (x<y?1) formed on the buffer layer. The fin structure has a side surface of a (110) plane perpendicular to the surface of the Si substrate and the width thereof in a direction perpendicular to the one direction of the fin structure is narrower than that of the buffer layer.

Abstract: A vertical transistor includes a gate isolating layer flanking a stack of a source layer, a resilient active unit and a drain layer, and a gate layer formed on the gate isolating layer. The active unit includes an active layer formed between first and second barrier layers each having a thickness ranging from 4 nm to 40 nm. When an input voltage including a DC component and a ripple component is applied to the source layer, the active unit periodically vibrates as a result of the ripple component of the input voltage such that an induced AC current is generated based on a control voltage applied to the gate layer to flow to the drain layer. The induced AC current flowing to the drain layer serves as an AC output generated by the vertical transistor based on the input voltage. A method of enabling a vertical transistor to generate an AC output is also disclosed.

Abstract: Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality fins is formed, the fins are isotropically etched to reduce a width of the fins and to round an upper surface of the fins. A first dielectric layer is formed overlying the isotropically etched fins. A first conductive layer is formed overlying the first dielectric layer. A second dielectric layer is formed overlying the first conductive layer. A second conductive layer is formed overlying the second dielectric layer.

Abstract: An access device and a semiconductor device are disclosed. The access device includes a vertically oriented channel separating a lower source/drain region and an upper source/drain region, a gate dielectric disposed on the channel, and a unified gate electrode/connection line coupled to the channel across the gate dielectric, wherein the unified gate electrode/connection line comprises a descending lip portion disposed proximate to the gate dielectric and overlaying at least a portion of the lower source/drain region.

Abstract: A method for manufacturing a semiconductor memory apparatus may include forming a channel region and a gate region through a self-alignment etching process on a cell region; and forming a three-dimensional multi-channel region through an etching process using a first multi-channel mask on a core region and a peripheral region and forming a gate region through an etching process using a second multi-channel mask, thereby preventing mis-arrangement of gates.

Abstract: A semiconductor device includes an n+ type semiconductor substrate 1 and a super junction region that has, on the top of the substrate 1, an n and p type pillar regions 2 and 3 provided alternately. The device also includes, in the top surface of the super junction region, a p type base region 4 and an n type source layer 5. The device also includes a gate electrode 7 on the region 4 and layer 5 via a gate-insulating film 6, a drain electrode 9 on the bottom of the substrate 1, and a source electrode 8 on the top of the substrate 1. In the top surface of the super junction region in the terminal region, a RESURF region 10 is formed. The RESURF region has a comb-like planar shape with repeatedly-formed teeth having tips facing the end portion of the terminal region.

Abstract: A semiconductor device is provided which includes an NMOS vertical channel transistor located on a substrate and including a p+ polysilicon gate electrode surrounding a vertical p-channel region, and a PMOS vertical channel transistor located on the substrate and including an n+ polysilicon gate electrode surrounding a vertical n-channel region. The NMOS and PMOS vertical channel transistors are optionally operable in a CMOS operational mode.

Abstract: For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates overlie the tunnel dielectric layer, and the floating gates correspond one-to-one with the fins protruding from the substrate. An intergate dielectric layer overlies the floating gates. A control gate layer overlies the intergate dielectric layer. Each fin includes an upper surface rounded by isotropic etching.

Abstract: A vertical transistor includes a substrate, a semiconductor structure, a gate, a gate dielectric layer, and a conductive layer. The semiconductor structure is disposed on the substrate and includes two vertical plates and a bottom plate. The bottom plate has an upper surface connected to bottoms of the two vertical plates and a bottom surface connected to the substrate. The gate surrounds the semiconductor structure to fill between the two vertical plates, and the gate is disposed around the two vertical plates. The gate dielectric layer is sandwiched in between the gate and the semiconductor structure, and the conductive layer is disposed on the semiconductor structure and electrically connected with tops of the two vertical plates.

Abstract: A vertically-conducting charge balance semiconductor power device includes an active area comprising a plurality of cells capable of conducting current along a vertical dimension when biased in a conducting state, and a non-active perimeter region surrounding the active area. No current flows along the vertical dimension through the non-active perimeter region when the plurality of cells is biased in the conducting state. Strips of p pillars and strips of n pillars are arranged in an alternating manner. The strips of p pillars have a depth extending along the vertical dimension, a width, and a length. The strips of p and n pillars extend through both the active area and the non-active perimeter region along a length of a die that contains the semiconductor power device. The length of the die extends parallel to the length of the strips of p pillars. Each of the strips of p pillars includes a plurality of discontinuities forming portions of a plurality of strips of n regions.

Abstract: A structure and method of forming a body contact for a semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.

Abstract: A semiconductor chip comprises a first MOS device, a second MOS device, a first metallization structure connected to said first MOS device, a second metallization structure connected to said second MOS device, a passivation layer over said first and second MOS devices and over said first and second metallization structures, and a third metallization structure connecting said first and second metallization structures.

Abstract: A semiconductor device having a super junction MOS transistor includes: a semiconductor substrate; a first semiconductor layer on the substrate; a second semiconductor layer on the first semiconductor layer; a channel forming region on a first surface portion of the second semiconductor layer; a source region on a first surface portion of the channel forming region; a source contact region on a second surface portion of the channel forming region; a gate electrode on a third surface portion of the channel forming region; a source electrode on the source region and the source contact region; a drain electrode on a backside of the substrate; and an anode electrode on a second surface portion of the second semiconductor layer. The anode electrode provides a Schottky barrier diode.

Abstract: A vertical transistor including a substrate, a gate, a base line and a gate dielectric layer is provided. The substrate includes a pillar protruding out of a surface of the substrate. The pillar includes a first doped region, a channel region and a second doped region from bottom to top. The gate is disposed on a sidewall at one side of the channel region. The base line is disposed on a sidewall at the other side of the channel region and not contacted with the gate. The gate dielectric layer is disposed between the gate and the channel region.

Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate.

Abstract: Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material separates the first and second doped regions. A third doped region is defined in the semiconductor material bordering the sidewall of the trench and disposed between the first and second doped regions. The third doped region is doped to have a second conductivity type opposite to the first conductivity type. Methods for forming the doped regions involve depositing either a layer of a material doped with both dopants or different layers each doped with one of the dopants in the trench and, then, diffusing the dopants from the layer or layers into the semiconductor material bordering the trench sidewall.

Abstract: A semiconductor device and methods for its fabrication are provided. The semiconductor device comprises a trench formed in the semiconductor substrate and bounded by a trench wall extending from the semiconductor surface to a trench bottom. A drain region and a source region, spaced apart along the length of the trench, are formed along the trench wall, each extending from the surface toward the bottom. A channel region is formed in the substrate along the trench wall between the drain region and the source region and extending along the length of the trench parallel to the substrate surface. A gate insulator and a gate electrode are formed overlying the channel.

Abstract: A method for producing an integrated circuit including a trench transistor and an integrated circuit is disclosed.

Abstract: A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the active pillars to fill a gap region between the active pillars; partially removing the first insulation layer to exposes a circumferential surface of the gate electrode in all directions, without exposing the substrate in the gap region between the active pillars; forming a conductive layer on the remaining first insulation layer to fill the gap region between the active pillars; and patterning the conductive layer to form a word line that surrounds and contacts the circumferential surface of the gate electrode in all directions.

Abstract: A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory including: a columnar semiconductor; a charge storage insulating film including: a first insulating film formed around the columnar semiconductor, a charge storage film formed around the first insulating film, and a second insulating film formed around the charge storage film; an electrode extending two-dimensionally to surround the charge storage insulating film, the electrode having a groove; and a metal silicide formed on a sidewall of the groove.

Abstract: According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; an element isolation region formed in the semiconductor substrate so as to extend in a first direction; a gate electrode formed in the semiconductor substrate so as to extend in a second direction crossing the first direction and to penetrate through the element isolation region; a gate insulating film interposed between the gate electrode and the semiconductor substrate; an interlayer dielectric film formed on the gate electrode; a ferroelectric capacitor including: first and second electrodes disposed on the interlayer dielectric film and a ferroelectric between the first and second electrodes; and first and second semiconductor pillars being in contact respectively with the first and second electrodes.

Abstract: A method is provided for producing a fin structure on a semiconductor substrate using a thin SiGe layer to produce a void between a silicon substrate and a silicon fin portion. A fin structure produced by such a method is also provided.