Abstract: A memory cell includes a memory element including a MFSFET having a gate insulating film made of a ferroelectric film, and a selection switching element including a MISFET having a gate insulating film made of a paraelectric film. A load element for a read operation is connected in series to the memory cell. The ferroelectric film and the paraelectric film are stacked with a semiconductor film being interposed therebetween. The semiconductor film forms a common channel shared by the MFSFET and the MISFET. The load element includes a MISFET having a channel made of the semiconductor film or a resistance element having a resistor made of the semiconductor film.

Abstract: It is an object of the present invention to provide a technology for forming an ULSI fine copper wiring by a simpler method. An electronic component in which a thin alloy film of tungsten and a noble metal used as a barrier-seed layer for an ULSI fine copper wiring is formed on a base material, wherein the thin alloy film has a composition comprising tungsten at a ratio equal to or greater than 60 at. % and the noble metal at a ratio of equal to or greater than 5 at. % and equal to or less than 40 at. %. The noble metal is preferably one or more kinds of metals selected from the group consisting of platinum, gold, silver and palladium.

Abstract: Provided is a semiconductor device that includes: a base insulating film 25 formed above a silicon substrate 10; a ferroelectric capacitor Q formed on the base insulating film 25; multiple interlayer insulating films 35, 48, and 62, and metal interconnections 45, 58, and 72 which are alternately formed on and above the capacitor Q; and conductive plugs 57 which are respectively formed inside holes 54a provided in the interlayer insulating films 48 and are electrically connected to the metal interconnections 45. In the semiconductor device, a first capacitor protection insulating film 50 is formed on an upper surface of the interlayer insulating film 48 by sequentially stacking a first insulating metal oxide film 50a, an intermediate insulating film 50b having a relative dielectric constant lower than that of the interlayer insulating film 48, and a second insulating metal oxide film 50c; and the holes 54a are also formed in the first capacitor protection insulating film 50.

Abstract: A semiconductor memory device includes: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; an interlayer dielectric layer formed on the field effect transistor; a contact plug connected to the field effect transistor through the interlayer dielectric layer; and a ferroelectric capacitor disposed on the interlayer dielectric layer and connected to the contact plug, wherein a contact surface between a lower electrode of the ferroelectric capacitor and the contact plug is smaller than a contact plug surface of the contact plug.

Abstract: A memory includes a first conductive-type first diffusion layer on the semiconductor substrate; second conductive-type bodies on the first diffusion layer(s); first conductive-type second diffusion layers on the bodies; first gate dielectric films comprising ferroelectric films and provided on first side surfaces of the bodies; second gate dielectric films comprising ferroelectric films and provided on second side surfaces of the bodies; first gate electrodes on the first gate dielectric film; and second gate electrodes on the second gate dielectric film, wherein the first and the second diffusion layers, the body, the first and the second gate dielectric films, and the first and the second gate electrodes constitute memory cells, and each of the memory cells stores a plural pieces of logical data depending on a polarization state of the first gate dielectric film and on a polarization state of the second gate dielectric film.

Abstract: A semiconductor device is equipped with a plug conductive layer formed in an interlayer dielectric film on a substrate, and a conductive member provided on the plug conductive layer. The semiconductor device further includes a spacer dielectric film formed on the interlayer dielectric film and having a hole section connecting to the plug conductive layer; and a spacer conductive section embedded in the hole section of the spacer dielectric film, connected to the plug conductive layer and connected to the conducive member, wherein the spacer conductive section is formed from a conductive material having self-orientation characteristic, and a top surface of the spacer dielectric film and a top surface of the spacer conductive section are planarized.

Abstract: Flux-closed spin-transfer torque memory having a specular insulative spacer is disclosed. A flux-closed spin-transfer torque memory unit includes a multilayer free magnetic element including a first free magnetic layer anti-ferromagnetically coupled to a second free magnetic layer through an electrically insulating and electronically reflective layer. An electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic element from a reference magnetic layer.

Abstract: The use of atomic layer deposition (ALD) to form a zirconium substituted layer of barium titanium oxide (BaTiO3), produces a reliable ferroelectric structure for use in a variety of electronic devices such as a dielectric in nonvolatile random access memories (NVRAM), tunable dielectrics for multi layer ceramic capacitors (MLCC), infrared sensors and electro-optic modulators. The structure is formed by depositing alternating layers of barium titanate and barium zirconate by ALD on a substrate surface using precursor chemicals, and repeating to form a sequentially deposited interleaved structure of desired thickness and composition. Such a layer may be used as the gate insulator of a MOSFET, or as a capacitor dielectric. The properties of the dielectric may be tuned by adjusting the percentage of zirconium to titanium to optimize properties such as a dielectric constant, Curie point, film polarization, ferroelectric property and a desired relaxor response.

Abstract: A dual-gate non-volatile memory cell includes a first dielectric layer extending over a first gate, a semiconductor region extending over the first dielectric layer, a second dielectric layer comprising tunnel oxide extending over the semiconductor region, a ferroelectric layer extending over the second dielectric layer, and a second gate extending over the ferroelectric layer.

Abstract: A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a bottom word line formed in the insulating layer so as to be enclosed by the insulating layer, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.

Abstract: Methods of forming planar carbon nanotube (“CNT”) resistivity-switching materials for use in memory cells are provided, that include depositing first dielectric material, patterning the first dielectric material, etching the first dielectric material to form a feature within the first dielectric material, depositing CNT resistivity-switching material over the first dielectric material to fill the feature at least partially with the CNT resistivity-switching material, depositing second dielectric material over the CNT resistivity-switching material, and planarizing the second dielectric material and the CNT resistivity-switching material so as to expose at least a portion of the CNT resistivity-switching material within the feature. Other aspects are also provided.

Abstract: As an example of a nitride semiconductor light emitting device, on a sapphire substrate, a GaN buffer layer, an n-type GaN contact layer, an MQW active layer, and a p-type GaN contact layer are sequentially stacked, and a partial region from the p-type GaN contact layer to the middle of the n-type GaN contact layer is mesa-etched so as to form an n electrode. Meanwhile, a p electrode is provided on the p-type GaN contact layer, and, in addition to the p electrode, multiple ridge parts are formed by crystal growth so as to be scattered. By providing the multiple ridge parts, device characteristics can be improved without causing damage on the GaN-based semiconductor layer.

Abstract: A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode, a resistance variable material over the first electrode, and a first second-electrode over the resistance variable material. The first second-electrode is associated with the first electrode to define a first memory element. Each memory unit further includes a second second-electrode over the resistance variable material. The second-second electrode is associated with the first electrode to define a second memory element.

Abstract: Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.

Abstract: A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).

Abstract: A memory device including a dielectric thin film having a plurality of dielectric layers and a method of manufacturing the same are provided. The memory device includes: a bottom electrode; at least one dielectric thin film disposed on the bottom electrode and having a plurality of dielectric layers with different charge trap densities from each other; and an top electrode disposed on the dielectric thin film. Therefore, a memory device, which can be readily manufactured by a simple process and can be highly integrated using its simple structure, can be provided.

Abstract: A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 ?, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

Abstract: A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a bottom word line formed in the insulating layer so as to be enclosed by the insulating layer, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.

Abstract: A ferroelectric capacitor is formed over a semiconductor substrate (10), and thereafter, interlayer insulating films (48, 50, 52) covering the ferroelectric capacitor are formed. Next, a contact hole (54) reaching a top electrode (40) is formed in the interlayer insulating films (48, 50, 52). Next, a wiring (58) electrically connected to the top electrode (40) through the contact hole (54) is formed on the interlayer insulating films (48, 50, 52). At the time of forming the top electrode (40), conductive oxide films (40a, 40b) are formed, and then a cap film (40c) composed of a noble metal exhibiting less catalytic action than Pt and having a thickness of 150 nm or less is formed on the conductive oxide films (40a, 40b).

Abstract: A method for manufacturing a ferroelectric memory device includes: forming a conductive base layer above a substrate; and laminating above the base layer a first electrode, a ferroelectric layer and a second electrode, wherein, prior to the step of forming the base layer, the method includes forming an active element in the substrate, forming an interlayer dielectric film on the substrate, and forming a contact plug in the interlayer dielectric film, and wherein the step of forming the base layer includes: forming a first conductive layer composed of a conductive material having a self-orienting property on the interlayer dielectric film including the contact plug; planarizing the first conductive layer by a chemical mechanical polishing method thereby forming a planarized first conductive layer that covers the interlayer dielectric film including the contact plug; applying an ammonia plasma process to a surface of the planarized first conductive layer; forming a titanium layer on the planarized first conduct

Abstract: An interlayer insulating film (14) covering a ferroelectric capacitor is formed and a contact hole (19) reaching a top electrode (11a) is formed in the interlayer insulating film (14). An Al wiring (17) connected to the top electrode (11a) via the contact hole (19) is formed on the interlayer insulating film (14). A planar shape of the contact hole (19) is an ellipse.

Abstract: A method of manufacturing patterned ferroelectric media, which includes forming an electrode on a substrate; forming features having a predetermined pattern on the electrode, the features including a precursor for forming a ferroelectric material; and reacting a source material with the precursor features to transform the precursor features into ferroelectric features. Also disclosed is a method which includes forming on a substrate an electrode having wells and precursor features formed in the wells of the electrode, the precursor features including a precursor for forming a ferroelectric material; and reacting a source material with the precursor features to transform the precursor features into ferroelectric features. The above first embodiment relates to non-embedded type media, and the above second embodiment relates to embedded type media.

Abstract: A resistive memory device includes: a substrate, an insulation layer arranged over the substrate, a first electrode plug penetrating the insulation layer from the substrate, having a portion protruded out of an upper portion of the insulation layer, and having peaks at edges of the protruded portion, a resistive layer disposed over the insulation layer and covering the first electrode plug, and a second electrode arranged over the resistive layer.

Abstract: A ferroelectric capacitor having a three-dimensional structure, a nonvolatile memory device having the same, and a method of fabricating the same are provided. The ferroelectric capacitor may include a trench-type lower electrode, at least one layer formed around the lower electrode, a ferroelectric layer (PZT layer) formed on the lower electrode and the at least one layer and an upper electrode formed on the ferroelectric layer. The at least one layer may be at least one insulating interlayer and the at least one layer may also be at least one diffusion barrier layer. The at least one layer may be formed of an insulating material excluding SiO2 or may have a perovskite crystal structure excluding Pb.

Abstract: An aspect of the present disclosure, there is provided semiconductor memory device including a ferroelectric capacitor and a field effect transistor as a memory cell, the ferroelectric capacitor including a lower electrode connected to one of the pair of the impurity diffusion layers, a bit line formed below the lower electrode, wherein each of the memory cells shares the bit line contact with an adjacent memory cell at one side in the first direction to connect to the bit line, and three of the word lines are formed between the bit line contacts in the first direction.

Abstract: A ferroelectric memory device manufacturing method includes the steps of forming an interlayer isolating film for covering a transistor formed on a semiconductor substrate; forming a conductive plug in the interlayer insulating film to contact a diffusion region of the transistor formed on the semiconductor substrate; forming a ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode; and forming a compound film including silicon (Si) and a CH group on a surface of the interlayer insulating film and a surface of the conductive plug by depositing a Si compound containing Si atoms and the CH groups; wherein the compound film is formed after forming the conductive plug, and the compound film is formed before forming the lower electrode; and a self-orientation film is formed on a surface of the compound film.

Abstract: The present invention is to provide a semiconductor memory device capable of providing excellent storage properties, scaling and high integration and a method of fabricating the same. A semiconductor memory device has a multiferroic film exhibiting ferroelectricity and ferromagnetism, a channel region on an interface of a semiconductor substrate below the multiferroic film, source and drain regions formed on both sides of the channel region, a gate electrode (data write electrode) applying gate voltage to the multiferroic film to write data in such a way that the orientation of magnetization is changed as corresponding to the orientation of dielectric polarization, and source and drain electrodes (data read electrodes) that read data based on a deviation in a flow of the carrier, the deviation caused by applying the Lorentz force to the carrier flowing in the channel region from a magnetic field occurring in the channel region because of magnetization.

Abstract: A ferroelectric memory device includes a field effect transistor formed over a semiconductor substrate and including first and second diffusion regions, an interlayer insulation film formed over the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug. The ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below.

Abstract: A semiconductor device includes a ferroelectric capacitor formed above the lower interlevel insulating film covering a MOS transistor formed on a semiconductor substrate, including lamination of a lower electrode, an oxide ferroelectric film, a first upper electrode made of conductive oxide having a stoichiometric composition AOx1 and an actual composition AOx2, a second upper electrode made of conductive oxide having a stoichiometric composition BOy1 and an actual composition BOy2, where y2/y1>x2/x1, and a third upper electrode having a composition containing metal of the platinum group; and a multilayer wiring structure formed above the lower ferroelectric capacitor, and including interlevel insulating films and wirings. Abnormal growth and oxygen vacancies can be prevented which may occur when the upper electrode of the ferroelectric capacitor is made of a conductive oxide film having a low oxidation degree and a conductive oxide film having a high oxidation degree.

Abstract: The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared by the following steps. A single-crystalline MgO (001) substrate 11 is prepared. An epitaxial Fe(001) lower electrode (a first electrode) 17 with the thickness of 50 nm is grown on a MgO(001) seed layer 15 at room temperature, followed by annealing under ultrahigh vacuum (2×10?8 Pa) and at 350° C. A MgO(001) barrier layer 21 with the thickness of 2 nm is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) with the thickness of 10 nm is then formed on the MgO(001) barrier layer 21 at room temperature. This is successively followed by the deposition of a Co layer 21 with the thickness of 10 nm on the Fe(001) upper electrode (the second electrode) 23.

Abstract: A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.

Abstract: A memory includes first contact plugs; ferroelectric capacitors above the first contact plugs; second contact plugs in a first interlayer film being below an area which is between two adjacent ferroelectric capacitors, the second contact plug; first interconnections connected to the second contact plugs, the first interconnections extending in a first direction substantially perpendicular to an arrangement direction, in which the two ferroelectric capacitors are arranged, on the first interlayer film; a second interlayer film above the first interlayer film and the first interconnection; third contact plugs in the second interlayer film, the third contact plugs being respectively connected to the first interconnections at positions shifted from the second contact plugs in the first direction; and second interconnections electrically connecting the third contact plug to the upper electrodes of the two ferroelectric capacitors.

Abstract: An aspect of the present disclosure, there is provided a magnetoresistive random access memory device, including, an active area formed on a semiconductor substrate in a first direction, a magnetoresistive effect element formed on the active area and storing data by a change in resistance value, a gate electrode of a cell transistor formed on each side of the magnetoresistive effect element on the active area in a second direction, a bit line contact formed on the active area and arranged alternately with the magnetoresistive effect element, a first bit line connected to the magnetoresistive effect, and a second bit line connected to the bit line contact.

Abstract: The present invention describes a method including: providing a substrate; forming an underlying layer over the substrate; heating the substrate; forming a ferroelectric layer over the underlying layer, the ferroelectric layer having a thickness below a critical thickness, the underlying layer having a smaller lattice constant than the ferroelectric layer; cooling the substrate to room temperature; and inducing a compressive strain in the ferroelectric layer.

Abstract: Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode.

Abstract: A memory device includes: a memory layer that retains information based on a magnetization state of a magnetic material, a first intermediate layer and a second intermediate layer that are provided to sandwich the memory layer and are each formed of an insulator, a first fixed magnetic layer disposed on an opposite side of the first intermediate layer from the memory layer, a second fixed magnetic layer disposed on an opposite side of the second intermediate layer from the memory layer, and a nonmagnetic conductive layer provided between either the first intermediate layer or the second intermediate layer and the memory layer, the memory device being configured so that spin-polarized electrons are injected thereinto in a stacking direction to change the magnetization direction of the memory layer, thereby storing information in the memory layer.

Abstract: A multi-layer non-volatile memory integrally formed on top of a substrate including active circuitry is disclosed. Each layer of memory includes memory cells (e.g., a two-terminal memory cell) having a multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a write voltage across the memory cell. Data stored in the memory cells can be non-destructively determined by applying a read voltage across the memory cells. Data storage capacity can be tailored to a specific application by increasing or decreasing the number of memory layers that are integrally fabricated on top of the substrate (e.g., more than four layers or less than four layers). The memory cells can include a non-ohmic device for allowing access to the memory cell only during read and write operations. Each memory layer can comprise a cross point array.

Abstract: A nonvolatile ferroelectric memory device includes a plurality of unit cells. Each of the unit cells includes a cell capacitor and a cell transistor. The cell capacitor includes a storage node, a ferroelectric layer, and a plate line. The cell capacitors of more than one of the plurality of unit cells are provided in a trench.

Abstract: A memory element including a first FET, and a selection switch including a second FET are connected in series, and a semiconductor film and a dielectric film stacked over a substrate form a common channel and a common gate insulating film in the first and second FETs. A first gate electrode of the first FET and a second gate electrode of the second FET are formed on the dielectric film, and a drain electrode and a source electrode are formed on the semiconductor film. Under the semiconductor film, a back-gate electrode is formed with a ferroelectric film interposed therebetween, and the ends of the semiconductor film that forms the channel are located inwardly of the ends of the back-gate electrode.

Abstract: A method for fabricating a ferroelectric memory device, including terminating a surface of the interlayer insulation film and a surface of the contact plug with an OH group; forming a layer containing Si, oxygen and a CH group on the surface of the interlayer insulation film and the contact hole terminated with the OH group by coating a Si compound containing a Si atom and a CH group in a molecule thereof; converting the layer containing Si, oxygen and the CH group to a layer containing nitrogen at a surface thereof, by substituting the CH group in the layer containing Si, oxygen and the CH group at least at a surface part thereof with nitrogen atoms; and forming a layer showing self-orientation on the surface containing nitrogen.

Abstract: Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode structures separated by a gap; and a polymer-based ferroelectric layer overlying and directly abutting some of the electrode structures. Methods may comprise actions to form and operate the apparatus and systems. Additional apparatus, systems, and methods are disclosed.

Abstract: Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.

Abstract: A multi-bit spin torque magnetic element that has a ferromagnetic pinned layer having a pinned magnetization orientation, a non-magnetic layer, and a ferromagnetic free layer having a magnetization orientation switchable among at least four directions, the at least four directions being defined by a physical shape of the free layer. The magnetic element has at least four distinct resistance states. Magnetic elements with at least eight magnetization directions are also provided.

Abstract: A layered ferromagnetic structure is composed of a first ferromagnetic layer positioned over a substrate; a second ferromagnetic layer positioned over the first ferromagnetic layer; and a first non-magnetic layer placed between the first and second ferromagnetic layers. The top surface of the first ferromagnetic layer is in contact with the first non-magnetic layer. The first ferromagnetic layer includes a first orientation control buffer that exhibits an effect of enhancing crystalline orientation of a film formed thereon.

Abstract: There is provided a semiconductor device including, a semiconductor substrate having a circuit forming region and a peripheral region, a base insulating film formed over the semiconductor substrate, a capacitor formed of a lower electrode, a capacitor dielectric film made of a ferroelectric material, and an upper electrode in this order over the base insulating film in the circuit forming region, an uppermost interlayer insulating film formed over the capacitor, a seal ring formed over the semiconductor substrate in the peripheral region, the seal ring having a height that reaches at least the upper surface of the interlayer insulating film, and surrounding the circuit forming region, a block film formed over the seal ring and over the interlayer insulating film in the circumference of the seal ring, and an electrode conductor pattern which is formed over the interlayer insulating film in the peripheral region, the electrode conductor pattern having an electrode pad, and having a cross-section exposed to a di

Abstract: According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; an element isolation region formed in the semiconductor substrate so as to extend in a first direction; a gate electrode formed in the semiconductor substrate so as to extend in a second direction crossing the first direction and to penetrate through the element isolation region; a gate insulating film interposed between the gate electrode and the semiconductor substrate; an interlayer dielectric film formed on the gate electrode; a ferroelectric capacitor including: first and second electrodes disposed on the interlayer dielectric film and a ferroelectric between the first and second electrodes; and first and second semiconductor pillars being in contact respectively with the first and second electrodes.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first ferroelectric film over a lower electrode, crystallizing the first ferroelectric film, forming a second ferroelectric film in an amorphous state over the first ferroelectric film so as to fill voids existing on a surface of the first ferroelectric film, and forming an upper electrode over the second ferroelectric film of the amorphous state, wherein the crystallizing step of the first ferroelectric film is conducted by a thermal annealing process at a temperature of 585° C. or higher.

Abstract: A semiconductor memory device, comprising: a semiconductor substrate; a memory cell section comprising a memory transistor provided on the semiconductor substrate, the memory transistor including a first gate electrode provided on the semiconductor substrate with a gate insulating film interposed therebetween, and a source and drain provided at both sides of the first gate electrode on the semiconductor substrate, and a ferroelectric capacitor provided above the memory transistor, the ferroelectric capacitor including a first electrode film connected to any one of a source and drain of the memory transistor, a second electrode film connected to the other one of the drain and source of the memory transistor, and a ferroelectric film provided between the first electrode film and the second electrode film, the memory cell section having the memory transistor and the ferroelectric capacitor connected in parallel to each other; and a select transistor section, comprising a select transistor provided at an end of t

Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a transistor including: a source, a drain and a gate; first and second plugs on the source and the drain; a third plug on the gate to have a top face higher than that of the first plug; an interlayer insulating film covering the transistor and the first to the third plugs; a ferroelectric capacitor on the interlayer insulating film, one electrode thereof being connected to the first plug; a barrier film covering surfaces of the ferroelectric capacitor and the interlayer insulating film to prevent a substance affecting the ferroelectric capacitor from entering therethrough; and fourth and fifth plugs disposed on the second and the third plugs and connected thereto through connection holes formed in the barrier film.

Abstract: A nonvolatile ferroelectric memory device includes a plurality of unit cell arrays, wherein each of the plurality of unit cell arrays includes: a bottom word line; a plurality of insulating layers formed on the bottom word line, respectively; a floating channel layer comprising a plurality of channel regions located on the plurality of insulating layers and a plurality of drain and source regions which are alternately electrically connected in series to the plurality of channel regions; a plurality of ferroelectric layers formed respectively on the plurality of channel regions of the floating channel layer; and a plurality of word lines formed on the plurality of ferroelectric layers, respectively. The unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of channel regions depending on polarity states of the plurality of ferroelectric layers.