Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.

Abstract: The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer.

Abstract: Second diffusion layers to be guard rings of a second conductivity type are formed on the major surface of a semiconductor substrate of a first conductivity type in a guard ring region. An insulating film is formed on these second diffusion layers. The semiconductor device has a structure wherein a conductive film is formed on the insulating film between adjacent electrodes among a first surface electrode, second surface electrodes, and a third surface electrode.

Abstract: In a lateral thin-film Silicon-On-Insulator (SOI) device, a field plate is provided to extend substantially over a lateral drift region to protect the device from package and surface charge effects. In particular, the field plate comprises a layer of plural metallic regions which are isolated laterally from one another by spacing so as to assume a lateral electric field profile which is established by a volume doping gradient in the silicon drift region.

Abstract: A gallium nitride high electron mobility transistor, in which an inner field-plate is disposed between the gate and drain of the high electron mobility transistor, so that an electric field is distributed between gate and drain regions to reduce a peak value and to reduce gate leakage current while maintaining high frequency performance, thus obtaining a high breakdown voltage, reducing the capacitance between the gate and the drain attributable to a shielding effect, and improving linearity and high power and high frequency characteristics through variation in the input voltage of the inner field-plate.

Abstract: A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 m?-cm2, of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 m?-cm2, of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.

Abstract: In accordance with an embodiment of the invention, a semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. A first silicon region of a first conductivity type extends to a first depth within a second silicon region of a second conductivity type, the first and second silicon regions forming a PN junction therebetween. At least one termination trench is formed in the termination. The termination trench extends into the second silicon region, and is laterally spaced from the first silicon region. An insulating layer lines the sidewalls and bottom of the termination trench. A conductive electrode at least partially fills the termination trench.

Abstract: A transistor structure comprising an active semiconductor layer with metal source and drain contacts formed in electrical contact with the active layer. A gate contact is formed between the source and drain contacts for modulating electric fields within the active layer. A spacer layer is formed above the active layer and a conductive field plate formed above the spacer layer, extending a distance Lf from the edge of the gate contact toward the drain contact. The field plate is electrically connected to the gate contact.

Abstract: A method includes forming a plurality of functional features on a semiconductor layer in a first region. A non-functional feature corresponding to the functional feature is formed adjacent at least one of the functional features disposed on a periphery of the region. A stress-inducing layer is formed over at least a portion of the functional features and the non-functional feature. A device includes a semiconductor layer, a first dummy gate electrode, and a stress-inducing layer. The plurality of transistor gate electrodes is formed above the semiconductor layer. The plurality includes at least a first end gate electrode, a second end gate electrode, and at least one interior gate electrode. The first dummy gate electrode is disposed proximate the first end gate electrode. The stress-inducing layer is disposed over at least a portion of the plurality of transistor gate electrodes and the first dummy gate electrode.

Abstract: A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

Abstract: A MOS field plate trench transistor device is disclosed. In one embodiment, in order to obtain a lowest possible on resistance, in the case of a MOS field plate trench transistor device having a body contact hole, it is proposed to form the avalanche breakdown region preferably in an end region of a provided trench structure by virtue of the fact that a mesa region with the body contact region in the semiconductor region as intermediate region in a direction running perpendicular to the first direction and with respect to an adjacent MOS transistor device has a width DMesa, the value of which corresponds to the value of the width DTrench of the trench structure in this direction or exceeds said value and does not go beyond 1.5 times said value, so that the following holds true: DTrench?DMesa?1.5·DTrench. As an alternative, the width DMesa is chosen such that the body contact hole precisely still has space, but the breakdown region is in any event shifted into the end region.

Abstract: A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A nitride semiconductor device according to one embodiment of the present invention includes: a non-doped first aluminum gallium nitride (AlxGa1-xN (0?x?1)) layer which is formed as a channel layer; a non-doped or n type second aluminum gallium nitride (AlyGa1-yN (0?y?1, x <y)) layer which is formed on the first aluminum gallium nitride layer as a barrier layer; an aluminum nitride (AlN) film which is formed on the second aluminum gallium nitride layer as a gate insulating film lower layer; an aluminum oxide (AL2O3) film which is formed on the aluminum nitride film as a gate insulating film upper layer; a source electrode and a drain electrode which are formed as first and second main electrodes to be electrically connected to the second aluminum gallium nitride layer, respectively; and a gate electrode which is formed on the aluminum oxide film as a control electrode.

Abstract: A technique of spreading current flowing in a semiconductor device comprising an electrode, a drift region adjacent to the electrode, a junction termination extension implant region in the drift region, and a current spreader adjacent to the junction termination extension implant region and the electrode. The current spreader is adapted to reduce current densities and electrostatic fields (preferably simultaneously) in an area connecting the electrode with the drift region. Moreover, the current spreader is adapted to spread current flowing from the electrode into the drift region. The semiconductor device further comprises an ohmic metal contact connected to the electrode and an implant pocket in the drift region, wherein the implant pocket is adapted for terminating electrostatic field lines in the semiconductor device. Preferably, the current spreader comprises an ohmic metal and the electrode comprises any of an anode and a cathode.

Abstract: In accordance with an embodiment of the invention, a semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. A first silicon region of a first conductivity type extends to a first depth within a second silicon region of a second conductivity type, the first and second silicon regions forming a PN junction therebetween. At least one termination trench is formed in the termination. The termination trench extends into the second silicon region, and is laterally spaced from the first silicon region. An insulating layer lines the sidewalls and bottom of the termination trench. A conductive electrode at least partially fills the termination trench.

Abstract: A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: A field effect device includes at least one segmented field plate, each of the at least one segmented field plates having a plurality of segments that each form a plate of a capacitor, wherein the field effect device is connected to an electronic element that dynamically connects selected segments to selectively set a gate-to-drain and a drain-to-source capacitance. An ultrasonic device includes a transducer coupled to a switching device that switches the transducer between a transmit mode and a receive mode switching device, wherein the switching device includes the field effect device.

Abstract: In a semiconductor device of the present invention, a MOS transistor is disposed in an elliptical shape. Linear regions in the elliptical shape are respectively used as the active regions, and round regions in the elliptical shape is used respectively as the inactive regions. In each of the inactive regions, a P type diffusion layer is formed to coincide with a round shape. Another P type diffusion layer is formed in a part of one of the inactive regions. These P type diffusion layers are formed as floating diffusion layers, are capacitively coupled to a metal layer on an insulating layer, and assume a state where predetermined potentials are respectively applied thereto. This structure makes it possible to maintain current performance of the active regions, while improving the withstand voltage characteristics in the inactive regions.

Abstract: A p well serving as a channel region of a MOSFET is formed on one side of an n? layer and an n+ drain region is formed on the other side. Above the n? layer, a plurality of first floating field plates are formed with a first insulating film interposed therebetween. A plurality of second floating field plates are formed thereon with a second insulating film interposed therebetween. Assuming that the thickness of the first insulating film is “a” and the distance between the first floating field plates and the second floating field plates in a direction of thickness of the second insulating film is “b”, a relation a>b is held.

Abstract: A monolithically integrated circuit comprises a thin film resistor (8) with low resistance and low temperature coefficient; a high frequency lateral power transistor device (9) including gate (17), source (16) and drain (15) regions, and a Faraday shield layer region (22; 22?) above the gate region; and at least a first metallization layer (28) there above for electrical connection of the gate (17), source (16) and drain (15) regions through via holes filled with conductive material (29c–d). The thin film resistor (8) and the Faraday shield layer region (22; 22?) are made in the same conductive layer, which is arranged below the first metallization layer (28).

Abstract: A high voltage laterally double-diffused metal oxide semiconductor (LDMOS) stricture is characterized as follows: the second source electrode metal layer connected to the first source electrode metal layer protrudes out of a certain length relative to the first source electrode metal layer of the source electrode region connected thereto. The second drain electrode metal layer connected to the first drain electrode metal layer protrudes out of a certain length relative to the first drain electrode metal layer of the drain electrode region. The protruded length overlaps more portions of the drift layer than the first source electrode metal layer and the first drain electrode metal layer disposed below, to reduce the electric field concentration of the gate electrode interface or the interface between the N+ type drain electrode layer and the N-type extended drift layer.