Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.

Abstract: In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core.

Abstract: A circuit structure of an ultra high voltage level shifter includes a low voltage substrate having the electronic elements of the ultra high voltage level shifter thereon, an ultra high voltage redistribution layer, and a passivation layer between the substrate and the redistribution layer to prevent dielectric breakdown between the redistribution layer and the substrate.

Abstract: A silicon-on-insulator device with a with buried depletion shield layer.

Abstract: Electrostatic discharge devices and methods of forming thereof are disclosed. In one embodiment, a semiconductor device includes an electrostatic discharge (ESD) device region disposed within a semiconductor body. A first ESD device is disposed in a first region of the ESD device region, and a second ESD device disposed in a second region of the ESD device region. The second region is separated from the first region by a first trench.

Abstract: A method for forming an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate. A flowable insulation layer is formed to fill the trench. The flowable insulation layer is recessed. A buried insulation layer is deposited on the flowable insulation layer while keeping a deposition sputtering rate (DSR) below about 22 so as to fill the trench with the buried insulation layer while restraining the buried insulation layer from growing on a lateral portion of the trench.

Abstract: A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer.

Abstract: A semiconductor device includes at least one semiconductor element having a semiconductor stack containing a channel layer and a cap layer and a lower electrode and an upper electrode formed over a semiconductor stack, and at least one protective element having the semiconductor stack in common with the semiconductor element for protecting the semiconductor element. The protective element includes a recessed portion that penetrates the cap layer in the direction of the thickness, an insulation region formed in the semiconductor stack from the bottom of the recessed portion 221 in the direction of the thickness, and a pair of ohmic electrodes and formed on both sides of the recessed portion and connected to the cap layer.

Abstract: A semiconductor device includes a plurality of first MOS transistors has a first gate electrode formed on a first gate insulating film provided on a semiconductor substrate, a plurality of second MOS transistors has a second gate electrode formed on a second gate insulating film which is provided on the substrate and which is smaller in thickness than the first gate insulating film. A first element isolation region has a first region and a second region, a bottom surface of the second region is deeper than that of the first region by the difference of thickness between the first gate insulating film and the second gate insulating film, and a bottom surface of the first region is equal in a bottom surface of a second element isolation region.

Abstract: A method of forming a bonded wafer structure includes providing a first semiconductor wafer substrate having a first silicon oxide layer at the top surface of the first semiconductor wafer substrate; providing a second semiconductor wafer substrate; forming a second silicon oxide layer on the second semiconductor wafer substrate; forming a silicon nitride layer on the second silicon oxide layer; and bringing the first silicon oxide layer of the first semiconductor wafer substrate into physical contact with the silicon nitride layer of the second semiconductor wafer substrate to form a bonded interface between the first silicon oxide layer and the silicon nitride layer. Alternatively, a third silicon oxide layer may be formed on the silicon nitride layer before bonding. A bonded interface is then formed between the first and third silicon oxide layers. A bonded wafer structure formed by such a method is also provided.

Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

Abstract: Silicon wafers, are manufactured with which a desired strength and electric resistance of a semiconductor device can be obtained. A non-oxidizing heat treatment for oxygen out-diffusion is performed wherein the desired amount of oxygen is discharged from the surface layer of the silicon substrate. By this heat treatment for oxygen out-diffusion, a surface layer having a low oxygen content is formed on the silicon substrate, the heat treatment of the silicon substrate being performed through an oxide film.

Abstract: An integrated microelectronic device is formed from a substrate having a first side and a second side and including a doped active zone (2) in the first side of the substrate. A circuit component is situated in the doped active zone. A through silicon via extends between the second side and the first side, the via being electrically isolated from the substrate by an insulating layer. A buffer zone is situated between the insulating layer and the doped active zone. This buffer zone is positioned under a shallow trench isolation zone provided around the doped active zone. The buffer zone functions to reduce the electrical coupling between the through silicon via and the doped active zone.

Abstract: Methods and structures for a semiconductor device can use mask openings of varying widths to form structures of different depths, different materials, and different functionality. For example, processes and structures for forming shallow trench isolation, deep isolation, trench capacitors, base, emitter, and collector, among other structures for a lateral bipolar transistor are described.

Abstract: A passivation structure and fabricating method thereof includes providing a chip having a main die region and a scribe line region defined thereon and a plurality of metal pads respectively positioned in the main die region and the scribe line region, forming a first patterned passivation layer having a plurality of first openings and second openings respectively exposing the metal pads in the main die region and the scribe line region on the chip, and forming a second patterned passivation layer filling the first openings in the scribe line region and having a plurality of third openings corresponding to the first openings thus exposing the metal pads in the main die region.

Abstract: A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive back gate layer formed on the lower insulating layer; an upper insulating layer formed on the back gate layer; and a hybrid semiconductor-on-insulator layer formed on the upper insulating layer, the hybrid semiconductor-on-insulator layer comprising a first portion having a first crystal orientation and a second portion having a second crystal orientation.

Abstract: The disclosed invention provides a structure and method for providing a high lateral voltage resistance between the electrical networks, sharing a lateral plane, of conductive elements (e.g., having different high voltage potentials) comprising a coupler. In one embodiment, an integrated coupler providing a high lateral voltage resistance comprises a primary conductive element and a secondary conductive element. An isolating material is laterally configured between the electrical network of the primary conductive element and an electrical network of the secondary conductive element. The isolating material may comprise a low-k dielectric layer and prevents any lateral barrier layers (e.g., etch stop layers, diffusion barrier layers, etc.) from extending between the first conductive element and the electrical network of the second conductive element. The structure therefore provides a galvanically isolated integrated coupler which avoids electrical shorting between circuits (e.g.

Abstract: An integrated circuit structure comprises a semiconductor substrate, a device region positioned in the semiconductor substrate, an insulating region adjacent to the device region, an isolation structure positioned in the insulating region and including a bottle portion and a neck portion filled with a dielectric material, and a dielectric layer sandwiched between the device region and the insulation region.

Abstract: A semiconductor device comprises a semiconductor substrate of the first conductivity type. A well layer of the first conductivity type is selectively formed on the semiconductor substrate. A first diffused layer of the second conductivity type is selectively formed on the well layer. A second diffused layer of the second conductivity type is formed on the well layer apart from the first diffused layer. A control electrode is formed on an insulating film between the first diffused layer and the second diffused layer. A main electrode is formed on each of the first diffused layer and the second diffused layer. A first trench is formed in the semiconductor substrate surrounding the well layer. A third diffused layer of the second conductivity type is formed contacting to the first trench. The second diffused layer and the third diffused layer are electrically kept at the same potential.

Abstract: A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve the yield, and trench grooves are formed to be deep in the high voltage transistor region of the peripheral circuit region, in particular in a high voltage transistor region thereof, in order to improve the element isolation withstand voltage. A plurality of memory cell transistors having an ONO layer 15 serving as a charge accumulating insulating layer are provided in the memory cell region, where element isolation grooves 6 for these memory cell transistors are narrow and shallow.

Abstract: A semiconductor device includes: a SOI substrate; a semiconductor element having first and second impurity layers disposed in an active layer of the SOI substrate, the second impurity layer surrounding the first impurity layer; and multiple first and second conductive type regions disposed in a part of the active layer adjacent to an embedded insulation film of the SOI substrate. The first and second conductive type regions are alternately arranged. The first and second conductive type regions have a layout, which corresponds to the semiconductor element.

Abstract: Semiconductor devices containing a CVD BPSG layer and an undoped CVD oxide cap layer are described. The cap layer can be any silicon oxide material with a thickness between about 50 ? and about 350 ?. The cap layer may be formed using a low temperature CVD process that is controlled for density by adjusting the amount of silicon precursor in the gas-phase. In some embodiments, the cap layer is deposited on the BPSG layer followed immediately by the BPSG film deposition prior to any annealing of the BPSG layer. The cap layer may prevent dopant out-diffusion and/or out-gassing during storage and high-temperature annealing, and moisture penetration into the BPSG layer, as well as suppress defect nucleation on the as-deposited BPSG surface and defect formation during high temperature annealing, while still allowing flow ability of the BPSG layer. Other embodiments are also described.

Abstract: An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.

Abstract: A method of double patterning a semiconductor structure with a single material which after patterning becomes a permanent part of the semiconductor structure. More specifically, a method to form a patterned semiconductor structure with small features is provided which are difficult to obtain using conventional exposure lithographic processes. The method of the present invention includes the use of patternable low-k materials which after patterning remain as a low-k dielectric material within the semiconductor structure. The method is useful in forming semiconductor interconnect structures in which the patternable low-k materials after patterning and curing become a permanent element, e.g., a patterned interlayer low-k material, of the interconnect structure.

Abstract: III-nitride materials are used to form isolation structures in high voltage ICs to isolate low voltage and high voltage functions on a monolithic power IC. Critical performance parameters are improved using III-nitride materials, due to the improved breakdown performance and thermal performance available in III-nitride semiconductor materials. An isolation structure may include a dielectric layer that is epitaxially grown using a III-nitride material to provide a simplified manufacturing process. The process permits the use of planar manufacturing technology to avoid additional manufacturing costs. High voltage power ICs have improved performance in a smaller package in comparison to corresponding silicon structures.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high resistivity substrate and a buried inductor formed directly in the high resistivity substrate and devoid of an insulating layer therebetween.

Abstract: A thin silicon-rich nitride film (e.g., having a thickness in the range of around 100A to 10000A) deposited using low-pressure chemical vapor deposition (LPCVD) is used for etch stop during vapor HF etching in various MEMS wafer fabrication processes and devices. The LPCVD silicon-rich nitride film may replace, or be used in combination with, a LPCVD stoichiometric nitride layer in many existing MEMS fabrication processes and devices. The LPCVD silicon-rich nitride film is deposited at high temperatures (e.g., typically around 650-900 degrees C.). Such a LPCVD silicon-rich nitride film generally has enhanced etch selectivity to vapor HF and other harsh chemical environments compared to stoichiometric silicon nitride and therefore a thinner layer typically can be used as an embedded etch stop layer in various MEMS wafer fabrication processes and devices and particularly for vapor HF etching processes, saving time and money in the fabrication process.

Abstract: Circuits including a laterally diffused output driver transistor and a distinct device configured to provide electrostatic discharge (ESD) protection for the laterally diffused output driver transistor are presented. In general, the device configured to provide ESD protection includes a drain extended metal oxide semiconductor transistor (DEMOS) transistor configured to breakdown at a lower voltage than a breakdown voltage of the laterally diffused output driver transistor. The laterally diffused output driver transistor may be a pull-down or a pull-up output driver transistor. The device also includes a silicon controlled rectifier (SCR) configured to inject charge within a semiconductor layer of the circuit upon breakdown of the DEMOS transistor. Moreover, the device includes a region configured to collect the charge injected from the SCR and further includes an ohmic contact region configured to at least partially affect the holding voltage of the SCR.

Abstract: A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high Ohmic region and at least an insulating structure is provided insulating the first well from the second well. The insulating structure extends through the buried high Ohmic region and includes a conductive plug in Ohmic contact with the first semiconductor region. A method for forming an integrated semiconductor device is also provided.

Abstract: An integrated circuit structure includes a semiconductor substrate of a first conductivity type; a depletion region in the semiconductor substrate; and a deep well region substantially enclosed by the depletion region. The deep well region is of a second conductivity type opposite the first conductivity type, and includes a first portion directly over the deep well region and a second portion directly under the deep well region. A transmission line is directly over the depletion region.

Abstract: A semiconductor device may include, but is not limited to, first and second well regions, and a well isolation region isolating the first and second well regions. The first and second well regions each may include an active region, a device isolation groove that defines the active region, and a device isolation insulating film that fills the device isolation groove. The first and second well regions may include first and second well layers, respectively. The well isolation region may include a well isolation groove, a well isolation insulating film that fills the well isolation groove, and a diffusion stopper layer disposed under a bottom of the well isolation groove. The first and second well layers have first and second bottoms respectively, which are deeper in depth than a bottom of the device isolation groove and shallower in depth than the bottom of the well isolation groove.

Abstract: Trench-generated device structures fabricated using a semiconductor-on-insulator (SOI) wafer, design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, as well as methods for fabricating trench-generated device structures. The device structure includes a trench extending through the semiconductor and insulator layers of the SOI wafer and into the underlying semiconductor substrate, and a first doped region in the semiconductor substrate. The doped region, which extends about the trench, has a second conductivity type opposite to the first conductivity type. The device structure further includes a first contact extending from the top surface through the semiconductor and insulator layers to a portion of the semiconductor substrate outside of the doped region, and a second contact extending from the top surface through the semiconductor and insulator layers to the doped region in the semiconductor substrate.

Abstract: A method of fabricating a flash memory and an isolating structure applied to a flash memory is provided. The feature of the method lies in a T-shaped shallow trench isolation (STI). The T-shaped STI has a widened cap covering on a substrate and a tapered bottom embedded in the substrate. The widened cap of the T-shaped STI can provide a high process widow when fabricating the floating gate wings, and the product yield will thereby be increased.

Abstract: An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate.

Abstract: A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred embodiment, a transition metal oxide is deposited over a bottom electrode and implanted with a dopant. In a preferred embodiment, the metal oxide is hafnium oxide or zirconium oxide and the dopant is nitrogen. The dopant can convert the crystal structure of the hafnium oxide or zirconium oxide to a tetragonal structure and increase the dielectric constant of the metal oxide.

Abstract: An embodiment of the present invention is a technique to provide a dielectric film material with controllable coefficient of thermal expansion (CTE). A first compound containing a first liquid crystalline component is formed. The first compound is cast into a first film. The first film is oriented in an magnetic or electromagnetic field in a first direction. The first film is cured at a first temperature.

Abstract: Issue Providing a silicon film which can prevent damage of electronic devices formed on a substrate from occurrence, can prevent apparatus arrangement from becoming large-scale one, can improve coherency of a silicon thin film to a substrate, and is hardly happened crack and/or flaking, and providing a method for forming the silicon thin film. Solving Means A method for forming a silicon thin film according to the present invention is a method for forming a silicon thin film having isolation function or barrier function, on a substrate K using CVD method, and comprises a step for forming a first thin film on the substrate using plasma CVD method employing gas containing hydrogen element and a gas containing silicon element; a step for forming a second thin film using plasma CVD method employing a gas containing nitrogen element and a gas containing silicon element; and a step for forming a third thin film using plasma CVD method employing a gas containing oxygen element and a gas containing silicon element.

Abstract: A doped semiconductor region having a same conductivity type as a bottom semiconductor layer is formed underneath a buried insulator layer in a bottom semiconductor layer of a semiconductor-on-insulator (SOI) substrate. At least one conductive via structure is formed, which extends from a interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to the doped semiconductor region. The shallow trench isolation structure laterally abuts at least one field effect transistor that functions as a radio frequency (RF) switch. During operation, the doped semiconductor region is biased at a voltage that keeps an induced charge layer within the bottom semiconductor layer in a depletion mode and avoids an accumulation mode. Elimination of electrical charges in an accumulation mode during half of each frequency cycle reduces harmonic generation and signal distortion in the RF switch.

Abstract: A structure including at least one electronic component formed in a semiconductor stack comprising a heavily-doped buried silicon layer of a first conductivity type extending on a lightly-doped silicon substrate of a second conductivity type and a vertical insulating trench surrounding the component. The trench penetrates, into the silicon substrate, under the silicon layer, down to a depth greater than the thickness of the space charge region in the silicon substrate.

Abstract: Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.

Abstract: A passivation structure and fabricating method thereof includes providing a chip having a main die region and a scribe line region defined thereon and a plurality of metal pads respectively positioned in the main die region and the scribe line region, forming a first patterned passivation layer having a plurality of first openings and second openings respectively exposing the metal pads in the main die region and the scribe line region on the chip, and forming a second patterned passivation layer filling the first openings in the scribe line region and having a plurality of third openings corresponding to the first openings thus exposing the metal pads in the main die region.

Abstract: An RESURF region is formed so as to surround a high-potential logic region with an isolation region interposed therebetween, in which a sense resistance and a first logic circuit which are applied with a high potential are formed in high-potential logic region. On the outside of RESURF region, a second logic circuit region is formed, which is applied with the driving voltage level required for driving a second logic circuit with respect to the ground potential. In RESURF region, a drain electrode of a field-effect transistor is formed along the inner periphery, and a source electrode is formed along the outer periphery. Furthermore, a polysilicon resistance connected to sense resistance is formed in the shape of a spiral from the inner peripheral side toward the outer peripheral side.

Abstract: The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.

Abstract: Disclosed is a silicon-containing film-forming material which contains an organosilane compound represented by the following general formula (1). (In the formula, R1-R4 may be the same or different and represent a hydrogen atom, an alkyl group having 1-4 carbon atoms, a vinyl group or a phenyl group; R5 represents an alkyl group having 1-4 carbon atoms, an acetyl group or a phenyl group; n represents an integer of 1-3; and m represents an integer of 1-2.

Abstract: In sophisticated metallization systems, air gaps may be formed on the basis of a self-aligned patterning regime during which the conductive cap material of metal lines may be protected by providing one or more materials, which may subsequently be removed. Consequently, the etch behavior and the electrical characteristics of metal lines during the self-aligned patterning regime may be individually adjusted.

Abstract: According to the present invention, it is possible to isolate elements from each other without formation of STI and integrate the elements at a high density. A step is formed on a surface of a silicon substrate so as to provide different surfaces. Transistors are formed on the respective different surfaces. The transistors are insulated from each other by a silicon layer and an insulating sidewall. Since no STI is formed between the transistors, it is possible to integrate the transistors at a high density.

Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

Abstract: A semiconductor substrate is a semiconductor substrate used when an SOI substrate having an SOI structure is manufactured, in which a silicon oxide film and a silicon single crystal layer are formed on the surface of a silicon substrate. A region containing no nitrogen, which is made of a silicon single crystal layer with a thickness of 10 ?m or less, is formed in the vicinity of the surface, and the nitrogen concentration of a portion excluding the region, that is, the region containing nitrogen, is in a range of 1×1013 to 5×1015 atoms/cm3.

Abstract: This invention is directed to offer a technology that makes it possible to form desired bump electrodes easily when the bump electrodes are to be formed at locations lowered by a step. There is formed an isolation layer 12 to isolate each of bump electrode forming regions 11. The isolation layer 12 is a resist layer, for example, and is formed by exposure and development processes, for example. Each of the bump electrode forming regions 11 is surrounded by the isolation layer 12 and a protection layer 10 that covers a side surface of a semiconductor substrate 2. Then, a printing mask 16 that has openings 15 at locations corresponding to the bump electrode forming regions 11 is placed above the semiconductor substrate 2. Next, solder 17 in paste form is applied to the printing mask 16. Then the solder 17 is applied to a metal layer 9 by moving a squeeze 18 at a constant speed. Bump electrodes 19 are obtained by heating, melting and re-crystallizing the solder 17 after removing the printing mask 16.

Abstract: There is a method of forming a contact post and surrounding isolation trench in a semiconductor-on-insulator (SOI) substrate. The method comprises etching a contact hole and surrounding isolation trench from an active layer of the substrate to the insulating layer, masking the trench and further etching the contact hole to the base substrate layer, filling the trench and contact hole with undoped intrinsic polysilicon and then performing a doping process in respect of the polysilicon material filling the contact hole so as to form in situ a highly doped contact post, while the material filling the isolation trench remains non-conductive. The isolation trench and contact post are formed substantially simultaneously so as to avoid undue interference with the device fabrication process.