Abstract: A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.

Abstract: A silicon-on-insulator wafer (10). The SOI wafer (10) comprises a top silicon layer (6), a silicon substrate (4), and an oxide insulator layer (2) disposed across the wafer (10) and between the silicon substrate (4) and the top silicon layer (6). The oxide insulator layer (2) has at least one of a contoured top surface (8a, 8b, 8c, 8d, 8e) and a contoured bottom surface (12e). Also provided are processes for manufacturing such a SOI wafer (10).

Abstract: In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in contact with the whole of the opposed surfaces between the four source regions in such a manner that the channel region formed under the gate electrode is divided across the channel length. A body-tied region containing N-type impurities relatively high in concentration is arranged in contact with the side surface of the source region opposite to the gate electrode, and the potential of the body region is fixed through the well region from the body-tied region.

Abstract: A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.

Abstract: Integrated circuit (1) comprising a substrate (2), an active component (13) above the substrate (2), a cavity (14) surrounding partially the active component (13), a low dielectric region (15) surrounding partially the cavity (14) and a protective barrier (16) arranged around the low dielectric region (15).

Abstract: A novel multi-functional linear siloxane compound, a siloxane polymer prepared from the siloxane compound, and a process for forming a dielectric film by using the siloxane polymer. The linear siloxane polymer has enhanced mechanical properties (e.g., modulus), superior thermal stability, a low carbon content and a low hygroscopicity and is prepared by the homopolymerization of the linear siloxane compound or the copolymerization of the linear siloxane compound with another monomer. A dielectric film can be produced by heat-curing a coating solution containing the siloxane polymer which is highly reactive. The siloxane polymer prepared from the siloxane compound not only has satisfactory mechanical properties, thermal stability and crack resistance, but also exhibits a low hygroscopicity and excellent compatibility with pore-forming materials, which leads to a low dielectric constant.

Abstract: A memory cell transistor comprises: an active region, the active region being elongated in a first direction of extension; a tunnel layer on the active region, the tunnel layer comprising a first tunnel insulating layer, a second tunnel insulating layer on the first tunnel insulating layer and a third tunnel insulating layer on the second tunnel insulating layer; a charge storage layer on the tunnel layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer, the control gate electrode being elongated in a second direction of extension that is transverse the first direction of extension, the active region having a first width in the second direction of extension, the second tunnel insulating layer having a second width in the second direction of extension, the second width being different than the first width.

Abstract: Issue Providing a silicon film which can prevent damage of electronic devices formed on a substrate from occurrence, can prevent apparatus arrangement from becoming large-scale one, can improve coherency of a silicon thin film to a substrate, and is hardly happened crack and/or flaking, and providing a method for forming the silicon thin film. Solving Means A method for forming a silicon thin film according to the present invention is a method for forming a silicon thin film having isolation function or barrier function, on a substrate K using CVD method, and comprises a step for forming a first thin film on the substrate using plasma CVD method employing gas containing hydrogen element and a gas containing silicon element; a step for forming a second thin film using plasma CVD method employing a gas containing nitrogen element and a gas containing silicon element; and a step for forming a third thin film using plasma CVD method employing a gas containing oxygen element and a gas containing silicon element.

Abstract: An isolation layer of a semiconductor device, and a method of manufacturing the same, may include a trench formed in a semiconductor substrate, a first liner protective layer formed along an inner surface of the trench, a low-K material pattern formed over the first liner protective layer filling the trench, a recess formed over the low-K material pattern such that an upper sidewall of the first liner protective layer is exposed, and a second liner protective layer formed in the recess preventing the low-K material pattern from being exposed.

Abstract: The present invention concerns a process for the preparation of a silicone coating of low dielectric constant, comprising the following essential steps: a) a film-forming silicone composition is deposited on the surface of a substrate, said silicone composition comprising: (i) at least one crosslinkable film-forming silicone resin, (ii) at least one ?,?-hydroxylated, essentially linear silicone oil capable of degrading under the action of heat, and (iii) at least one solvent capable of rendering the silicone resin (i) compatible with the silicone oil (ii), b) the solvent (iii) is removed, preferably by heating, and, simultaneously or sequentially, c) the film-forming silicone composition is cured by heating. The invention deals also with a silicone coating obtained by this process and an integrated circuit comprising such a silicone coating as an electrical insulator.

Abstract: A seal ring structure for an integrated circuit includes a seal ring disposed along a periphery of the integrated circuit, wherein the seal ring is divided into at least a first portion and a second portion, and wherein the second portion is positioned facing and shielding an analog and/or RF circuit block from a noise. A P+ region is provided in a P substrate and positioned under the second portion. A shallow trench isolation (STI) structure surrounds the P+ region and laterally extends underneath a conductive rampart of the second portion.

Abstract: A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body.

Abstract: In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.

Abstract: An integrated circuit includes silicon layer (2) supported by a bottom oxide layer (3), a shallow trench oxide (4) in the shallow trench (30), and a polycrystalline silicon layer (5) on the shallow trench oxide. A deep trench oxide (25) extending from the shallow trench oxide to the bottom oxide layer electrically isolates a section (2A) of the silicon layer to prevent a silicon cone defect (22) on the silicon layer (2) from causing short-circuiting of the polycrystalline silicon layer (5) to a non-isolated section of the silicon layer. The polycrystalline silicon layer (5) can form a bottom plate of a poly/metal capacitor (20) and can also form a poly interconnect conductor (5A).

Abstract: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length.

Abstract: A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.

Abstract: A trench isolation having a sidewall and bottom implanted region located within a substrate of a first conductivity type is disclosed. The sidewall and bottom implanted region is formed by an angled implant, a 90 degree implant, or a combination of an angled implant and a 90 degree implant, of dopants of the first conductivity type. The sidewall and bottom implanted region located adjacent the trench isolation reduces surface leakage and dark current.

Abstract: A MOSFET switch which has a low surface electric field at an edge termination area, and also has increased breakdown voltage. The MOSFET switch has a new edge termination structure employing an N-P-N sandwich structure. The MOSFET switch also has a polysilicon field plate configuration operative to enhance any spreading of any depletion layer located at an edge of a main PN junction of the N-P-N sandwich structure.

Abstract: An active barrier structure has a p-type region and an n-type region, each of which is in contact with a p-type impurity region and which are ohmic-connected to each other to attain a floating potential. A trench isolation structure is formed between an active barrier region and the other region (an output transistor formation region and a control circuit formation region). The trench isolation structure has a trench extending from the main surface of the semiconductor substrate through the n? epitaxial layer to reach the p-type impurity region. Therefore, a semiconductor device is obtained which allows the chip size to be reduced easily and is highly effective in preventing movement of electrons from the output transistor formation region to the other element formation region.

Abstract: In a power semiconductor device and a method of forming a power semiconductor device, a thin layer of semiconductor substrate is left below the drift region of a semiconductor device. A power semiconductor device has an active region that includes the drift region and has top and bottom surfaces formed in a layer provided on a semiconductor substrate. A portion of the semiconductor substrate below the active region is removed to leave a thin layer of semiconductor substrate below the drift region. Electrical terminals are provided directly or indirectly to the top surface of the active region to allow a voltage to be applied laterally across the drift region.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed.

Abstract: A method for forming a device isolation layer in a semiconductor substrate by destroying a lattice structure of the semiconductor substrate through a high-energy ion implantation process.

Abstract: The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf3N4) and hafnium oxide (HfO2) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing hafnium oxide using precursor chemicals, followed by depositing hafnium nitride using precursor chemicals, and repeating to form the laminate structure. Alternatively, the hafnium nitride may be deposited first followed by the hafnium nitride. Such a dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric in a DRAM, or a tunnel gate insulator in flash memories, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because of the reduced leakage current when compared to an electrically equivalent thickness of silicon dioxide.

Abstract: A method for forming an interlayer dielectric film by a plasma CVD method, including turning off a radio frequency power and purging with an inert gas simultaneously.

Abstract: A semiconductor device according to an embodiment of the invention includes: a semiconductor substrate; a well, having a well contact connection region, formed in the semiconductor substrate; a transistor formed on the well; an isolation region formed between the transistor formed on the well, and the well contact connection region; and a silicide layer formed between a bottom surface of the isolation region, and the semiconductor substrate.

Abstract: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.

Abstract: A semiconductor device including a substrate of a first semiconductor type with a pad region and a noise prevention structure in the substrate, on least one side of the pad region. The device further includes the substrate structure, a pad, and a dielectric layer therebetween.

Abstract: An oxide film formation method comprises steps of: generating a plasma from a gas mixture containing an inert gas and an oxidizing gas whose mixing ratio to the inert gas is higher than 0, and is 0.007 or lower; and forming an oxide film on a surface of a silicon substrate by using the plasma.

Abstract: A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.

Abstract: In a method of manufacturing a semiconductor memory device, an opening is made in a part of an insulating film formed on a silicon substrate. An amorphous silicon thin film is formed on the insulating film in which the opening has been made and inside the opening. Then, a monocrystal is solid-phase-grown in the amorphous silicon thin film, with the opening as a seed, thereby forming a monocrystalline silicon layer. Then, the monocrystalline silicon layer is heat-treated in an oxidizing atmosphere, thereby thinning the monocrystalline silicon layer and reducing the defect density. Then, a memory cell array is formed on the monocrystalline silicon layer which has been thinned and whose defect density has been reduced.

Abstract: Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.

Abstract: A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region.

Abstract: In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts.

Abstract: An integrated circuit (IC) includes one or more silicon-on-insulator (SOI) transistors. Each SOI transistor includes a first source region, a second source region, a drain region, a body contact region, a gate, and first and second isolation regions. The body contact region couples electrically to a body of the SOI transistor. The gate controls current flow between the first and second source regions and a drain region of the transistor. The first isolation region is disposed between the first source region and the body contact region. The second isolation region is disposed between the second source region and the body contact region.

Abstract: In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in contact with the whole of the opposed surfaces between the four source regions in such a manner that the channel region formed under the gate electrode is divided across the channel length. A body-tied region containing N-type impurities relatively high in concentration is arranged in contact with the side surface of the source region opposite to the gate electrode, and the potential of the body region is fixed through the well region from the body-tied region.

Abstract: A high resistance region may be used to isolate the body of a first transistor from a body contact.

Abstract: An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region.